1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8660"; 13 compatible = "qcom,msm8660"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "qcom,scorpion"; 22 enable-method = "qcom,gcc-msm8660"; 23 device_type = "cpu"; 24 reg = <0>; 25 next-level-cache = <&L2>; 26 }; 27 28 cpu@1 { 29 compatible = "qcom,scorpion"; 30 enable-method = "qcom,gcc-msm8660"; 31 device_type = "cpu"; 32 reg = <1>; 33 next-level-cache = <&L2>; 34 }; 35 36 L2: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x0 0x0>; 46 }; 47 48 cpu-pmu { 49 compatible = "qcom,scorpion-mp-pmu"; 50 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 51 }; 52 53 clocks { 54 cxo_board: cxo-board-clk { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <19200000>; 58 clock-output-names = "cxo_board"; 59 }; 60 61 pxo_board: pxo-board-clk { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <27000000>; 65 clock-output-names = "pxo_board"; 66 }; 67 68 sleep-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <32768>; 72 clock-output-names = "sleep_clk"; 73 }; 74 }; 75 76 soc: soc { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges; 80 compatible = "simple-bus"; 81 82 intc: interrupt-controller@2080000 { 83 compatible = "qcom,msm-8660-qgic"; 84 interrupt-controller; 85 #interrupt-cells = <3>; 86 reg = < 0x02080000 0x1000 >, 87 < 0x02081000 0x1000 >; 88 }; 89 90 timer@2000000 { 91 compatible = "qcom,scss-timer", "qcom,msm-timer"; 92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 93 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 94 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 95 reg = <0x02000000 0x100>; 96 clock-frequency = <27000000>; 97 cpu-offset = <0x40000>; 98 }; 99 100 tlmm: pinctrl@800000 { 101 compatible = "qcom,msm8660-pinctrl"; 102 reg = <0x800000 0x4000>; 103 104 gpio-controller; 105 gpio-ranges = <&tlmm 0 0 173>; 106 #gpio-cells = <2>; 107 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-controller; 109 #interrupt-cells = <2>; 110 111 }; 112 113 gcc: clock-controller@900000 { 114 compatible = "qcom,gcc-msm8660"; 115 #clock-cells = <1>; 116 #reset-cells = <1>; 117 reg = <0x900000 0x4000>; 118 clocks = <&pxo_board>, <&cxo_board>; 119 clock-names = "pxo", "cxo"; 120 }; 121 122 gsbi1: gsbi@16000000 { 123 compatible = "qcom,gsbi-v1.0.0"; 124 cell-index = <12>; 125 reg = <0x16000000 0x100>; 126 clocks = <&gcc GSBI1_H_CLK>; 127 clock-names = "iface"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 syscon-tcsr = <&tcsr>; 133 134 status = "disabled"; 135 136 gsbi1_spi: spi@16080000 { 137 compatible = "qcom,spi-qup-v1.1.1"; 138 reg = <0x16080000 0x1000>; 139 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 141 clock-names = "core", "iface"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 status = "disabled"; 145 }; 146 }; 147 148 gsbi3: gsbi@16200000 { 149 compatible = "qcom,gsbi-v1.0.0"; 150 cell-index = <12>; 151 reg = <0x16200000 0x100>; 152 clocks = <&gcc GSBI3_H_CLK>; 153 clock-names = "iface"; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges; 157 158 syscon-tcsr = <&tcsr>; 159 status = "disabled"; 160 161 gsbi3_i2c: i2c@16280000 { 162 compatible = "qcom,i2c-qup-v1.1.1"; 163 reg = <0x16280000 0x1000>; 164 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 166 clock-names = "core", "iface"; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 status = "disabled"; 170 }; 171 }; 172 173 gsbi6: gsbi@16500000 { 174 compatible = "qcom,gsbi-v1.0.0"; 175 cell-index = <12>; 176 reg = <0x16500000 0x100>; 177 clocks = <&gcc GSBI6_H_CLK>; 178 clock-names = "iface"; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 ranges; 182 status = "disabled"; 183 184 syscon-tcsr = <&tcsr>; 185 186 gsbi6_serial: serial@16540000 { 187 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 188 reg = <0x16540000 0x1000>, 189 <0x16500000 0x1000>; 190 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 192 clock-names = "core", "iface"; 193 status = "disabled"; 194 }; 195 196 gsbi6_i2c: i2c@16580000 { 197 compatible = "qcom,i2c-qup-v1.1.1"; 198 reg = <0x16580000 0x1000>; 199 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 201 clock-names = "core", "iface"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 status = "disabled"; 205 }; 206 }; 207 208 gsbi7: gsbi@16600000 { 209 compatible = "qcom,gsbi-v1.0.0"; 210 cell-index = <12>; 211 reg = <0x16600000 0x100>; 212 clocks = <&gcc GSBI7_H_CLK>; 213 clock-names = "iface"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 status = "disabled"; 218 219 syscon-tcsr = <&tcsr>; 220 221 gsbi7_serial: serial@16640000 { 222 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 223 reg = <0x16640000 0x1000>, 224 <0x16600000 0x1000>; 225 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 227 clock-names = "core", "iface"; 228 status = "disabled"; 229 }; 230 231 gsbi7_i2c: i2c@16680000 { 232 compatible = "qcom,i2c-qup-v1.1.1"; 233 reg = <0x16680000 0x1000>; 234 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 236 clock-names = "core", "iface"; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 status = "disabled"; 240 }; 241 }; 242 243 gsbi8: gsbi@19800000 { 244 compatible = "qcom,gsbi-v1.0.0"; 245 cell-index = <12>; 246 reg = <0x19800000 0x100>; 247 clocks = <&gcc GSBI8_H_CLK>; 248 clock-names = "iface"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges; 252 253 syscon-tcsr = <&tcsr>; 254 status = "disabled"; 255 256 gsbi8_i2c: i2c@19880000 { 257 compatible = "qcom,i2c-qup-v1.1.1"; 258 reg = <0x19880000 0x1000>; 259 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; 261 clock-names = "core", "iface"; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 }; 267 268 gsbi12: gsbi@19c00000 { 269 compatible = "qcom,gsbi-v1.0.0"; 270 cell-index = <12>; 271 reg = <0x19c00000 0x100>; 272 clocks = <&gcc GSBI12_H_CLK>; 273 clock-names = "iface"; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges; 277 278 syscon-tcsr = <&tcsr>; 279 280 gsbi12_serial: serial@19c40000 { 281 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 282 reg = <0x19c40000 0x1000>, 283 <0x19c00000 0x1000>; 284 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 286 clock-names = "core", "iface"; 287 status = "disabled"; 288 }; 289 290 gsbi12_i2c: i2c@19c80000 { 291 compatible = "qcom,i2c-qup-v1.1.1"; 292 reg = <0x19c80000 0x1000>; 293 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; 295 clock-names = "core", "iface"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 }; 301 302 ebi2: external-bus@1a100000 { 303 compatible = "qcom,msm8660-ebi2"; 304 #address-cells = <2>; 305 #size-cells = <1>; 306 ranges = <0 0x0 0x1a800000 0x00800000>, 307 <1 0x0 0x1b000000 0x00800000>, 308 <2 0x0 0x1b800000 0x00800000>, 309 <3 0x0 0x1d000000 0x08000000>, 310 <4 0x0 0x1c800000 0x00800000>, 311 <5 0x0 0x1c000000 0x00800000>; 312 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; 313 reg-names = "ebi2", "xmem"; 314 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; 315 clock-names = "ebi2x", "ebi2"; 316 status = "disabled"; 317 }; 318 319 ssbi: ssbi@500000 { 320 compatible = "qcom,ssbi"; 321 reg = <0x500000 0x1000>; 322 qcom,controller-type = "pmic-arbiter"; 323 }; 324 325 l2cc: clock-controller@2082000 { 326 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; 327 reg = <0x02082000 0x1000>; 328 }; 329 330 rpm: rpm@104000 { 331 compatible = "qcom,rpm-msm8660"; 332 reg = <0x00104000 0x1000>; 333 qcom,ipc = <&l2cc 0x8 2>; 334 335 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 337 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 338 interrupt-names = "ack", "err", "wakeup"; 339 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 340 clock-names = "ram"; 341 342 rpmcc: clock-controller { 343 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 344 #clock-cells = <1>; 345 clocks = <&pxo_board>; 346 clock-names = "pxo"; 347 }; 348 }; 349 350 amba { 351 compatible = "simple-bus"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges; 355 sdcc1: mmc@12400000 { 356 status = "disabled"; 357 compatible = "arm,pl18x", "arm,primecell"; 358 arm,primecell-periphid = <0x00051180>; 359 reg = <0x12400000 0x8000>; 360 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 362 clock-names = "mclk", "apb_pclk"; 363 bus-width = <8>; 364 max-frequency = <48000000>; 365 non-removable; 366 cap-sd-highspeed; 367 cap-mmc-highspeed; 368 }; 369 370 sdcc2: mmc@12140000 { 371 status = "disabled"; 372 compatible = "arm,pl18x", "arm,primecell"; 373 arm,primecell-periphid = <0x00051180>; 374 reg = <0x12140000 0x8000>; 375 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 377 clock-names = "mclk", "apb_pclk"; 378 bus-width = <8>; 379 max-frequency = <48000000>; 380 cap-sd-highspeed; 381 cap-mmc-highspeed; 382 }; 383 384 sdcc3: mmc@12180000 { 385 compatible = "arm,pl18x", "arm,primecell"; 386 arm,primecell-periphid = <0x00051180>; 387 status = "disabled"; 388 reg = <0x12180000 0x8000>; 389 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 391 clock-names = "mclk", "apb_pclk"; 392 bus-width = <4>; 393 cap-sd-highspeed; 394 cap-mmc-highspeed; 395 max-frequency = <48000000>; 396 no-1-8-v; 397 }; 398 399 sdcc4: mmc@121c0000 { 400 compatible = "arm,pl18x", "arm,primecell"; 401 arm,primecell-periphid = <0x00051180>; 402 status = "disabled"; 403 reg = <0x121c0000 0x8000>; 404 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 406 clock-names = "mclk", "apb_pclk"; 407 bus-width = <4>; 408 max-frequency = <48000000>; 409 cap-sd-highspeed; 410 cap-mmc-highspeed; 411 }; 412 413 sdcc5: mmc@12200000 { 414 compatible = "arm,pl18x", "arm,primecell"; 415 arm,primecell-periphid = <0x00051180>; 416 status = "disabled"; 417 reg = <0x12200000 0x8000>; 418 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 420 clock-names = "mclk", "apb_pclk"; 421 bus-width = <4>; 422 cap-sd-highspeed; 423 cap-mmc-highspeed; 424 max-frequency = <48000000>; 425 }; 426 }; 427 428 tcsr: syscon@1a400000 { 429 compatible = "qcom,tcsr-msm8660", "syscon"; 430 reg = <0x1a400000 0x100>; 431 }; 432 }; 433 434}; 435