1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&intc>; 20 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 clocks { 29 xo_board: xo_board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 }; 34 35 sleep_clk: sleep_clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32768>; 39 }; 40 }; 41 42 firmware { 43 scm { 44 compatible = "qcom,scm-msm8226", "qcom,scm"; 45 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 46 clock-names = "core", "bus", "iface"; 47 }; 48 }; 49 50 pmu { 51 compatible = "arm,cortex-a7-pmu"; 52 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 53 IRQ_TYPE_LEVEL_HIGH)>; 54 }; 55 56 rpm: remoteproc { 57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 58 59 master-stats { 60 compatible = "qcom,rpm-master-stats"; 61 qcom,rpm-msg-ram = <&apss_master_stats>, 62 <&mpss_master_stats>, 63 <&lpss_master_stats>, 64 <&pronto_master_stats>; 65 qcom,master-names = "APSS", 66 "MPSS", 67 "LPSS", 68 "PRONTO"; 69 }; 70 71 smd-edge { 72 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 73 qcom,ipc = <&apcs 8 0>; 74 qcom,smd-edge = <15>; 75 76 rpm_requests: rpm-requests { 77 compatible = "qcom,rpm-msm8226"; 78 qcom,smd-channels = "rpm_requests"; 79 80 rpmcc: clock-controller { 81 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 82 #clock-cells = <1>; 83 clocks = <&xo_board>; 84 clock-names = "xo"; 85 }; 86 87 rpmpd: power-controller { 88 compatible = "qcom,msm8226-rpmpd"; 89 #power-domain-cells = <1>; 90 operating-points-v2 = <&rpmpd_opp_table>; 91 92 rpmpd_opp_table: opp-table { 93 compatible = "operating-points-v2"; 94 95 rpmpd_opp_ret: opp1 { 96 opp-level = <1>; 97 }; 98 rpmpd_opp_svs_krait: opp2 { 99 opp-level = <2>; 100 }; 101 rpmpd_opp_svs_soc: opp3 { 102 opp-level = <3>; 103 }; 104 rpmpd_opp_nom: opp4 { 105 opp-level = <4>; 106 }; 107 rpmpd_opp_turbo: opp5 { 108 opp-level = <5>; 109 }; 110 rpmpd_opp_super_turbo: opp6 { 111 opp-level = <6>; 112 }; 113 }; 114 }; 115 }; 116 }; 117 }; 118 119 reserved-memory { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 smem_region: smem@3000000 { 125 reg = <0x3000000 0x100000>; 126 no-map; 127 }; 128 129 adsp_region: adsp@dc00000 { 130 reg = <0x0dc00000 0x1900000>; 131 no-map; 132 }; 133 }; 134 135 smem { 136 compatible = "qcom,smem"; 137 138 memory-region = <&smem_region>; 139 qcom,rpm-msg-ram = <&rpm_msg_ram>; 140 141 hwlocks = <&tcsr_mutex 3>; 142 }; 143 144 smp2p-adsp { 145 compatible = "qcom,smp2p"; 146 qcom,smem = <443>, <429>; 147 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 150 151 qcom,ipc = <&apcs 8 10>; 152 153 qcom,local-pid = <0>; 154 qcom,remote-pid = <2>; 155 156 adsp_smp2p_out: master-kernel { 157 qcom,entry-name = "master-kernel"; 158 #qcom,smem-state-cells = <1>; 159 }; 160 161 adsp_smp2p_in: slave-kernel { 162 qcom,entry-name = "slave-kernel"; 163 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 }; 167 }; 168 169 soc: soc { 170 compatible = "simple-bus"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges; 174 175 intc: interrupt-controller@f9000000 { 176 compatible = "qcom,msm-qgic2"; 177 reg = <0xf9000000 0x1000>, 178 <0xf9002000 0x1000>; 179 interrupt-controller; 180 #interrupt-cells = <3>; 181 }; 182 183 apcs: syscon@f9011000 { 184 compatible = "syscon"; 185 reg = <0xf9011000 0x1000>; 186 }; 187 188 sdhc_1: mmc@f9824900 { 189 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 190 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 191 reg-names = "hc", "core"; 192 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "hc_irq", "pwr_irq"; 195 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 196 <&gcc GCC_SDCC1_APPS_CLK>, 197 <&rpmcc RPM_SMD_XO_CLK_SRC>; 198 clock-names = "iface", "core", "xo"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&sdhc1_default_state>; 201 status = "disabled"; 202 }; 203 204 sdhc_2: mmc@f98a4900 { 205 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 206 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 207 reg-names = "hc", "core"; 208 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "hc_irq", "pwr_irq"; 211 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 212 <&gcc GCC_SDCC2_APPS_CLK>, 213 <&rpmcc RPM_SMD_XO_CLK_SRC>; 214 clock-names = "iface", "core", "xo"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&sdhc2_default_state>; 217 status = "disabled"; 218 }; 219 220 sdhc_3: mmc@f9864900 { 221 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 222 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 223 reg-names = "hc", "core"; 224 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "hc_irq", "pwr_irq"; 227 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 228 <&gcc GCC_SDCC3_APPS_CLK>, 229 <&rpmcc RPM_SMD_XO_CLK_SRC>; 230 clock-names = "iface", "core", "xo"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&sdhc3_default_state>; 233 status = "disabled"; 234 }; 235 236 blsp1_uart1: serial@f991d000 { 237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 238 reg = <0xf991d000 0x1000>; 239 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 241 clock-names = "core", "iface"; 242 status = "disabled"; 243 }; 244 245 blsp1_uart3: serial@f991f000 { 246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 247 reg = <0xf991f000 0x1000>; 248 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 250 clock-names = "core", "iface"; 251 status = "disabled"; 252 }; 253 254 blsp1_uart4: serial@f9920000 { 255 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 256 reg = <0xf9920000 0x1000>; 257 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 259 clock-names = "core", "iface"; 260 status = "disabled"; 261 }; 262 263 blsp1_i2c1: i2c@f9923000 { 264 status = "disabled"; 265 compatible = "qcom,i2c-qup-v2.1.1"; 266 reg = <0xf9923000 0x1000>; 267 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 269 clock-names = "core", "iface"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&blsp1_i2c1_pins>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 }; 275 276 blsp1_i2c2: i2c@f9924000 { 277 status = "disabled"; 278 compatible = "qcom,i2c-qup-v2.1.1"; 279 reg = <0xf9924000 0x1000>; 280 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 282 clock-names = "core", "iface"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&blsp1_i2c2_pins>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 }; 288 289 blsp1_i2c3: i2c@f9925000 { 290 status = "disabled"; 291 compatible = "qcom,i2c-qup-v2.1.1"; 292 reg = <0xf9925000 0x1000>; 293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 295 clock-names = "core", "iface"; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&blsp1_i2c3_pins>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 }; 301 302 blsp1_i2c4: i2c@f9926000 { 303 status = "disabled"; 304 compatible = "qcom,i2c-qup-v2.1.1"; 305 reg = <0xf9926000 0x1000>; 306 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 308 clock-names = "core", "iface"; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&blsp1_i2c4_pins>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 }; 314 315 blsp1_i2c5: i2c@f9927000 { 316 status = "disabled"; 317 compatible = "qcom,i2c-qup-v2.1.1"; 318 reg = <0xf9927000 0x1000>; 319 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 321 clock-names = "core", "iface"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&blsp1_i2c5_pins>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 328 cci: cci@fda0c000 { 329 compatible = "qcom,msm8226-cci"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0xfda0c000 0x1000>; 333 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 334 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 335 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 336 <&mmcc CAMSS_CCI_CCI_CLK>; 337 clock-names = "camss_top_ahb", 338 "cci_ahb", 339 "cci"; 340 341 pinctrl-names = "default", "sleep"; 342 pinctrl-0 = <&cci_default>; 343 pinctrl-1 = <&cci_sleep>; 344 345 status = "disabled"; 346 347 cci_i2c0: i2c-bus@0 { 348 reg = <0>; 349 clock-frequency = <400000>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 }; 353 }; 354 355 usb: usb@f9a55000 { 356 compatible = "qcom,ci-hdrc"; 357 reg = <0xf9a55000 0x200>, 358 <0xf9a55200 0x200>; 359 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 361 <&gcc GCC_USB_HS_SYSTEM_CLK>; 362 clock-names = "iface", "core"; 363 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 364 assigned-clock-rates = <75000000>; 365 resets = <&gcc GCC_USB_HS_BCR>; 366 reset-names = "core"; 367 phy_type = "ulpi"; 368 dr_mode = "otg"; 369 hnp-disable; 370 srp-disable; 371 adp-disable; 372 ahb-burst-config = <0>; 373 phy-names = "usb-phy"; 374 phys = <&usb_hs_phy>; 375 status = "disabled"; 376 #reset-cells = <1>; 377 378 ulpi { 379 usb_hs_phy: phy { 380 compatible = "qcom,usb-hs-phy-msm8226", 381 "qcom,usb-hs-phy"; 382 #phy-cells = <0>; 383 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 384 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 385 clock-names = "ref", "sleep"; 386 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 387 reset-names = "phy", "por"; 388 qcom,init-seq = /bits/ 8 <0x0 0x44 389 0x1 0x68 0x2 0x24 0x3 0x13>; 390 }; 391 }; 392 }; 393 394 gcc: clock-controller@fc400000 { 395 compatible = "qcom,gcc-msm8226"; 396 reg = <0xfc400000 0x4000>; 397 #clock-cells = <1>; 398 #reset-cells = <1>; 399 #power-domain-cells = <1>; 400 401 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 402 <&sleep_clk>; 403 clock-names = "xo", 404 "sleep_clk"; 405 }; 406 407 mmcc: clock-controller@fd8c0000 { 408 compatible = "qcom,mmcc-msm8226"; 409 reg = <0xfd8c0000 0x6000>; 410 #clock-cells = <1>; 411 #reset-cells = <1>; 412 #power-domain-cells = <1>; 413 414 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 415 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 416 <&gcc GPLL0_VOTE>, 417 <&gcc GPLL1_VOTE>, 418 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 419 <0>, 420 <0>; 421 clock-names = "xo", 422 "mmss_gpll0_vote", 423 "gpll0_vote", 424 "gpll1_vote", 425 "gfx3d_clk_src", 426 "dsi0pll", 427 "dsi0pllbyte"; 428 }; 429 430 tlmm: pinctrl@fd510000 { 431 compatible = "qcom,msm8226-pinctrl"; 432 reg = <0xfd510000 0x4000>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 gpio-ranges = <&tlmm 0 0 117>; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 439 440 blsp1_i2c1_pins: blsp1-i2c1-state { 441 pins = "gpio2", "gpio3"; 442 function = "blsp_i2c1"; 443 drive-strength = <2>; 444 bias-disable; 445 }; 446 447 blsp1_i2c2_pins: blsp1-i2c2-state { 448 pins = "gpio6", "gpio7"; 449 function = "blsp_i2c2"; 450 drive-strength = <2>; 451 bias-disable; 452 }; 453 454 blsp1_i2c3_pins: blsp1-i2c3-state { 455 pins = "gpio10", "gpio11"; 456 function = "blsp_i2c3"; 457 drive-strength = <2>; 458 bias-disable; 459 }; 460 461 blsp1_i2c4_pins: blsp1-i2c4-state { 462 pins = "gpio14", "gpio15"; 463 function = "blsp_i2c4"; 464 drive-strength = <2>; 465 bias-disable; 466 }; 467 468 blsp1_i2c5_pins: blsp1-i2c5-state { 469 pins = "gpio18", "gpio19"; 470 function = "blsp_i2c5"; 471 drive-strength = <2>; 472 bias-disable; 473 }; 474 475 cci_default: cci-default-state { 476 pins = "gpio29", "gpio30"; 477 function = "cci_i2c0"; 478 479 drive-strength = <2>; 480 bias-disable; 481 }; 482 483 cci_sleep: cci-sleep-state { 484 pins = "gpio29", "gpio30"; 485 function = "gpio"; 486 487 drive-strength = <2>; 488 bias-disable; 489 }; 490 491 sdhc1_default_state: sdhc1-default-state { 492 clk-pins { 493 pins = "sdc1_clk"; 494 drive-strength = <10>; 495 bias-disable; 496 }; 497 498 cmd-data-pins { 499 pins = "sdc1_cmd", "sdc1_data"; 500 drive-strength = <10>; 501 bias-pull-up; 502 }; 503 }; 504 505 sdhc2_default_state: sdhc2-default-state { 506 clk-pins { 507 pins = "sdc2_clk"; 508 drive-strength = <10>; 509 bias-disable; 510 }; 511 512 cmd-data-pins { 513 pins = "sdc2_cmd", "sdc2_data"; 514 drive-strength = <10>; 515 bias-pull-up; 516 }; 517 }; 518 519 sdhc3_default_state: sdhc3-default-state { 520 clk-pins { 521 pins = "gpio44"; 522 function = "sdc3"; 523 drive-strength = <8>; 524 bias-disable; 525 }; 526 527 cmd-pins { 528 pins = "gpio43"; 529 function = "sdc3"; 530 drive-strength = <8>; 531 bias-pull-up; 532 }; 533 534 data-pins { 535 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 536 function = "sdc3"; 537 drive-strength = <8>; 538 bias-pull-up; 539 }; 540 }; 541 }; 542 543 tsens: thermal-sensor@fc4a9000 { 544 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 545 reg = <0xfc4a9000 0x1000>, /* TM */ 546 <0xfc4a8000 0x1000>; /* SROT */ 547 nvmem-cells = <&tsens_mode>, 548 <&tsens_base1>, <&tsens_base2>, 549 <&tsens_s0_p1>, <&tsens_s0_p2>, 550 <&tsens_s1_p1>, <&tsens_s1_p2>, 551 <&tsens_s2_p1>, <&tsens_s2_p2>, 552 <&tsens_s3_p1>, <&tsens_s3_p2>, 553 <&tsens_s4_p1>, <&tsens_s4_p2>, 554 <&tsens_s5_p1>, <&tsens_s5_p2>, 555 <&tsens_s6_p1>, <&tsens_s6_p2>; 556 nvmem-cell-names = "mode", 557 "base1", "base2", 558 "s0_p1", "s0_p2", 559 "s1_p1", "s1_p2", 560 "s2_p1", "s2_p2", 561 "s3_p1", "s3_p2", 562 "s4_p1", "s4_p2", 563 "s5_p1", "s5_p2", 564 "s6_p1", "s6_p2"; 565 #qcom,sensors = <6>; 566 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 567 interrupt-names = "uplow"; 568 #thermal-sensor-cells = <1>; 569 }; 570 571 restart@fc4ab000 { 572 compatible = "qcom,pshold"; 573 reg = <0xfc4ab000 0x4>; 574 }; 575 576 qfprom: qfprom@fc4bc000 { 577 compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 578 reg = <0xfc4bc000 0x1000>; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 582 tsens_base1: base1@1c1 { 583 reg = <0x1c1 0x2>; 584 bits = <5 8>; 585 }; 586 587 tsens_s0_p1: s0-p1@1c2 { 588 reg = <0x1c2 0x2>; 589 bits = <5 6>; 590 }; 591 592 tsens_s1_p1: s1-p1@1c4 { 593 reg = <0x1c4 0x1>; 594 bits = <0 6>; 595 }; 596 597 tsens_s2_p1: s2-p1@1c4 { 598 reg = <0x1c4 0x2>; 599 bits = <6 6>; 600 }; 601 602 tsens_s3_p1: s3-p1@1c5 { 603 reg = <0x1c5 0x2>; 604 bits = <4 6>; 605 }; 606 607 tsens_s4_p1: s4-p1@1c6 { 608 reg = <0x1c6 0x1>; 609 bits = <2 6>; 610 }; 611 612 tsens_s5_p1: s5-p1@1c7 { 613 reg = <0x1c7 0x1>; 614 bits = <0 6>; 615 }; 616 617 tsens_s6_p1: s6-p1@1ca { 618 reg = <0x1ca 0x2>; 619 bits = <4 6>; 620 }; 621 622 tsens_base2: base2@1cc { 623 reg = <0x1cc 0x1>; 624 bits = <0 8>; 625 }; 626 627 tsens_s0_p2: s0-p2@1cd { 628 reg = <0x1cd 0x1>; 629 bits = <0 6>; 630 }; 631 632 tsens_s1_p2: s1-p2@1cd { 633 reg = <0x1cd 0x2>; 634 bits = <6 6>; 635 }; 636 637 tsens_s2_p2: s2-p2@1ce { 638 reg = <0x1ce 0x2>; 639 bits = <4 6>; 640 }; 641 642 tsens_s3_p2: s3-p2@1cf { 643 reg = <0x1cf 0x1>; 644 bits = <2 6>; 645 }; 646 647 tsens_s4_p2: s4-p2@446 { 648 reg = <0x446 0x2>; 649 bits = <4 6>; 650 }; 651 652 tsens_s5_p2: s5-p2@447 { 653 reg = <0x447 0x1>; 654 bits = <2 6>; 655 }; 656 657 tsens_s6_p2: s6-p2@44e { 658 reg = <0x44e 0x1>; 659 bits = <1 6>; 660 }; 661 662 tsens_mode: mode@44f { 663 reg = <0x44f 0x1>; 664 bits = <5 3>; 665 }; 666 }; 667 668 spmi_bus: spmi@fc4cf000 { 669 compatible = "qcom,spmi-pmic-arb"; 670 reg-names = "core", "intr", "cnfg"; 671 reg = <0xfc4cf000 0x1000>, 672 <0xfc4cb000 0x1000>, 673 <0xfc4ca000 0x1000>; 674 interrupt-names = "periph_irq"; 675 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 676 qcom,ee = <0>; 677 qcom,channel = <0>; 678 #address-cells = <2>; 679 #size-cells = <0>; 680 interrupt-controller; 681 #interrupt-cells = <4>; 682 }; 683 684 rng@f9bff000 { 685 compatible = "qcom,prng"; 686 reg = <0xf9bff000 0x200>; 687 clocks = <&gcc GCC_PRNG_AHB_CLK>; 688 clock-names = "core"; 689 }; 690 691 timer@f9020000 { 692 compatible = "arm,armv7-timer-mem"; 693 reg = <0xf9020000 0x1000>; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges; 697 698 frame@f9021000 { 699 frame-number = <0>; 700 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 702 reg = <0xf9021000 0x1000>, 703 <0xf9022000 0x1000>; 704 }; 705 706 frame@f9023000 { 707 frame-number = <1>; 708 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 709 reg = <0xf9023000 0x1000>; 710 status = "disabled"; 711 }; 712 713 frame@f9024000 { 714 frame-number = <2>; 715 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 716 reg = <0xf9024000 0x1000>; 717 status = "disabled"; 718 }; 719 720 frame@f9025000 { 721 frame-number = <3>; 722 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 723 reg = <0xf9025000 0x1000>; 724 status = "disabled"; 725 }; 726 727 frame@f9026000 { 728 frame-number = <4>; 729 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 730 reg = <0xf9026000 0x1000>; 731 status = "disabled"; 732 }; 733 734 frame@f9027000 { 735 frame-number = <5>; 736 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 737 reg = <0xf9027000 0x1000>; 738 status = "disabled"; 739 }; 740 741 frame@f9028000 { 742 frame-number = <6>; 743 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 744 reg = <0xf9028000 0x1000>; 745 status = "disabled"; 746 }; 747 }; 748 749 sram@fc190000 { 750 compatible = "qcom,msm8226-rpm-stats"; 751 reg = <0xfc190000 0x10000>; 752 }; 753 754 rpm_msg_ram: sram@fc428000 { 755 compatible = "qcom,rpm-msg-ram"; 756 reg = <0xfc428000 0x4000>; 757 758 #address-cells = <1>; 759 #size-cells = <1>; 760 ranges = <0 0xfc428000 0x4000>; 761 762 apss_master_stats: sram@150 { 763 reg = <0x150 0x14>; 764 }; 765 766 mpss_master_stats: sram@b50 { 767 reg = <0xb50 0x14>; 768 }; 769 770 lpss_master_stats: sram@1550 { 771 reg = <0x1550 0x14>; 772 }; 773 774 pronto_master_stats: sram@1f50 { 775 reg = <0x1f50 0x14>; 776 }; 777 }; 778 779 tcsr_mutex: hwlock@fd484000 { 780 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 781 reg = <0xfd484000 0x1000>; 782 #hwlock-cells = <1>; 783 }; 784 785 adsp: remoteproc@fe200000 { 786 compatible = "qcom,msm8226-adsp-pil"; 787 reg = <0xfe200000 0x100>; 788 789 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 790 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 791 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 792 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 793 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 794 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 795 796 power-domains = <&rpmpd MSM8226_VDDCX>; 797 power-domain-names = "cx"; 798 799 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 800 clock-names = "xo"; 801 802 memory-region = <&adsp_region>; 803 804 qcom,smem-states = <&adsp_smp2p_out 0>; 805 qcom,smem-state-names = "stop"; 806 807 status = "disabled"; 808 809 smd-edge { 810 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 811 812 qcom,ipc = <&apcs 8 8>; 813 qcom,smd-edge = <1>; 814 815 label = "lpass"; 816 }; 817 }; 818 819 sram@fdd00000 { 820 compatible = "qcom,msm8226-ocmem"; 821 reg = <0xfdd00000 0x2000>, 822 <0xfec00000 0x20000>; 823 reg-names = "ctrl", "mem"; 824 ranges = <0 0xfec00000 0x20000>; 825 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 826 clock-names = "core"; 827 828 #address-cells = <1>; 829 #size-cells = <1>; 830 831 gmu_sram: gmu-sram@0 { 832 reg = <0x0 0x20000>; 833 }; 834 }; 835 836 sram@fe805000 { 837 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 838 reg = <0xfe805000 0x1000>; 839 840 reboot-mode { 841 compatible = "syscon-reboot-mode"; 842 offset = <0x65c>; 843 844 mode-bootloader = <0x77665500>; 845 mode-normal = <0x77665501>; 846 mode-recovery = <0x77665502>; 847 }; 848 }; 849 850 mdss: display-subsystem@fd900000 { 851 compatible = "qcom,mdss"; 852 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 853 reg-names = "mdss_phys", "vbif_phys"; 854 855 power-domains = <&mmcc MDSS_GDSC>; 856 857 clocks = <&mmcc MDSS_AHB_CLK>, 858 <&mmcc MDSS_AXI_CLK>, 859 <&mmcc MDSS_VSYNC_CLK>; 860 clock-names = "iface", 861 "bus", 862 "vsync"; 863 864 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 865 866 interrupt-controller; 867 #interrupt-cells = <1>; 868 869 #address-cells = <1>; 870 #size-cells = <1>; 871 ranges; 872 873 status = "disabled"; 874 875 mdss_mdp: display-controller@fd900000 { 876 compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 877 reg = <0xfd900100 0x22000>; 878 reg-names = "mdp_phys"; 879 880 interrupt-parent = <&mdss>; 881 interrupts = <0>; 882 883 clocks = <&mmcc MDSS_AHB_CLK>, 884 <&mmcc MDSS_AXI_CLK>, 885 <&mmcc MDSS_MDP_CLK>, 886 <&mmcc MDSS_VSYNC_CLK>; 887 clock-names = "iface", 888 "bus", 889 "core", 890 "vsync"; 891 892 ports { 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 port@0 { 897 reg = <0>; 898 mdss_mdp_intf1_out: endpoint { 899 remote-endpoint = <&mdss_dsi0_in>; 900 }; 901 }; 902 }; 903 }; 904 905 mdss_dsi0: dsi@fd922800 { 906 compatible = "qcom,msm8226-dsi-ctrl", 907 "qcom,mdss-dsi-ctrl"; 908 reg = <0xfd922800 0x1f8>; 909 reg-names = "dsi_ctrl"; 910 911 interrupt-parent = <&mdss>; 912 interrupts = <4>; 913 914 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 915 <&mmcc PCLK0_CLK_SRC>; 916 assigned-clock-parents = <&mdss_dsi0_phy 0>, 917 <&mdss_dsi0_phy 1>; 918 919 clocks = <&mmcc MDSS_MDP_CLK>, 920 <&mmcc MDSS_AHB_CLK>, 921 <&mmcc MDSS_AXI_CLK>, 922 <&mmcc MDSS_BYTE0_CLK>, 923 <&mmcc MDSS_PCLK0_CLK>, 924 <&mmcc MDSS_ESC0_CLK>, 925 <&mmcc MMSS_MISC_AHB_CLK>; 926 clock-names = "mdp_core", 927 "iface", 928 "bus", 929 "byte", 930 "pixel", 931 "core", 932 "core_mmss"; 933 934 phys = <&mdss_dsi0_phy>; 935 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 ports { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 943 port@0 { 944 reg = <0>; 945 mdss_dsi0_in: endpoint { 946 remote-endpoint = <&mdss_mdp_intf1_out>; 947 }; 948 }; 949 950 port@1 { 951 reg = <1>; 952 mdss_dsi0_out: endpoint { 953 }; 954 }; 955 }; 956 }; 957 958 mdss_dsi0_phy: phy@fd922a00 { 959 compatible = "qcom,dsi-phy-28nm-8226"; 960 reg = <0xfd922a00 0xd4>, 961 <0xfd922b00 0x280>, 962 <0xfd922d80 0x30>; 963 reg-names = "dsi_pll", 964 "dsi_phy", 965 "dsi_phy_regulator"; 966 967 #clock-cells = <1>; 968 #phy-cells = <0>; 969 970 clocks = <&mmcc MDSS_AHB_CLK>, 971 <&rpmcc RPM_SMD_XO_CLK_SRC>; 972 clock-names = "iface", 973 "ref"; 974 }; 975 }; 976 }; 977 978 thermal-zones { 979 cpu0-thermal { 980 polling-delay-passive = <250>; 981 polling-delay = <1000>; 982 983 thermal-sensors = <&tsens 5>; 984 985 trips { 986 cpu_alert0: trip0 { 987 temperature = <75000>; 988 hysteresis = <2000>; 989 type = "passive"; 990 }; 991 992 cpu_crit0: trip1 { 993 temperature = <110000>; 994 hysteresis = <2000>; 995 type = "critical"; 996 }; 997 }; 998 }; 999 1000 cpu1-thermal { 1001 polling-delay-passive = <250>; 1002 polling-delay = <1000>; 1003 1004 thermal-sensors = <&tsens 2>; 1005 1006 trips { 1007 cpu_alert1: trip0 { 1008 temperature = <75000>; 1009 hysteresis = <2000>; 1010 type = "passive"; 1011 }; 1012 1013 cpu_crit1: trip1 { 1014 temperature = <110000>; 1015 hysteresis = <2000>; 1016 type = "critical"; 1017 }; 1018 }; 1019 }; 1020 }; 1021 1022 timer { 1023 compatible = "arm,armv7-timer"; 1024 interrupts = <GIC_PPI 2 1025 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1026 <GIC_PPI 3 1027 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1028 <GIC_PPI 4 1029 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 1030 <GIC_PPI 1 1031 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1032 }; 1033}; 1034