1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Device Tree Source for Qualcomm MDM9615 SoC 4 * 5 * Copyright (C) 2016 BayLibre, SAS. 6 * Author : Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13#include <dt-bindings/reset/qcom,gcc-mdm9615.h> 14#include <dt-bindings/mfd/qcom-rpm.h> 15#include <dt-bindings/soc/qcom,gsbi.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 model = "Qualcomm MDM9615"; 21 compatible = "qcom,mdm9615"; 22 interrupt-parent = <&intc>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a5"; 30 reg = <0>; 31 device_type = "cpu"; 32 next-level-cache = <&L2>; 33 }; 34 }; 35 36 cpu-pmu { 37 compatible = "arm,cortex-a5-pmu"; 38 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 39 }; 40 41 clocks { 42 cxo_board { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <19200000>; 46 }; 47 }; 48 49 regulators { 50 vsdcc_fixed: vsdcc-regulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "SDCC Power"; 53 regulator-min-microvolt = <2700000>; 54 regulator-max-microvolt = <2700000>; 55 regulator-always-on; 56 }; 57 }; 58 59 soc: soc { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 compatible = "simple-bus"; 64 65 L2: cache-controller@2040000 { 66 compatible = "arm,pl310-cache"; 67 reg = <0x02040000 0x1000>; 68 arm,data-latency = <2 2 0>; 69 cache-unified; 70 cache-level = <2>; 71 }; 72 73 intc: interrupt-controller@2000000 { 74 compatible = "qcom,msm-qgic2"; 75 interrupt-controller; 76 #interrupt-cells = <3>; 77 reg = <0x02000000 0x1000>, 78 <0x02002000 0x1000>; 79 }; 80 81 timer@200a000 { 82 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", 83 "qcom,msm-timer"; 84 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 85 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 86 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; 87 reg = <0x0200a000 0x100>; 88 clock-frequency = <27000000>; 89 cpu-offset = <0x80000>; 90 }; 91 92 msmgpio: pinctrl@800000 { 93 compatible = "qcom,mdm9615-pinctrl"; 94 gpio-controller; 95 gpio-ranges = <&msmgpio 0 0 88>; 96 #gpio-cells = <2>; 97 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-controller; 99 #interrupt-cells = <2>; 100 reg = <0x800000 0x4000>; 101 }; 102 103 gcc: clock-controller@900000 { 104 compatible = "qcom,gcc-mdm9615"; 105 #clock-cells = <1>; 106 #power-domain-cells = <1>; 107 #reset-cells = <1>; 108 reg = <0x900000 0x4000>; 109 }; 110 111 lcc: clock-controller@28000000 { 112 compatible = "qcom,lcc-mdm9615"; 113 reg = <0x28000000 0x1000>; 114 #clock-cells = <1>; 115 #reset-cells = <1>; 116 }; 117 118 l2cc: clock-controller@2011000 { 119 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 120 reg = <0x02011000 0x1000>; 121 }; 122 123 rng@1a500000 { 124 compatible = "qcom,prng"; 125 reg = <0x1a500000 0x200>; 126 clocks = <&gcc PRNG_CLK>; 127 clock-names = "core"; 128 assigned-clocks = <&gcc PRNG_CLK>; 129 assigned-clock-rates = <32000000>; 130 }; 131 132 gsbi2: gsbi@16100000 { 133 compatible = "qcom,gsbi-v1.0.0"; 134 cell-index = <2>; 135 reg = <0x16100000 0x100>; 136 clocks = <&gcc GSBI2_H_CLK>; 137 clock-names = "iface"; 138 status = "disabled"; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges; 142 143 gsbi2_i2c: i2c@16180000 { 144 compatible = "qcom,i2c-qup-v1.1.1"; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 reg = <0x16180000 0x1000>; 148 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 149 150 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 151 clock-names = "core", "iface"; 152 status = "disabled"; 153 }; 154 }; 155 156 gsbi3: gsbi@16200000 { 157 compatible = "qcom,gsbi-v1.0.0"; 158 cell-index = <3>; 159 reg = <0x16200000 0x100>; 160 clocks = <&gcc GSBI3_H_CLK>; 161 clock-names = "iface"; 162 status = "disabled"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges; 166 167 gsbi3_spi: spi@16280000 { 168 compatible = "qcom,spi-qup-v1.1.1"; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 reg = <0x16280000 0x1000>; 172 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 173 174 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 175 clock-names = "core", "iface"; 176 status = "disabled"; 177 }; 178 }; 179 180 gsbi4: gsbi@16300000 { 181 compatible = "qcom,gsbi-v1.0.0"; 182 cell-index = <4>; 183 reg = <0x16300000 0x100>; 184 clocks = <&gcc GSBI4_H_CLK>; 185 clock-names = "iface"; 186 status = "disabled"; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 ranges; 190 191 syscon-tcsr = <&tcsr>; 192 193 gsbi4_serial: serial@16340000 { 194 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 195 reg = <0x16340000 0x1000>, 196 <0x16300000 0x1000>; 197 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 199 clock-names = "core", "iface"; 200 status = "disabled"; 201 }; 202 }; 203 204 gsbi5: gsbi@16400000 { 205 compatible = "qcom,gsbi-v1.0.0"; 206 cell-index = <5>; 207 reg = <0x16400000 0x100>; 208 clocks = <&gcc GSBI5_H_CLK>; 209 clock-names = "iface"; 210 status = "disabled"; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 syscon-tcsr = <&tcsr>; 216 217 gsbi5_i2c: i2c@16480000 { 218 compatible = "qcom,i2c-qup-v1.1.1"; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x16480000 0x1000>; 222 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 223 224 /* QUP clock is not initialized, set rate */ 225 assigned-clocks = <&gcc GSBI5_QUP_CLK>; 226 assigned-clock-rates = <24000000>; 227 228 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 229 clock-names = "core", "iface"; 230 status = "disabled"; 231 }; 232 233 gsbi5_serial: serial@16440000 { 234 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 235 reg = <0x16440000 0x1000>, 236 <0x16400000 0x1000>; 237 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 239 clock-names = "core", "iface"; 240 status = "disabled"; 241 }; 242 }; 243 244 qcom,ssbi@500000 { 245 compatible = "qcom,ssbi"; 246 reg = <0x500000 0x1000>; 247 qcom,controller-type = "pmic-arbiter"; 248 249 pmicintc: pmic { 250 compatible = "qcom,pm8018", "qcom,pm8921"; 251 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 pwrkey@1c { 258 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; 259 reg = <0x1c>; 260 interrupt-parent = <&pmicintc>; 261 interrupts = <50 IRQ_TYPE_EDGE_RISING>, 262 <51 IRQ_TYPE_EDGE_RISING>; 263 debounce = <15625>; 264 pull-up; 265 }; 266 267 pmicmpp: mpps@50 { 268 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; 269 interrupt-controller; 270 #interrupt-cells = <2>; 271 reg = <0x50>; 272 gpio-controller; 273 #gpio-cells = <2>; 274 gpio-ranges = <&pmicmpp 0 0 6>; 275 }; 276 277 rtc@11d { 278 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; 279 interrupt-parent = <&pmicintc>; 280 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 281 reg = <0x11d>; 282 allow-set-time; 283 }; 284 285 pmicgpio: gpio@150 { 286 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; 287 reg = <0x150>; 288 interrupt-controller; 289 #interrupt-cells = <2>; 290 gpio-controller; 291 gpio-ranges = <&pmicgpio 0 0 6>; 292 #gpio-cells = <2>; 293 }; 294 }; 295 }; 296 297 sdcc1bam: dma-controller@12182000 { 298 compatible = "qcom,bam-v1.3.0"; 299 reg = <0x12182000 0x8000>; 300 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&gcc SDC1_H_CLK>; 302 clock-names = "bam_clk"; 303 #dma-cells = <1>; 304 qcom,ee = <0>; 305 }; 306 307 sdcc2bam: dma-controller@12142000 { 308 compatible = "qcom,bam-v1.3.0"; 309 reg = <0x12142000 0x8000>; 310 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&gcc SDC2_H_CLK>; 312 clock-names = "bam_clk"; 313 #dma-cells = <1>; 314 qcom,ee = <0>; 315 }; 316 317 sdcc1: mmc@12180000 { 318 status = "disabled"; 319 compatible = "arm,pl18x", "arm,primecell"; 320 arm,primecell-periphid = <0x00051180>; 321 reg = <0x12180000 0x2000>; 322 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 324 clock-names = "mclk", "apb_pclk"; 325 bus-width = <8>; 326 max-frequency = <48000000>; 327 cap-sd-highspeed; 328 cap-mmc-highspeed; 329 vmmc-supply = <&vsdcc_fixed>; 330 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 331 dma-names = "tx", "rx"; 332 assigned-clocks = <&gcc SDC1_CLK>; 333 assigned-clock-rates = <400000>; 334 }; 335 336 sdcc2: mmc@12140000 { 337 compatible = "arm,pl18x", "arm,primecell"; 338 arm,primecell-periphid = <0x00051180>; 339 status = "disabled"; 340 reg = <0x12140000 0x2000>; 341 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 343 clock-names = "mclk", "apb_pclk"; 344 bus-width = <4>; 345 cap-sd-highspeed; 346 cap-mmc-highspeed; 347 max-frequency = <48000000>; 348 no-1-8-v; 349 vmmc-supply = <&vsdcc_fixed>; 350 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; 351 dma-names = "tx", "rx"; 352 assigned-clocks = <&gcc SDC2_CLK>; 353 assigned-clock-rates = <400000>; 354 }; 355 356 tcsr: syscon@1a400000 { 357 compatible = "qcom,tcsr-mdm9615", "syscon"; 358 reg = <0x1a400000 0x100>; 359 }; 360 361 rpm: rpm@108000 { 362 compatible = "qcom,rpm-mdm9615"; 363 reg = <0x108000 0x1000>; 364 365 qcom,ipc = <&l2cc 0x8 2>; 366 367 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 369 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 370 interrupt-names = "ack", "err", "wakeup"; 371 372 regulators { 373 compatible = "qcom,rpm-pm8018-regulators"; 374 375 vin_lvs1-supply = <&pm8018_s3>; 376 377 vdd_l7-supply = <&pm8018_s4>; 378 vdd_l8-supply = <&pm8018_s3>; 379 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; 380 381 /* Buck SMPS */ 382 pm8018_s1: s1 { 383 regulator-min-microvolt = <500000>; 384 regulator-max-microvolt = <1150000>; 385 qcom,switch-mode-frequency = <1600000>; 386 bias-pull-down; 387 }; 388 389 pm8018_s2: s2 { 390 regulator-min-microvolt = <1225000>; 391 regulator-max-microvolt = <1300000>; 392 qcom,switch-mode-frequency = <1600000>; 393 bias-pull-down; 394 }; 395 396 pm8018_s3: s3 { 397 regulator-always-on; 398 regulator-min-microvolt = <1800000>; 399 regulator-max-microvolt = <1800000>; 400 qcom,switch-mode-frequency = <1600000>; 401 bias-pull-down; 402 }; 403 404 pm8018_s4: s4 { 405 regulator-min-microvolt = <2100000>; 406 regulator-max-microvolt = <2200000>; 407 qcom,switch-mode-frequency = <1600000>; 408 bias-pull-down; 409 }; 410 411 pm8018_s5: s5 { 412 regulator-always-on; 413 regulator-min-microvolt = <1350000>; 414 regulator-max-microvolt = <1350000>; 415 qcom,switch-mode-frequency = <1600000>; 416 bias-pull-down; 417 }; 418 419 /* PMOS LDO */ 420 pm8018_l2: l2 { 421 regulator-always-on; 422 regulator-min-microvolt = <1800000>; 423 regulator-max-microvolt = <1800000>; 424 bias-pull-down; 425 }; 426 427 pm8018_l3: l3 { 428 regulator-always-on; 429 regulator-min-microvolt = <1800000>; 430 regulator-max-microvolt = <1800000>; 431 bias-pull-down; 432 }; 433 434 pm8018_l4: l4 { 435 regulator-min-microvolt = <3300000>; 436 regulator-max-microvolt = <3300000>; 437 bias-pull-down; 438 }; 439 440 pm8018_l5: l5 { 441 regulator-min-microvolt = <2850000>; 442 regulator-max-microvolt = <2850000>; 443 bias-pull-down; 444 }; 445 446 pm8018_l6: l6 { 447 regulator-min-microvolt = <1800000>; 448 regulator-max-microvolt = <2850000>; 449 bias-pull-down; 450 }; 451 452 pm8018_l7: l7 { 453 regulator-min-microvolt = <1850000>; 454 regulator-max-microvolt = <1900000>; 455 bias-pull-down; 456 }; 457 458 pm8018_l8: l8 { 459 regulator-min-microvolt = <1200000>; 460 regulator-max-microvolt = <1200000>; 461 bias-pull-down; 462 }; 463 464 pm8018_l9: l9 { 465 regulator-min-microvolt = <750000>; 466 regulator-max-microvolt = <1150000>; 467 bias-pull-down; 468 }; 469 470 pm8018_l10: l10 { 471 regulator-min-microvolt = <1050000>; 472 regulator-max-microvolt = <1050000>; 473 bias-pull-down; 474 }; 475 476 pm8018_l11: l11 { 477 regulator-min-microvolt = <1050000>; 478 regulator-max-microvolt = <1050000>; 479 bias-pull-down; 480 }; 481 482 pm8018_l12: l12 { 483 regulator-min-microvolt = <1050000>; 484 regulator-max-microvolt = <1050000>; 485 bias-pull-down; 486 }; 487 488 pm8018_l13: l13 { 489 regulator-min-microvolt = <1850000>; 490 regulator-max-microvolt = <2950000>; 491 bias-pull-down; 492 }; 493 494 pm8018_l14: l14 { 495 regulator-min-microvolt = <2850000>; 496 regulator-max-microvolt = <2850000>; 497 bias-pull-down; 498 }; 499 500 /* Low Voltage Switch */ 501 pm8018_lvs1: lvs1 { 502 bias-pull-down; 503 }; 504 }; 505 }; 506 }; 507}; 508