1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 qcom,saw = <&saw_l2>; 107 }; 108 }; 109 110 cpu0_opp_table: opp-table { 111 compatible = "operating-points-v2"; 112 opp-shared; 113 114 opp-48000000 { 115 opp-hz = /bits/ 64 <48000000>; 116 clock-latency-ns = <256000>; 117 }; 118 opp-200000000 { 119 opp-hz = /bits/ 64 <200000000>; 120 clock-latency-ns = <256000>; 121 }; 122 opp-500000000 { 123 opp-hz = /bits/ 64 <500000000>; 124 clock-latency-ns = <256000>; 125 }; 126 opp-716000000 { 127 opp-hz = /bits/ 64 <716000000>; 128 clock-latency-ns = <256000>; 129 }; 130 }; 131 132 memory { 133 device_type = "memory"; 134 reg = <0x0 0x0>; 135 }; 136 137 pmu { 138 compatible = "arm,cortex-a7-pmu"; 139 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 140 IRQ_TYPE_LEVEL_HIGH)>; 141 }; 142 143 clocks { 144 sleep_clk: sleep_clk { 145 compatible = "fixed-clock"; 146 clock-frequency = <32000>; 147 #clock-cells = <0>; 148 }; 149 150 xo: xo { 151 compatible = "fixed-clock"; 152 clock-frequency = <48000000>; 153 #clock-cells = <0>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-ipq4019", "qcom,scm"; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 169 clock-frequency = <48000000>; 170 always-on; 171 }; 172 173 soc { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 compatible = "simple-bus"; 178 179 intc: interrupt-controller@b000000 { 180 compatible = "qcom,msm-qgic2"; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 reg = <0x0b000000 0x1000>, 184 <0x0b002000 0x1000>; 185 }; 186 187 gcc: clock-controller@1800000 { 188 compatible = "qcom,gcc-ipq4019"; 189 #clock-cells = <1>; 190 #reset-cells = <1>; 191 reg = <0x1800000 0x60000>; 192 clocks = <&xo>, <&sleep_clk>; 193 clock-names = "xo", "sleep_clk"; 194 }; 195 196 prng: rng@22000 { 197 compatible = "qcom,prng"; 198 reg = <0x22000 0x140>; 199 clocks = <&gcc GCC_PRNG_AHB_CLK>; 200 clock-names = "core"; 201 status = "disabled"; 202 }; 203 204 tlmm: pinctrl@1000000 { 205 compatible = "qcom,ipq4019-pinctrl"; 206 reg = <0x01000000 0x300000>; 207 gpio-controller; 208 gpio-ranges = <&tlmm 0 0 100>; 209 #gpio-cells = <2>; 210 interrupt-controller; 211 #interrupt-cells = <2>; 212 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 215 vqmmc: regulator@1948000 { 216 compatible = "qcom,vqmmc-ipq4019-regulator"; 217 reg = <0x01948000 0x4>; 218 regulator-name = "vqmmc"; 219 regulator-min-microvolt = <1500000>; 220 regulator-max-microvolt = <3000000>; 221 regulator-always-on; 222 status = "disabled"; 223 }; 224 225 sdhci: mmc@7824900 { 226 compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4"; 227 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 228 reg-names = "hc", "core"; 229 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "hc_irq", "pwr_irq"; 231 bus-width = <8>; 232 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 233 <&gcc GCC_SDCC1_APPS_CLK>, 234 <&xo>; 235 clock-names = "iface", 236 "core", 237 "xo"; 238 status = "disabled"; 239 }; 240 241 blsp_dma: dma-controller@7884000 { 242 compatible = "qcom,bam-v1.7.0"; 243 reg = <0x07884000 0x23000>; 244 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 246 clock-names = "bam_clk"; 247 #dma-cells = <1>; 248 qcom,ee = <0>; 249 status = "disabled"; 250 }; 251 252 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 253 compatible = "qcom,spi-qup-v2.2.1"; 254 reg = <0x78b5000 0x600>; 255 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 257 <&gcc GCC_BLSP1_AHB_CLK>; 258 clock-names = "core", "iface"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 262 dma-names = "tx", "rx"; 263 status = "disabled"; 264 }; 265 266 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 267 compatible = "qcom,spi-qup-v2.2.1"; 268 reg = <0x78b6000 0x600>; 269 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 271 <&gcc GCC_BLSP1_AHB_CLK>; 272 clock-names = "core", "iface"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 276 dma-names = "tx", "rx"; 277 status = "disabled"; 278 }; 279 280 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 281 compatible = "qcom,i2c-qup-v2.2.1"; 282 reg = <0x78b7000 0x600>; 283 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 285 <&gcc GCC_BLSP1_AHB_CLK>; 286 clock-names = "core", "iface"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 290 dma-names = "tx", "rx"; 291 status = "disabled"; 292 }; 293 294 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 295 compatible = "qcom,i2c-qup-v2.2.1"; 296 reg = <0x78b8000 0x600>; 297 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 299 <&gcc GCC_BLSP1_AHB_CLK>; 300 clock-names = "core", "iface"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 304 dma-names = "tx", "rx"; 305 status = "disabled"; 306 }; 307 308 cryptobam: dma-controller@8e04000 { 309 compatible = "qcom,bam-v1.7.0"; 310 reg = <0x08e04000 0x20000>; 311 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 313 clock-names = "bam_clk"; 314 #dma-cells = <1>; 315 qcom,ee = <1>; 316 qcom,controlled-remotely; 317 status = "disabled"; 318 }; 319 320 crypto: crypto@8e3a000 { 321 compatible = "qcom,crypto-v5.1"; 322 reg = <0x08e3a000 0x6000>; 323 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 324 <&gcc GCC_CRYPTO_AXI_CLK>, 325 <&gcc GCC_CRYPTO_CLK>; 326 clock-names = "iface", "bus", "core"; 327 dmas = <&cryptobam 2>, <&cryptobam 3>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 }; 331 332 acc0: power-manager@b088000 { 333 compatible = "qcom,kpss-acc-v2"; 334 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 335 }; 336 337 acc1: power-manager@b098000 { 338 compatible = "qcom,kpss-acc-v2"; 339 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 340 }; 341 342 acc2: power-manager@b0a8000 { 343 compatible = "qcom,kpss-acc-v2"; 344 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 345 }; 346 347 acc3: power-manager@b0b8000 { 348 compatible = "qcom,kpss-acc-v2"; 349 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 350 }; 351 352 saw0: power-manager@b089000 { 353 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 354 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 355 }; 356 357 saw1: power-manager@b099000 { 358 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 359 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 360 }; 361 362 saw2: power-manager@b0a9000 { 363 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 364 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 365 }; 366 367 saw3: power-manager@b0b9000 { 368 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 369 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 370 }; 371 372 saw_l2: power-manager@b012000 { 373 compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; 374 reg = <0xb012000 0x1000>; 375 }; 376 377 blsp1_uart1: serial@78af000 { 378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 379 reg = <0x78af000 0x200>; 380 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 381 status = "disabled"; 382 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 383 <&gcc GCC_BLSP1_AHB_CLK>; 384 clock-names = "core", "iface"; 385 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 386 dma-names = "tx", "rx"; 387 }; 388 389 blsp1_uart2: serial@78b0000 { 390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 391 reg = <0x78b0000 0x200>; 392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 393 status = "disabled"; 394 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 395 <&gcc GCC_BLSP1_AHB_CLK>; 396 clock-names = "core", "iface"; 397 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 398 dma-names = "tx", "rx"; 399 }; 400 401 watchdog: watchdog@b017000 { 402 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; 403 reg = <0xb017000 0x40>; 404 clocks = <&sleep_clk>; 405 timeout-sec = <10>; 406 status = "disabled"; 407 }; 408 409 restart@4ab000 { 410 compatible = "qcom,pshold"; 411 reg = <0x4ab000 0x4>; 412 }; 413 414 pcie0: pcie@40000000 { 415 compatible = "qcom,pcie-ipq4019"; 416 reg = <0x40000000 0xf1d>, 417 <0x40000f20 0xa8>, 418 <0x80000 0x2000>, 419 <0x40100000 0x1000>; 420 reg-names = "dbi", "elbi", "parf", "config"; 421 device_type = "pci"; 422 linux,pci-domain = <0>; 423 bus-range = <0x00 0xff>; 424 num-lanes = <1>; 425 #address-cells = <3>; 426 #size-cells = <2>; 427 428 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 429 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 430 431 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "msi"; 433 #interrupt-cells = <1>; 434 interrupt-map-mask = <0 0 0 0x7>; 435 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 436 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 437 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 438 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 439 clocks = <&gcc GCC_PCIE_AHB_CLK>, 440 <&gcc GCC_PCIE_AXI_M_CLK>, 441 <&gcc GCC_PCIE_AXI_S_CLK>; 442 clock-names = "aux", 443 "master_bus", 444 "slave_bus"; 445 446 resets = <&gcc PCIE_AXI_M_ARES>, 447 <&gcc PCIE_AXI_S_ARES>, 448 <&gcc PCIE_PIPE_ARES>, 449 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 450 <&gcc PCIE_AXI_S_XPU_ARES>, 451 <&gcc PCIE_PARF_XPU_ARES>, 452 <&gcc PCIE_PHY_ARES>, 453 <&gcc PCIE_AXI_M_STICKY_ARES>, 454 <&gcc PCIE_PIPE_STICKY_ARES>, 455 <&gcc PCIE_PWR_ARES>, 456 <&gcc PCIE_AHB_ARES>, 457 <&gcc PCIE_PHY_AHB_ARES>; 458 reset-names = "axi_m", 459 "axi_s", 460 "pipe", 461 "axi_m_vmid", 462 "axi_s_xpu", 463 "parf", 464 "phy", 465 "axi_m_sticky", 466 "pipe_sticky", 467 "pwr", 468 "ahb", 469 "phy_ahb"; 470 471 status = "disabled"; 472 473 pcie@0 { 474 device_type = "pci"; 475 reg = <0x0 0x0 0x0 0x0 0x0>; 476 bus-range = <0x01 0xff>; 477 478 #address-cells = <3>; 479 #size-cells = <2>; 480 ranges; 481 }; 482 }; 483 484 qpic_bam: dma-controller@7984000 { 485 compatible = "qcom,bam-v1.7.0"; 486 reg = <0x7984000 0x1a000>; 487 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&gcc GCC_QPIC_CLK>; 489 clock-names = "bam_clk"; 490 #dma-cells = <1>; 491 qcom,ee = <0>; 492 status = "disabled"; 493 }; 494 495 nand: nand-controller@79b0000 { 496 compatible = "qcom,ipq4019-nand"; 497 reg = <0x79b0000 0x1000>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&gcc GCC_QPIC_CLK>, 501 <&gcc GCC_QPIC_AHB_CLK>; 502 clock-names = "core", "aon"; 503 504 dmas = <&qpic_bam 0>, 505 <&qpic_bam 1>, 506 <&qpic_bam 2>; 507 dma-names = "tx", "rx", "cmd"; 508 status = "disabled"; 509 510 nand@0 { 511 reg = <0>; 512 513 nand-ecc-strength = <4>; 514 nand-ecc-step-size = <512>; 515 nand-bus-width = <8>; 516 }; 517 }; 518 519 wifi0: wifi@a000000 { 520 compatible = "qcom,ipq4019-wifi"; 521 reg = <0xa000000 0x200000>; 522 resets = <&gcc WIFI0_CPU_INIT_RESET>, 523 <&gcc WIFI0_RADIO_SRIF_RESET>, 524 <&gcc WIFI0_RADIO_WARM_RESET>, 525 <&gcc WIFI0_RADIO_COLD_RESET>, 526 <&gcc WIFI0_CORE_WARM_RESET>, 527 <&gcc WIFI0_CORE_COLD_RESET>; 528 reset-names = "wifi_cpu_init", "wifi_radio_srif", 529 "wifi_radio_warm", "wifi_radio_cold", 530 "wifi_core_warm", "wifi_core_cold"; 531 clocks = <&gcc GCC_WCSS2G_CLK>, 532 <&gcc GCC_WCSS2G_REF_CLK>, 533 <&gcc GCC_WCSS2G_RTC_CLK>; 534 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 535 "wifi_wcss_rtc"; 536 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 550 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 551 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 552 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-names = "msi0", "msi1", "msi2", "msi3", 554 "msi4", "msi5", "msi6", "msi7", 555 "msi8", "msi9", "msi10", "msi11", 556 "msi12", "msi13", "msi14", "msi15", 557 "legacy"; 558 status = "disabled"; 559 }; 560 561 wifi1: wifi@a800000 { 562 compatible = "qcom,ipq4019-wifi"; 563 reg = <0xa800000 0x200000>; 564 resets = <&gcc WIFI1_CPU_INIT_RESET>, 565 <&gcc WIFI1_RADIO_SRIF_RESET>, 566 <&gcc WIFI1_RADIO_WARM_RESET>, 567 <&gcc WIFI1_RADIO_COLD_RESET>, 568 <&gcc WIFI1_CORE_WARM_RESET>, 569 <&gcc WIFI1_CORE_COLD_RESET>; 570 reset-names = "wifi_cpu_init", "wifi_radio_srif", 571 "wifi_radio_warm", "wifi_radio_cold", 572 "wifi_core_warm", "wifi_core_cold"; 573 clocks = <&gcc GCC_WCSS5G_CLK>, 574 <&gcc GCC_WCSS5G_REF_CLK>, 575 <&gcc GCC_WCSS5G_RTC_CLK>; 576 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 577 "wifi_wcss_rtc"; 578 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 591 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 592 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 593 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 594 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 595 interrupt-names = "msi0", "msi1", "msi2", "msi3", 596 "msi4", "msi5", "msi6", "msi7", 597 "msi8", "msi9", "msi10", "msi11", 598 "msi12", "msi13", "msi14", "msi15", 599 "legacy"; 600 status = "disabled"; 601 }; 602 603 mdio: mdio@90000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "qcom,ipq4019-mdio"; 607 reg = <0x90000 0x64>; 608 status = "disabled"; 609 610 ethernet-phy-package@0 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 compatible = "qcom,qca8075-package"; 614 reg = <0>; 615 616 qcom,tx-drive-strength-milliwatt = <300>; 617 618 ethphy0: ethernet-phy@0 { 619 reg = <0>; 620 }; 621 622 ethphy1: ethernet-phy@1 { 623 reg = <1>; 624 }; 625 626 ethphy2: ethernet-phy@2 { 627 reg = <2>; 628 }; 629 630 ethphy3: ethernet-phy@3 { 631 reg = <3>; 632 }; 633 634 ethphy4: ethernet-phy@4 { 635 reg = <4>; 636 }; 637 }; 638 }; 639 640 usb3_ss_phy: usb-phy@9a000 { 641 compatible = "qcom,usb-ss-ipq4019-phy"; 642 #phy-cells = <0>; 643 reg = <0x9a000 0x800>; 644 reg-names = "phy_base"; 645 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 646 reset-names = "por_rst"; 647 status = "disabled"; 648 }; 649 650 usb3_hs_phy: usb-phy@a6000 { 651 compatible = "qcom,usb-hs-ipq4019-phy"; 652 #phy-cells = <0>; 653 reg = <0xa6000 0x40>; 654 reg-names = "phy_base"; 655 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 656 reset-names = "por_rst", "srif_rst"; 657 status = "disabled"; 658 }; 659 660 usb3: usb@8af8800 { 661 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 662 reg = <0x8af8800 0x100>; 663 #address-cells = <1>; 664 #size-cells = <1>; 665 clocks = <&gcc GCC_USB3_MASTER_CLK>, 666 <&gcc GCC_USB3_SLEEP_CLK>, 667 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 668 clock-names = "core", "sleep", "mock_utmi"; 669 ranges; 670 status = "disabled"; 671 672 usb3_dwc: usb@8a00000 { 673 compatible = "snps,dwc3"; 674 reg = <0x8a00000 0xf8000>; 675 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 676 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 677 phy-names = "usb2-phy", "usb3-phy"; 678 dr_mode = "host"; 679 }; 680 }; 681 682 usb2_hs_phy: usb-phy@a8000 { 683 compatible = "qcom,usb-hs-ipq4019-phy"; 684 #phy-cells = <0>; 685 reg = <0xa8000 0x40>; 686 reg-names = "phy_base"; 687 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 688 reset-names = "por_rst", "srif_rst"; 689 status = "disabled"; 690 }; 691 692 usb2: usb@60f8800 { 693 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 694 reg = <0x60f8800 0x100>; 695 #address-cells = <1>; 696 #size-cells = <1>; 697 clocks = <&gcc GCC_USB2_MASTER_CLK>, 698 <&gcc GCC_USB2_SLEEP_CLK>, 699 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 700 clock-names = "core", "sleep", "mock_utmi"; 701 ranges; 702 status = "disabled"; 703 704 usb@6000000 { 705 compatible = "snps,dwc3"; 706 reg = <0x6000000 0xf8000>; 707 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 708 phys = <&usb2_hs_phy>; 709 phy-names = "usb2-phy"; 710 dr_mode = "host"; 711 }; 712 }; 713 }; 714}; 715