1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&l2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 }; 58 59 cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 enable-method = "qcom,kpss-acc-v2"; 63 next-level-cache = <&l2>; 64 qcom,acc = <&acc1>; 65 qcom,saw = <&saw1>; 66 reg = <0x1>; 67 clocks = <&gcc GCC_APPS_CLK_SRC>; 68 clock-frequency = <0>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 }; 71 72 cpu@2 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a7"; 75 enable-method = "qcom,kpss-acc-v2"; 76 next-level-cache = <&l2>; 77 qcom,acc = <&acc2>; 78 qcom,saw = <&saw2>; 79 reg = <0x2>; 80 clocks = <&gcc GCC_APPS_CLK_SRC>; 81 clock-frequency = <0>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 }; 84 85 cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a7"; 88 enable-method = "qcom,kpss-acc-v2"; 89 next-level-cache = <&l2>; 90 qcom,acc = <&acc3>; 91 qcom,saw = <&saw3>; 92 reg = <0x3>; 93 clocks = <&gcc GCC_APPS_CLK_SRC>; 94 clock-frequency = <0>; 95 operating-points-v2 = <&cpu0_opp_table>; 96 }; 97 98 l2: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 qcom,saw = <&saw_l2>; 103 }; 104 }; 105 106 cpu0_opp_table: opp-table { 107 compatible = "operating-points-v2"; 108 opp-shared; 109 110 opp-48000000 { 111 opp-hz = /bits/ 64 <48000000>; 112 clock-latency-ns = <256000>; 113 }; 114 opp-200000000 { 115 opp-hz = /bits/ 64 <200000000>; 116 clock-latency-ns = <256000>; 117 }; 118 opp-500000000 { 119 opp-hz = /bits/ 64 <500000000>; 120 clock-latency-ns = <256000>; 121 }; 122 opp-716000000 { 123 opp-hz = /bits/ 64 <716000000>; 124 clock-latency-ns = <256000>; 125 }; 126 }; 127 128 memory { 129 device_type = "memory"; 130 reg = <0x0 0x0>; 131 }; 132 133 pmu { 134 compatible = "arm,cortex-a7-pmu"; 135 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 136 IRQ_TYPE_LEVEL_HIGH)>; 137 }; 138 139 clocks { 140 sleep_clk: sleep_clk { 141 compatible = "fixed-clock"; 142 clock-frequency = <32000>; 143 #clock-cells = <0>; 144 }; 145 146 xo: xo { 147 compatible = "fixed-clock"; 148 clock-frequency = <48000000>; 149 #clock-cells = <0>; 150 }; 151 }; 152 153 firmware { 154 scm { 155 compatible = "qcom,scm-ipq4019", "qcom,scm"; 156 }; 157 }; 158 159 timer { 160 compatible = "arm,armv7-timer"; 161 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 162 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 164 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 clock-frequency = <48000000>; 166 always-on; 167 }; 168 169 soc { 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges; 173 compatible = "simple-bus"; 174 175 intc: interrupt-controller@b000000 { 176 compatible = "qcom,msm-qgic2"; 177 interrupt-controller; 178 #address-cells = <0>; 179 #interrupt-cells = <3>; 180 reg = <0x0b000000 0x1000>, 181 <0x0b002000 0x1000>; 182 }; 183 184 gcc: clock-controller@1800000 { 185 compatible = "qcom,gcc-ipq4019"; 186 #clock-cells = <1>; 187 #reset-cells = <1>; 188 reg = <0x1800000 0x60000>; 189 clocks = <&xo>, <&sleep_clk>; 190 clock-names = "xo", "sleep_clk"; 191 }; 192 193 prng: rng@22000 { 194 compatible = "qcom,prng"; 195 reg = <0x22000 0x140>; 196 clocks = <&gcc GCC_PRNG_AHB_CLK>; 197 clock-names = "core"; 198 status = "disabled"; 199 }; 200 201 tlmm: pinctrl@1000000 { 202 compatible = "qcom,ipq4019-pinctrl"; 203 reg = <0x01000000 0x300000>; 204 gpio-controller; 205 gpio-ranges = <&tlmm 0 0 100>; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 210 }; 211 212 vqmmc: regulator@1948000 { 213 compatible = "qcom,vqmmc-ipq4019-regulator"; 214 reg = <0x01948000 0x4>; 215 regulator-name = "vqmmc"; 216 regulator-min-microvolt = <1500000>; 217 regulator-max-microvolt = <3000000>; 218 regulator-always-on; 219 status = "disabled"; 220 }; 221 222 sdhci: mmc@7824900 { 223 compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4"; 224 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 225 reg-names = "hc", "core"; 226 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "hc_irq", "pwr_irq"; 228 bus-width = <8>; 229 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 230 <&gcc GCC_SDCC1_APPS_CLK>, 231 <&xo>; 232 clock-names = "iface", 233 "core", 234 "xo"; 235 status = "disabled"; 236 }; 237 238 blsp_dma: dma-controller@7884000 { 239 compatible = "qcom,bam-v1.7.0"; 240 reg = <0x07884000 0x23000>; 241 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 243 clock-names = "bam_clk"; 244 #dma-cells = <1>; 245 qcom,ee = <0>; 246 status = "disabled"; 247 }; 248 249 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 250 compatible = "qcom,spi-qup-v2.2.1"; 251 reg = <0x78b5000 0x600>; 252 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 254 <&gcc GCC_BLSP1_AHB_CLK>; 255 clock-names = "core", "iface"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 259 dma-names = "tx", "rx"; 260 status = "disabled"; 261 }; 262 263 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 264 compatible = "qcom,spi-qup-v2.2.1"; 265 reg = <0x78b6000 0x600>; 266 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 268 <&gcc GCC_BLSP1_AHB_CLK>; 269 clock-names = "core", "iface"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 273 dma-names = "tx", "rx"; 274 status = "disabled"; 275 }; 276 277 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 278 compatible = "qcom,i2c-qup-v2.2.1"; 279 reg = <0x78b7000 0x600>; 280 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 282 <&gcc GCC_BLSP1_AHB_CLK>; 283 clock-names = "core", "iface"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 287 dma-names = "tx", "rx"; 288 status = "disabled"; 289 }; 290 291 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 292 compatible = "qcom,i2c-qup-v2.2.1"; 293 reg = <0x78b8000 0x600>; 294 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 296 <&gcc GCC_BLSP1_AHB_CLK>; 297 clock-names = "core", "iface"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 301 dma-names = "tx", "rx"; 302 status = "disabled"; 303 }; 304 305 cryptobam: dma-controller@8e04000 { 306 compatible = "qcom,bam-v1.7.0"; 307 reg = <0x08e04000 0x20000>; 308 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 310 clock-names = "bam_clk"; 311 #dma-cells = <1>; 312 qcom,ee = <1>; 313 qcom,controlled-remotely; 314 status = "disabled"; 315 }; 316 317 crypto: crypto@8e3a000 { 318 compatible = "qcom,crypto-v5.1"; 319 reg = <0x08e3a000 0x6000>; 320 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 321 <&gcc GCC_CRYPTO_AXI_CLK>, 322 <&gcc GCC_CRYPTO_CLK>; 323 clock-names = "iface", "bus", "core"; 324 dmas = <&cryptobam 2>, <&cryptobam 3>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 }; 328 329 acc0: power-manager@b088000 { 330 compatible = "qcom,kpss-acc-v2"; 331 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 332 }; 333 334 acc1: power-manager@b098000 { 335 compatible = "qcom,kpss-acc-v2"; 336 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 337 }; 338 339 acc2: power-manager@b0a8000 { 340 compatible = "qcom,kpss-acc-v2"; 341 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 342 }; 343 344 acc3: power-manager@b0b8000 { 345 compatible = "qcom,kpss-acc-v2"; 346 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 347 }; 348 349 saw0: power-manager@b089000 { 350 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 351 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 352 }; 353 354 saw1: power-manager@b099000 { 355 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 356 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 357 }; 358 359 saw2: power-manager@b0a9000 { 360 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 361 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 362 }; 363 364 saw3: power-manager@b0b9000 { 365 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 366 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 367 }; 368 369 saw_l2: power-manager@b012000 { 370 compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; 371 reg = <0xb012000 0x1000>; 372 }; 373 374 blsp1_uart1: serial@78af000 { 375 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 376 reg = <0x78af000 0x200>; 377 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 378 status = "disabled"; 379 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 380 <&gcc GCC_BLSP1_AHB_CLK>; 381 clock-names = "core", "iface"; 382 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 383 dma-names = "tx", "rx"; 384 }; 385 386 blsp1_uart2: serial@78b0000 { 387 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 388 reg = <0x78b0000 0x200>; 389 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 390 status = "disabled"; 391 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 392 <&gcc GCC_BLSP1_AHB_CLK>; 393 clock-names = "core", "iface"; 394 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 395 dma-names = "tx", "rx"; 396 }; 397 398 watchdog: watchdog@b017000 { 399 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; 400 reg = <0xb017000 0x40>; 401 clocks = <&sleep_clk>; 402 timeout-sec = <10>; 403 status = "disabled"; 404 }; 405 406 restart@4ab000 { 407 compatible = "qcom,pshold"; 408 reg = <0x4ab000 0x4>; 409 }; 410 411 pcie0: pcie@40000000 { 412 compatible = "qcom,pcie-ipq4019"; 413 reg = <0x40000000 0xf1d>, 414 <0x40000f20 0xa8>, 415 <0x80000 0x2000>, 416 <0x40100000 0x1000>; 417 reg-names = "dbi", "elbi", "parf", "config"; 418 device_type = "pci"; 419 linux,pci-domain = <0>; 420 bus-range = <0x00 0xff>; 421 num-lanes = <1>; 422 #address-cells = <3>; 423 #size-cells = <2>; 424 425 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 426 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 427 428 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "msi"; 430 #interrupt-cells = <1>; 431 interrupt-map-mask = <0 0 0 0x7>; 432 interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 433 <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 434 <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 435 <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 436 clocks = <&gcc GCC_PCIE_AHB_CLK>, 437 <&gcc GCC_PCIE_AXI_M_CLK>, 438 <&gcc GCC_PCIE_AXI_S_CLK>; 439 clock-names = "aux", 440 "master_bus", 441 "slave_bus"; 442 443 resets = <&gcc PCIE_AXI_M_ARES>, 444 <&gcc PCIE_AXI_S_ARES>, 445 <&gcc PCIE_PIPE_ARES>, 446 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 447 <&gcc PCIE_AXI_S_XPU_ARES>, 448 <&gcc PCIE_PARF_XPU_ARES>, 449 <&gcc PCIE_PHY_ARES>, 450 <&gcc PCIE_AXI_M_STICKY_ARES>, 451 <&gcc PCIE_PIPE_STICKY_ARES>, 452 <&gcc PCIE_PWR_ARES>, 453 <&gcc PCIE_AHB_ARES>, 454 <&gcc PCIE_PHY_AHB_ARES>; 455 reset-names = "axi_m", 456 "axi_s", 457 "pipe", 458 "axi_m_vmid", 459 "axi_s_xpu", 460 "parf", 461 "phy", 462 "axi_m_sticky", 463 "pipe_sticky", 464 "pwr", 465 "ahb", 466 "phy_ahb"; 467 468 status = "disabled"; 469 470 pcie@0 { 471 device_type = "pci"; 472 reg = <0x0 0x0 0x0 0x0 0x0>; 473 bus-range = <0x01 0xff>; 474 475 #address-cells = <3>; 476 #size-cells = <2>; 477 ranges; 478 }; 479 }; 480 481 qpic_bam: dma-controller@7984000 { 482 compatible = "qcom,bam-v1.7.0"; 483 reg = <0x7984000 0x1a000>; 484 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&gcc GCC_QPIC_CLK>; 486 clock-names = "bam_clk"; 487 #dma-cells = <1>; 488 qcom,ee = <0>; 489 status = "disabled"; 490 }; 491 492 nand: nand-controller@79b0000 { 493 compatible = "qcom,ipq4019-nand"; 494 reg = <0x79b0000 0x1000>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clocks = <&gcc GCC_QPIC_CLK>, 498 <&gcc GCC_QPIC_AHB_CLK>; 499 clock-names = "core", "aon"; 500 501 dmas = <&qpic_bam 0>, 502 <&qpic_bam 1>, 503 <&qpic_bam 2>; 504 dma-names = "tx", "rx", "cmd"; 505 status = "disabled"; 506 507 nand@0 { 508 reg = <0>; 509 510 nand-ecc-strength = <4>; 511 nand-ecc-step-size = <512>; 512 nand-bus-width = <8>; 513 }; 514 }; 515 516 wifi0: wifi@a000000 { 517 compatible = "qcom,ipq4019-wifi"; 518 reg = <0xa000000 0x200000>; 519 resets = <&gcc WIFI0_CPU_INIT_RESET>, 520 <&gcc WIFI0_RADIO_SRIF_RESET>, 521 <&gcc WIFI0_RADIO_WARM_RESET>, 522 <&gcc WIFI0_RADIO_COLD_RESET>, 523 <&gcc WIFI0_CORE_WARM_RESET>, 524 <&gcc WIFI0_CORE_COLD_RESET>; 525 reset-names = "wifi_cpu_init", "wifi_radio_srif", 526 "wifi_radio_warm", "wifi_radio_cold", 527 "wifi_core_warm", "wifi_core_cold"; 528 clocks = <&gcc GCC_WCSS2G_CLK>, 529 <&gcc GCC_WCSS2G_REF_CLK>, 530 <&gcc GCC_WCSS2G_RTC_CLK>; 531 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 532 "wifi_wcss_rtc"; 533 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "msi0", "msi1", "msi2", "msi3", 551 "msi4", "msi5", "msi6", "msi7", 552 "msi8", "msi9", "msi10", "msi11", 553 "msi12", "msi13", "msi14", "msi15", 554 "legacy"; 555 status = "disabled"; 556 }; 557 558 wifi1: wifi@a800000 { 559 compatible = "qcom,ipq4019-wifi"; 560 reg = <0xa800000 0x200000>; 561 resets = <&gcc WIFI1_CPU_INIT_RESET>, 562 <&gcc WIFI1_RADIO_SRIF_RESET>, 563 <&gcc WIFI1_RADIO_WARM_RESET>, 564 <&gcc WIFI1_RADIO_COLD_RESET>, 565 <&gcc WIFI1_CORE_WARM_RESET>, 566 <&gcc WIFI1_CORE_COLD_RESET>; 567 reset-names = "wifi_cpu_init", "wifi_radio_srif", 568 "wifi_radio_warm", "wifi_radio_cold", 569 "wifi_core_warm", "wifi_core_cold"; 570 clocks = <&gcc GCC_WCSS5G_CLK>, 571 <&gcc GCC_WCSS5G_REF_CLK>, 572 <&gcc GCC_WCSS5G_RTC_CLK>; 573 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 574 "wifi_wcss_rtc"; 575 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 591 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "msi0", "msi1", "msi2", "msi3", 593 "msi4", "msi5", "msi6", "msi7", 594 "msi8", "msi9", "msi10", "msi11", 595 "msi12", "msi13", "msi14", "msi15", 596 "legacy"; 597 status = "disabled"; 598 }; 599 600 mdio: mdio@90000 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 compatible = "qcom,ipq4019-mdio"; 604 reg = <0x90000 0x64>; 605 status = "disabled"; 606 607 ethernet-phy-package@0 { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 compatible = "qcom,qca8075-package"; 611 reg = <0>; 612 613 qcom,tx-drive-strength-milliwatt = <300>; 614 615 ethphy0: ethernet-phy@0 { 616 reg = <0>; 617 }; 618 619 ethphy1: ethernet-phy@1 { 620 reg = <1>; 621 }; 622 623 ethphy2: ethernet-phy@2 { 624 reg = <2>; 625 }; 626 627 ethphy3: ethernet-phy@3 { 628 reg = <3>; 629 }; 630 631 ethphy4: ethernet-phy@4 { 632 reg = <4>; 633 }; 634 }; 635 }; 636 637 usb3_ss_phy: usb-phy@9a000 { 638 compatible = "qcom,usb-ss-ipq4019-phy"; 639 #phy-cells = <0>; 640 reg = <0x9a000 0x800>; 641 reg-names = "phy_base"; 642 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 643 reset-names = "por_rst"; 644 status = "disabled"; 645 }; 646 647 usb3_hs_phy: usb-phy@a6000 { 648 compatible = "qcom,usb-hs-ipq4019-phy"; 649 #phy-cells = <0>; 650 reg = <0xa6000 0x40>; 651 reg-names = "phy_base"; 652 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 653 reset-names = "por_rst", "srif_rst"; 654 status = "disabled"; 655 }; 656 657 usb3: usb@8af8800 { 658 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 659 reg = <0x8af8800 0x100>; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 clocks = <&gcc GCC_USB3_MASTER_CLK>, 663 <&gcc GCC_USB3_SLEEP_CLK>, 664 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 665 clock-names = "core", "sleep", "mock_utmi"; 666 ranges; 667 status = "disabled"; 668 669 usb3_dwc: usb@8a00000 { 670 compatible = "snps,dwc3"; 671 reg = <0x8a00000 0xf8000>; 672 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 673 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 674 phy-names = "usb2-phy", "usb3-phy"; 675 dr_mode = "host"; 676 }; 677 }; 678 679 usb2_hs_phy: usb-phy@a8000 { 680 compatible = "qcom,usb-hs-ipq4019-phy"; 681 #phy-cells = <0>; 682 reg = <0xa8000 0x40>; 683 reg-names = "phy_base"; 684 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 685 reset-names = "por_rst", "srif_rst"; 686 status = "disabled"; 687 }; 688 689 usb2: usb@60f8800 { 690 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 691 reg = <0x60f8800 0x100>; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 clocks = <&gcc GCC_USB2_MASTER_CLK>, 695 <&gcc GCC_USB2_SLEEP_CLK>, 696 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 697 clock-names = "core", "sleep", "mock_utmi"; 698 ranges; 699 status = "disabled"; 700 701 usb@6000000 { 702 compatible = "snps,dwc3"; 703 reg = <0x6000000 0xf8000>; 704 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 705 phys = <&usb2_hs_phy>; 706 phy-names = "usb2-phy"; 707 dr_mode = "host"; 708 }; 709 }; 710 }; 711}; 712