1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&L2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&CPU_SPC>; 48 }; 49 50 CPU1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&L2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&CPU_SPC>; 59 }; 60 61 CPU2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&L2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&CPU_SPC>; 70 }; 71 72 CPU3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&L2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&CPU_SPC>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 CPU_SPC: cpu-spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 sfpb_mutex: hwmutex { 217 compatible = "qcom,sfpb-mutex"; 218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 219 #hwlock-cells = <1>; 220 }; 221 222 smem { 223 compatible = "qcom,smem"; 224 memory-region = <&smem_region>; 225 226 hwlocks = <&sfpb_mutex 3>; 227 }; 228 229 smsm { 230 compatible = "qcom,smsm"; 231 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 qcom,ipc-1 = <&l2cc 8 4>; 236 qcom,ipc-2 = <&l2cc 8 14>; 237 qcom,ipc-3 = <&l2cc 8 23>; 238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 239 240 apps_smsm: apps@0 { 241 reg = <0>; 242 #qcom,smem-state-cells = <1>; 243 }; 244 245 modem_smsm: modem@1 { 246 reg = <1>; 247 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 253 q6_smsm: q6@2 { 254 reg = <2>; 255 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 256 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 }; 260 261 wcnss_smsm: wcnss@3 { 262 reg = <3>; 263 interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; 264 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 }; 268 269 dsps_smsm: dsps@4 { 270 reg = <4>; 271 interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>; 272 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 }; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-apq8064", "qcom,scm"; 281 282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 283 clock-names = "core"; 284 }; 285 }; 286 287 soc: soc { 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 compatible = "simple-bus"; 292 293 tlmm_pinmux: pinctrl@800000 { 294 compatible = "qcom,apq8064-pinctrl"; 295 reg = <0x800000 0x4000>; 296 297 gpio-controller; 298 gpio-ranges = <&tlmm_pinmux 0 0 90>; 299 #gpio-cells = <2>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 303 304 pinctrl-names = "default"; 305 pinctrl-0 = <&ps_hold>; 306 }; 307 308 sfpb_wrapper_mutex: syscon@1200000 { 309 compatible = "syscon"; 310 reg = <0x01200000 0x8000>; 311 }; 312 313 intc: interrupt-controller@2000000 { 314 compatible = "qcom,msm-qgic2"; 315 interrupt-controller; 316 #interrupt-cells = <3>; 317 reg = <0x02000000 0x1000>, 318 <0x02002000 0x1000>; 319 }; 320 321 timer@200a000 { 322 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 323 "qcom,msm-timer"; 324 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 325 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 326 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 327 reg = <0x0200a000 0x100>; 328 clock-frequency = <27000000>; 329 cpu-offset = <0x80000>; 330 }; 331 332 acc0: clock-controller@2088000 { 333 compatible = "qcom,kpss-acc-v1"; 334 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 335 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 336 clock-names = "pll8_vote", "pxo"; 337 clock-output-names = "acpu0_aux"; 338 #clock-cells = <0>; 339 }; 340 341 acc1: clock-controller@2098000 { 342 compatible = "qcom,kpss-acc-v1"; 343 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 344 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 345 clock-names = "pll8_vote", "pxo"; 346 clock-output-names = "acpu1_aux"; 347 #clock-cells = <0>; 348 }; 349 350 acc2: clock-controller@20a8000 { 351 compatible = "qcom,kpss-acc-v1"; 352 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 353 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 354 clock-names = "pll8_vote", "pxo"; 355 clock-output-names = "acpu2_aux"; 356 #clock-cells = <0>; 357 }; 358 359 acc3: clock-controller@20b8000 { 360 compatible = "qcom,kpss-acc-v1"; 361 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 362 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 363 clock-names = "pll8_vote", "pxo"; 364 clock-output-names = "acpu3_aux"; 365 #clock-cells = <0>; 366 }; 367 368 saw0: power-manager@2089000 { 369 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 370 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 371 372 saw0_vreg: regulator { 373 regulator-min-microvolt = <850000>; 374 regulator-max-microvolt = <1300000>; 375 }; 376 }; 377 378 saw1: power-manager@2099000 { 379 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 380 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 381 382 saw1_vreg: regulator { 383 regulator-min-microvolt = <850000>; 384 regulator-max-microvolt = <1300000>; 385 }; 386 }; 387 388 saw2: power-manager@20a9000 { 389 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 390 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 391 392 saw2_vreg: regulator { 393 regulator-min-microvolt = <850000>; 394 regulator-max-microvolt = <1300000>; 395 }; 396 }; 397 398 saw3: power-manager@20b9000 { 399 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 400 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 401 402 saw3_vreg: regulator { 403 regulator-min-microvolt = <850000>; 404 regulator-max-microvolt = <1300000>; 405 }; 406 }; 407 408 sps_sic_non_secure: sps-sic-non-secure@12100000 { 409 compatible = "syscon"; 410 reg = <0x12100000 0x10000>; 411 }; 412 413 gsbi1: gsbi@12440000 { 414 status = "disabled"; 415 compatible = "qcom,gsbi-v1.0.0"; 416 cell-index = <1>; 417 reg = <0x12440000 0x100>; 418 clocks = <&gcc GSBI1_H_CLK>; 419 clock-names = "iface"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 ranges; 423 424 syscon-tcsr = <&tcsr>; 425 426 gsbi1_serial: serial@12450000 { 427 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 428 reg = <0x12450000 0x100>, 429 <0x12400000 0x03>; 430 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 432 clock-names = "core", "iface"; 433 status = "disabled"; 434 }; 435 436 gsbi1_i2c: i2c@12460000 { 437 compatible = "qcom,i2c-qup-v1.1.1"; 438 pinctrl-0 = <&i2c1_pins>; 439 pinctrl-1 = <&i2c1_pins_sleep>; 440 pinctrl-names = "default", "sleep"; 441 reg = <0x12460000 0x1000>; 442 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 444 clock-names = "core", "iface"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 }; 451 452 gsbi2: gsbi@12480000 { 453 status = "disabled"; 454 compatible = "qcom,gsbi-v1.0.0"; 455 cell-index = <2>; 456 reg = <0x12480000 0x100>; 457 clocks = <&gcc GSBI2_H_CLK>; 458 clock-names = "iface"; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges; 462 463 syscon-tcsr = <&tcsr>; 464 465 gsbi2_i2c: i2c@124a0000 { 466 compatible = "qcom,i2c-qup-v1.1.1"; 467 reg = <0x124a0000 0x1000>; 468 pinctrl-0 = <&i2c2_pins>; 469 pinctrl-1 = <&i2c2_pins_sleep>; 470 pinctrl-names = "default", "sleep"; 471 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 473 clock-names = "core", "iface"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 }; 479 480 gsbi3: gsbi@16200000 { 481 status = "disabled"; 482 compatible = "qcom,gsbi-v1.0.0"; 483 cell-index = <3>; 484 reg = <0x16200000 0x100>; 485 clocks = <&gcc GSBI3_H_CLK>; 486 clock-names = "iface"; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges; 490 gsbi3_i2c: i2c@16280000 { 491 compatible = "qcom,i2c-qup-v1.1.1"; 492 pinctrl-0 = <&i2c3_pins>; 493 pinctrl-1 = <&i2c3_pins_sleep>; 494 pinctrl-names = "default", "sleep"; 495 reg = <0x16280000 0x1000>; 496 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&gcc GSBI3_QUP_CLK>, 498 <&gcc GSBI3_H_CLK>; 499 clock-names = "core", "iface"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 status = "disabled"; 503 }; 504 }; 505 506 gsbi4: gsbi@16300000 { 507 status = "disabled"; 508 compatible = "qcom,gsbi-v1.0.0"; 509 cell-index = <4>; 510 reg = <0x16300000 0x03>; 511 clocks = <&gcc GSBI4_H_CLK>; 512 clock-names = "iface"; 513 #address-cells = <1>; 514 #size-cells = <1>; 515 ranges; 516 517 gsbi4_serial: serial@16340000 { 518 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 519 reg = <0x16340000 0x100>, 520 <0x16300000 0x3>; 521 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 522 pinctrl-0 = <&gsbi4_uart_pin_a>; 523 pinctrl-names = "default"; 524 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 525 clock-names = "core", "iface"; 526 status = "disabled"; 527 }; 528 529 gsbi4_i2c: i2c@16380000 { 530 compatible = "qcom,i2c-qup-v1.1.1"; 531 pinctrl-0 = <&i2c4_pins>; 532 pinctrl-1 = <&i2c4_pins_sleep>; 533 pinctrl-names = "default", "sleep"; 534 reg = <0x16380000 0x1000>; 535 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&gcc GSBI4_QUP_CLK>, 537 <&gcc GSBI4_H_CLK>; 538 clock-names = "core", "iface"; 539 status = "disabled"; 540 }; 541 }; 542 543 gsbi5: gsbi@1a200000 { 544 status = "disabled"; 545 compatible = "qcom,gsbi-v1.0.0"; 546 cell-index = <5>; 547 reg = <0x1a200000 0x03>; 548 clocks = <&gcc GSBI5_H_CLK>; 549 clock-names = "iface"; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 ranges; 553 554 gsbi5_serial: serial@1a240000 { 555 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 556 reg = <0x1a240000 0x100>, 557 <0x1a200000 0x03>; 558 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 560 clock-names = "core", "iface"; 561 status = "disabled"; 562 }; 563 564 gsbi5_spi: spi@1a280000 { 565 compatible = "qcom,spi-qup-v1.1.1"; 566 reg = <0x1a280000 0x1000>; 567 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 568 pinctrl-0 = <&spi5_default>; 569 pinctrl-1 = <&spi5_sleep>; 570 pinctrl-names = "default", "sleep"; 571 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 572 clock-names = "core", "iface"; 573 status = "disabled"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 }; 577 }; 578 579 gsbi6: gsbi@16500000 { 580 status = "disabled"; 581 compatible = "qcom,gsbi-v1.0.0"; 582 cell-index = <6>; 583 reg = <0x16500000 0x03>; 584 clocks = <&gcc GSBI6_H_CLK>; 585 clock-names = "iface"; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges; 589 590 gsbi6_serial: serial@16540000 { 591 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 592 reg = <0x16540000 0x100>, 593 <0x16500000 0x03>; 594 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 596 clock-names = "core", "iface"; 597 status = "disabled"; 598 }; 599 600 gsbi6_i2c: i2c@16580000 { 601 compatible = "qcom,i2c-qup-v1.1.1"; 602 pinctrl-0 = <&i2c6_pins>; 603 pinctrl-1 = <&i2c6_pins_sleep>; 604 pinctrl-names = "default", "sleep"; 605 reg = <0x16580000 0x1000>; 606 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GSBI6_QUP_CLK>, 608 <&gcc GSBI6_H_CLK>; 609 clock-names = "core", "iface"; 610 status = "disabled"; 611 }; 612 }; 613 614 gsbi7: gsbi@16600000 { 615 status = "disabled"; 616 compatible = "qcom,gsbi-v1.0.0"; 617 cell-index = <7>; 618 reg = <0x16600000 0x100>; 619 clocks = <&gcc GSBI7_H_CLK>; 620 clock-names = "iface"; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 ranges; 624 syscon-tcsr = <&tcsr>; 625 626 gsbi7_serial: serial@16640000 { 627 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 628 reg = <0x16640000 0x1000>, 629 <0x16600000 0x1000>; 630 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 632 clock-names = "core", "iface"; 633 status = "disabled"; 634 }; 635 636 gsbi7_i2c: i2c@16680000 { 637 compatible = "qcom,i2c-qup-v1.1.1"; 638 pinctrl-0 = <&i2c7_pins>; 639 pinctrl-1 = <&i2c7_pins_sleep>; 640 pinctrl-names = "default", "sleep"; 641 reg = <0x16680000 0x1000>; 642 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GSBI7_QUP_CLK>, 644 <&gcc GSBI7_H_CLK>; 645 clock-names = "core", "iface"; 646 status = "disabled"; 647 }; 648 }; 649 650 rng@1a500000 { 651 compatible = "qcom,prng"; 652 reg = <0x1a500000 0x200>; 653 clocks = <&gcc PRNG_CLK>; 654 clock-names = "core"; 655 }; 656 657 ssbi2: ssbi@c00000 { 658 compatible = "qcom,ssbi"; 659 reg = <0x00c00000 0x1000>; 660 qcom,controller-type = "pmic-arbiter"; 661 }; 662 663 ssbi: ssbi@500000 { 664 compatible = "qcom,ssbi"; 665 reg = <0x00500000 0x1000>; 666 qcom,controller-type = "pmic-arbiter"; 667 }; 668 669 qfprom: qfprom@700000 { 670 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 671 reg = <0x00700000 0x1000>; 672 #address-cells = <1>; 673 #size-cells = <1>; 674 ranges; 675 tsens_calib: calib@404 { 676 reg = <0x404 0x10>; 677 }; 678 tsens_backup: backup_calib@414 { 679 reg = <0x414 0x10>; 680 }; 681 }; 682 683 gcc: clock-controller@900000 { 684 compatible = "qcom,gcc-apq8064", "syscon"; 685 reg = <0x00900000 0x4000>; 686 #clock-cells = <1>; 687 #power-domain-cells = <1>; 688 #reset-cells = <1>; 689 clocks = <&cxo_board>, 690 <&pxo_board>, 691 <&lcc PLL4>; 692 clock-names = "cxo", "pxo", "pll4"; 693 694 tsens: thermal-sensor { 695 compatible = "qcom,msm8960-tsens"; 696 697 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 698 nvmem-cell-names = "calib", "calib_backup"; 699 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "uplow"; 701 702 #qcom,sensors = <11>; 703 #thermal-sensor-cells = <1>; 704 }; 705 }; 706 707 lcc: clock-controller@28000000 { 708 compatible = "qcom,lcc-apq8064"; 709 reg = <0x28000000 0x1000>; 710 #clock-cells = <1>; 711 #reset-cells = <1>; 712 clocks = <&pxo_board>, 713 <&gcc PLL4_VOTE>, 714 <0>, 715 <0>, <0>, 716 <0>, <0>, 717 <0>; 718 clock-names = "pxo", 719 "pll4_vote", 720 "mi2s_codec_clk", 721 "codec_i2s_mic_codec_clk", 722 "spare_i2s_mic_codec_clk", 723 "codec_i2s_spkr_codec_clk", 724 "spare_i2s_spkr_codec_clk", 725 "pcm_codec_clk"; 726 }; 727 728 mmcc: clock-controller@4000000 { 729 compatible = "qcom,mmcc-apq8064"; 730 reg = <0x4000000 0x1000>; 731 #clock-cells = <1>; 732 #power-domain-cells = <1>; 733 #reset-cells = <1>; 734 clocks = <&pxo_board>, 735 <&gcc PLL3>, 736 <&gcc PLL8_VOTE>, 737 <&dsi0_phy 1>, 738 <&dsi0_phy 0>, 739 <&dsi1_phy 1>, 740 <&dsi1_phy 0>, 741 <&hdmi_phy>; 742 clock-names = "pxo", 743 "pll3", 744 "pll8_vote", 745 "dsi1pll", 746 "dsi1pllbyte", 747 "dsi2pll", 748 "dsi2pllbyte", 749 "hdmipll"; 750 }; 751 752 l2cc: clock-controller@2011000 { 753 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 754 reg = <0x2011000 0x1000>; 755 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 756 clock-names = "pll8_vote", "pxo"; 757 #clock-cells = <0>; 758 }; 759 760 rpm: rpm@108000 { 761 compatible = "qcom,rpm-apq8064"; 762 reg = <0x108000 0x1000>; 763 qcom,ipc = <&l2cc 0x8 2>; 764 765 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 766 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 767 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 768 interrupt-names = "ack", "err", "wakeup"; 769 770 rpmcc: clock-controller { 771 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 772 #clock-cells = <1>; 773 clocks = <&pxo_board>, <&cxo_board>; 774 clock-names = "pxo", "cxo"; 775 }; 776 }; 777 778 usb1: usb@12500000 { 779 compatible = "qcom,ci-hdrc"; 780 reg = <0x12500000 0x200>, 781 <0x12500200 0x200>; 782 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 784 clock-names = "core", "iface"; 785 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 786 assigned-clock-rates = <60000000>; 787 resets = <&gcc USB_HS1_RESET>; 788 reset-names = "core"; 789 phy_type = "ulpi"; 790 ahb-burst-config = <0>; 791 phys = <&usb_hs1_phy>; 792 phy-names = "usb-phy"; 793 status = "disabled"; 794 #reset-cells = <1>; 795 796 ulpi { 797 usb_hs1_phy: phy { 798 compatible = "qcom,usb-hs-phy-apq8064", 799 "qcom,usb-hs-phy"; 800 clocks = <&sleep_clk>, <&cxo_board>; 801 clock-names = "sleep", "ref"; 802 resets = <&usb1 0>; 803 reset-names = "por"; 804 #phy-cells = <0>; 805 }; 806 }; 807 }; 808 809 usb3: usb@12520000 { 810 compatible = "qcom,ci-hdrc"; 811 reg = <0x12520000 0x200>, 812 <0x12520200 0x200>; 813 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 815 clock-names = "core", "iface"; 816 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 817 assigned-clock-rates = <60000000>; 818 resets = <&gcc USB_HS3_RESET>; 819 reset-names = "core"; 820 phy_type = "ulpi"; 821 ahb-burst-config = <0>; 822 phys = <&usb_hs3_phy>; 823 phy-names = "usb-phy"; 824 status = "disabled"; 825 #reset-cells = <1>; 826 827 ulpi { 828 usb_hs3_phy: phy { 829 compatible = "qcom,usb-hs-phy-apq8064", 830 "qcom,usb-hs-phy"; 831 #phy-cells = <0>; 832 clocks = <&sleep_clk>, <&cxo_board>; 833 clock-names = "sleep", "ref"; 834 resets = <&usb3 0>; 835 reset-names = "por"; 836 }; 837 }; 838 }; 839 840 usb4: usb@12530000 { 841 compatible = "qcom,ci-hdrc"; 842 reg = <0x12530000 0x200>, 843 <0x12530200 0x200>; 844 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 846 clock-names = "core", "iface"; 847 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 848 assigned-clock-rates = <60000000>; 849 resets = <&gcc USB_HS4_RESET>; 850 reset-names = "core"; 851 phy_type = "ulpi"; 852 ahb-burst-config = <0>; 853 phys = <&usb_hs4_phy>; 854 phy-names = "usb-phy"; 855 status = "disabled"; 856 #reset-cells = <1>; 857 858 ulpi { 859 usb_hs4_phy: phy { 860 compatible = "qcom,usb-hs-phy-apq8064", 861 "qcom,usb-hs-phy"; 862 #phy-cells = <0>; 863 clocks = <&sleep_clk>, <&cxo_board>; 864 clock-names = "sleep", "ref"; 865 resets = <&usb4 0>; 866 reset-names = "por"; 867 }; 868 }; 869 }; 870 871 sata_phy0: phy@1b400000 { 872 compatible = "qcom,apq8064-sata-phy"; 873 status = "disabled"; 874 reg = <0x1b400000 0x200>; 875 reg-names = "phy_mem"; 876 clocks = <&gcc SATA_PHY_CFG_CLK>; 877 clock-names = "cfg"; 878 #phy-cells = <0>; 879 }; 880 881 sata0: sata@29000000 { 882 compatible = "qcom,apq8064-ahci", "generic-ahci"; 883 status = "disabled"; 884 reg = <0x29000000 0x180>; 885 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 886 887 clocks = <&gcc SFAB_SATA_S_H_CLK>, 888 <&gcc SATA_H_CLK>, 889 <&gcc SATA_A_CLK>, 890 <&gcc SATA_RXOOB_CLK>, 891 <&gcc SATA_PMALIVE_CLK>; 892 clock-names = "slave_iface", 893 "iface", 894 "bus", 895 "rxoob", 896 "core_pmalive"; 897 898 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 899 <&gcc SATA_PMALIVE_CLK>; 900 assigned-clock-rates = <100000000>, <100000000>; 901 902 phys = <&sata_phy0>; 903 phy-names = "sata-phy"; 904 ports-implemented = <0x1>; 905 }; 906 907 sdcc3: mmc@12180000 { 908 compatible = "arm,pl18x", "arm,primecell"; 909 arm,primecell-periphid = <0x00051180>; 910 status = "disabled"; 911 reg = <0x12180000 0x2000>; 912 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 914 clock-names = "mclk", "apb_pclk"; 915 bus-width = <4>; 916 cap-sd-highspeed; 917 cap-mmc-highspeed; 918 max-frequency = <192000000>; 919 no-1-8-v; 920 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 921 dma-names = "tx", "rx"; 922 }; 923 924 sdcc3bam: dma-controller@12182000 { 925 compatible = "qcom,bam-v1.3.0"; 926 reg = <0x12182000 0x8000>; 927 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&gcc SDC3_H_CLK>; 929 clock-names = "bam_clk"; 930 #dma-cells = <1>; 931 qcom,ee = <0>; 932 }; 933 934 sdcc4: mmc@121c0000 { 935 compatible = "arm,pl18x", "arm,primecell"; 936 arm,primecell-periphid = <0x00051180>; 937 status = "disabled"; 938 reg = <0x121c0000 0x2000>; 939 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 941 clock-names = "mclk", "apb_pclk"; 942 bus-width = <4>; 943 cap-sd-highspeed; 944 cap-mmc-highspeed; 945 max-frequency = <48000000>; 946 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 947 dma-names = "tx", "rx"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&sdc4_gpios>; 950 }; 951 952 sdcc4bam: dma-controller@121c2000 { 953 compatible = "qcom,bam-v1.3.0"; 954 reg = <0x121c2000 0x8000>; 955 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&gcc SDC4_H_CLK>; 957 clock-names = "bam_clk"; 958 #dma-cells = <1>; 959 qcom,ee = <0>; 960 }; 961 962 sdcc1: mmc@12400000 { 963 status = "disabled"; 964 compatible = "arm,pl18x", "arm,primecell"; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&sdcc1_pins>; 967 arm,primecell-periphid = <0x00051180>; 968 reg = <0x12400000 0x2000>; 969 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 971 clock-names = "mclk", "apb_pclk"; 972 bus-width = <8>; 973 max-frequency = <96000000>; 974 non-removable; 975 cap-sd-highspeed; 976 cap-mmc-highspeed; 977 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 978 dma-names = "tx", "rx"; 979 }; 980 981 sdcc1bam: dma-controller@12402000 { 982 compatible = "qcom,bam-v1.3.0"; 983 reg = <0x12402000 0x8000>; 984 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&gcc SDC1_H_CLK>; 986 clock-names = "bam_clk"; 987 #dma-cells = <1>; 988 qcom,ee = <0>; 989 }; 990 991 tcsr: syscon@1a400000 { 992 compatible = "qcom,tcsr-apq8064", "syscon"; 993 reg = <0x1a400000 0x100>; 994 }; 995 996 gpu: adreno-3xx@4300000 { 997 compatible = "qcom,adreno-320.2", "qcom,adreno"; 998 reg = <0x04300000 0x20000>; 999 reg-names = "kgsl_3d0_reg_memory"; 1000 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "kgsl_3d0_irq"; 1002 clock-names = 1003 "core", 1004 "iface", 1005 "mem", 1006 "mem_iface"; 1007 clocks = 1008 <&mmcc GFX3D_CLK>, 1009 <&mmcc GFX3D_AHB_CLK>, 1010 <&mmcc GFX3D_AXI_CLK>, 1011 <&mmcc MMSS_IMEM_AHB_CLK>; 1012 1013 iommus = <&gfx3d 0 1014 &gfx3d 1 1015 &gfx3d 2 1016 &gfx3d 3 1017 &gfx3d 4 1018 &gfx3d 5 1019 &gfx3d 6 1020 &gfx3d 7 1021 &gfx3d 8 1022 &gfx3d 9 1023 &gfx3d 10 1024 &gfx3d 11 1025 &gfx3d 12 1026 &gfx3d 13 1027 &gfx3d 14 1028 &gfx3d 15 1029 &gfx3d 16 1030 &gfx3d 17 1031 &gfx3d 18 1032 &gfx3d 19 1033 &gfx3d 20 1034 &gfx3d 21 1035 &gfx3d 22 1036 &gfx3d 23 1037 &gfx3d 24 1038 &gfx3d 25 1039 &gfx3d 26 1040 &gfx3d 27 1041 &gfx3d 28 1042 &gfx3d 29 1043 &gfx3d 30 1044 &gfx3d 31 1045 &gfx3d1 0 1046 &gfx3d1 1 1047 &gfx3d1 2 1048 &gfx3d1 3 1049 &gfx3d1 4 1050 &gfx3d1 5 1051 &gfx3d1 6 1052 &gfx3d1 7 1053 &gfx3d1 8 1054 &gfx3d1 9 1055 &gfx3d1 10 1056 &gfx3d1 11 1057 &gfx3d1 12 1058 &gfx3d1 13 1059 &gfx3d1 14 1060 &gfx3d1 15 1061 &gfx3d1 16 1062 &gfx3d1 17 1063 &gfx3d1 18 1064 &gfx3d1 19 1065 &gfx3d1 20 1066 &gfx3d1 21 1067 &gfx3d1 22 1068 &gfx3d1 23 1069 &gfx3d1 24 1070 &gfx3d1 25 1071 &gfx3d1 26 1072 &gfx3d1 27 1073 &gfx3d1 28 1074 &gfx3d1 29 1075 &gfx3d1 30 1076 &gfx3d1 31>; 1077 1078 operating-points-v2 = <&gpu_opp_table>; 1079 1080 gpu_opp_table: opp-table { 1081 compatible = "operating-points-v2"; 1082 1083 opp-450000000 { 1084 opp-hz = /bits/ 64 <450000000>; 1085 }; 1086 1087 opp-27000000 { 1088 opp-hz = /bits/ 64 <27000000>; 1089 }; 1090 }; 1091 }; 1092 1093 mmss_sfpb: syscon@5700000 { 1094 compatible = "syscon"; 1095 reg = <0x5700000 0x70>; 1096 }; 1097 1098 dsi0: dsi@4700000 { 1099 compatible = "qcom,apq8064-dsi-ctrl", 1100 "qcom,mdss-dsi-ctrl"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1104 reg = <0x04700000 0x200>; 1105 reg-names = "dsi_ctrl"; 1106 1107 clocks = <&mmcc DSI_M_AHB_CLK>, 1108 <&mmcc DSI_S_AHB_CLK>, 1109 <&mmcc AMP_AHB_CLK>, 1110 <&mmcc DSI_CLK>, 1111 <&mmcc DSI1_BYTE_CLK>, 1112 <&mmcc DSI_PIXEL_CLK>, 1113 <&mmcc DSI1_ESC_CLK>; 1114 clock-names = "iface", "bus", "core_mmss", 1115 "src", "byte", "pixel", 1116 "core"; 1117 1118 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1119 <&mmcc DSI1_ESC_SRC>, 1120 <&mmcc DSI_SRC>, 1121 <&mmcc DSI_PIXEL_SRC>; 1122 assigned-clock-parents = <&dsi0_phy 0>, 1123 <&dsi0_phy 0>, 1124 <&dsi0_phy 1>, 1125 <&dsi0_phy 1>; 1126 syscon-sfpb = <&mmss_sfpb>; 1127 phys = <&dsi0_phy>; 1128 status = "disabled"; 1129 1130 ports { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 port@0 { 1135 reg = <0>; 1136 dsi0_in: endpoint { 1137 }; 1138 }; 1139 1140 port@1 { 1141 reg = <1>; 1142 dsi0_out: endpoint { 1143 }; 1144 }; 1145 }; 1146 }; 1147 1148 1149 dsi0_phy: phy@4700200 { 1150 compatible = "qcom,dsi-phy-28nm-8960"; 1151 #clock-cells = <1>; 1152 #phy-cells = <0>; 1153 1154 reg = <0x04700200 0x100>, 1155 <0x04700300 0x200>, 1156 <0x04700500 0x5c>; 1157 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1158 clock-names = "iface", "ref"; 1159 clocks = <&mmcc DSI_M_AHB_CLK>, 1160 <&pxo_board>; 1161 status = "disabled"; 1162 }; 1163 1164 dsi1: dsi@5800000 { 1165 compatible = "qcom,mdss-dsi-ctrl"; 1166 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1167 reg = <0x05800000 0x200>; 1168 reg-names = "dsi_ctrl"; 1169 1170 clocks = <&mmcc DSI2_M_AHB_CLK>, 1171 <&mmcc DSI2_S_AHB_CLK>, 1172 <&mmcc AMP_AHB_CLK>, 1173 <&mmcc DSI2_CLK>, 1174 <&mmcc DSI2_BYTE_CLK>, 1175 <&mmcc DSI2_PIXEL_CLK>, 1176 <&mmcc DSI2_ESC_CLK>; 1177 clock-names = "iface", 1178 "bus", 1179 "core_mmss", 1180 "src", 1181 "byte", 1182 "pixel", 1183 "core"; 1184 1185 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1186 <&mmcc DSI2_ESC_SRC>, 1187 <&mmcc DSI2_SRC>, 1188 <&mmcc DSI2_PIXEL_SRC>; 1189 assigned-clock-parents = <&dsi1_phy 0>, 1190 <&dsi1_phy 0>, 1191 <&dsi1_phy 1>, 1192 <&dsi1_phy 1>; 1193 1194 syscon-sfpb = <&mmss_sfpb>; 1195 phys = <&dsi1_phy>; 1196 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 1200 status = "disabled"; 1201 1202 ports { 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 port@0 { 1207 reg = <0>; 1208 dsi1_in: endpoint { 1209 }; 1210 }; 1211 1212 port@1 { 1213 reg = <1>; 1214 dsi1_out: endpoint { 1215 }; 1216 }; 1217 }; 1218 }; 1219 1220 1221 dsi1_phy: dsi-phy@5800200 { 1222 compatible = "qcom,dsi-phy-28nm-8960"; 1223 reg = <0x05800200 0x100>, 1224 <0x05800300 0x200>, 1225 <0x05800500 0x5c>; 1226 reg-names = "dsi_pll", 1227 "dsi_phy", 1228 "dsi_phy_regulator"; 1229 clock-names = "iface", 1230 "ref"; 1231 clocks = <&mmcc DSI2_M_AHB_CLK>, 1232 <&pxo_board>; 1233 #clock-cells = <1>; 1234 #phy-cells = <0>; 1235 1236 status = "disabled"; 1237 }; 1238 1239 mdp_port0: iommu@7500000 { 1240 compatible = "qcom,apq8064-iommu"; 1241 #iommu-cells = <1>; 1242 clock-names = 1243 "smmu_pclk", 1244 "iommu_clk"; 1245 clocks = 1246 <&mmcc SMMU_AHB_CLK>, 1247 <&mmcc MDP_AXI_CLK>; 1248 reg = <0x07500000 0x100000>; 1249 interrupts = 1250 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1252 qcom,ncb = <2>; 1253 }; 1254 1255 mdp_port1: iommu@7600000 { 1256 compatible = "qcom,apq8064-iommu"; 1257 #iommu-cells = <1>; 1258 clock-names = 1259 "smmu_pclk", 1260 "iommu_clk"; 1261 clocks = 1262 <&mmcc SMMU_AHB_CLK>, 1263 <&mmcc MDP_AXI_CLK>; 1264 reg = <0x07600000 0x100000>; 1265 interrupts = 1266 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1268 qcom,ncb = <2>; 1269 }; 1270 1271 gfx3d: iommu@7c00000 { 1272 compatible = "qcom,apq8064-iommu"; 1273 #iommu-cells = <1>; 1274 clock-names = 1275 "smmu_pclk", 1276 "iommu_clk"; 1277 clocks = 1278 <&mmcc SMMU_AHB_CLK>, 1279 <&mmcc GFX3D_AXI_CLK>; 1280 reg = <0x07c00000 0x100000>; 1281 interrupts = 1282 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1284 qcom,ncb = <3>; 1285 }; 1286 1287 gfx3d1: iommu@7d00000 { 1288 compatible = "qcom,apq8064-iommu"; 1289 #iommu-cells = <1>; 1290 clock-names = 1291 "smmu_pclk", 1292 "iommu_clk"; 1293 clocks = 1294 <&mmcc SMMU_AHB_CLK>, 1295 <&mmcc GFX3D_AXI_CLK>; 1296 reg = <0x07d00000 0x100000>; 1297 interrupts = 1298 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1300 qcom,ncb = <3>; 1301 }; 1302 1303 pcie: pcie@1b500000 { 1304 compatible = "qcom,pcie-apq8064"; 1305 reg = <0x1b500000 0x1000>, 1306 <0x1b502000 0x80>, 1307 <0x1b600000 0x100>, 1308 <0x0ff00000 0x100000>; 1309 reg-names = "dbi", "elbi", "parf", "config"; 1310 device_type = "pci"; 1311 linux,pci-domain = <0>; 1312 bus-range = <0x00 0xff>; 1313 num-lanes = <1>; 1314 #address-cells = <3>; 1315 #size-cells = <2>; 1316 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1317 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1318 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "msi"; 1320 #interrupt-cells = <1>; 1321 interrupt-map-mask = <0 0 0 0x7>; 1322 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1323 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1324 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1325 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1326 clocks = <&gcc PCIE_A_CLK>, 1327 <&gcc PCIE_H_CLK>, 1328 <&gcc PCIE_PHY_REF_CLK>; 1329 clock-names = "core", "iface", "phy"; 1330 resets = <&gcc PCIE_ACLK_RESET>, 1331 <&gcc PCIE_HCLK_RESET>, 1332 <&gcc PCIE_POR_RESET>, 1333 <&gcc PCIE_PCI_RESET>, 1334 <&gcc PCIE_PHY_RESET>; 1335 reset-names = "axi", "ahb", "por", "pci", "phy"; 1336 status = "disabled"; 1337 1338 pcie@0 { 1339 device_type = "pci"; 1340 reg = <0x0 0x0 0x0 0x0 0x0>; 1341 bus-range = <0x01 0xff>; 1342 1343 #address-cells = <3>; 1344 #size-cells = <2>; 1345 ranges; 1346 }; 1347 }; 1348 1349 hdmi: hdmi-tx@4a00000 { 1350 compatible = "qcom,hdmi-tx-8960"; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&hdmi_pinctrl>; 1353 reg = <0x04a00000 0x2f0>; 1354 reg-names = "core_physical"; 1355 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&mmcc HDMI_APP_CLK>, 1357 <&mmcc HDMI_M_AHB_CLK>, 1358 <&mmcc HDMI_S_AHB_CLK>; 1359 clock-names = "core", 1360 "master_iface", 1361 "slave_iface"; 1362 1363 phys = <&hdmi_phy>; 1364 1365 status = "disabled"; 1366 1367 ports { 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 1371 port@0 { 1372 reg = <0>; 1373 hdmi_in: endpoint { 1374 }; 1375 }; 1376 1377 port@1 { 1378 reg = <1>; 1379 hdmi_out: endpoint { 1380 }; 1381 }; 1382 }; 1383 }; 1384 1385 hdmi_phy: phy@4a00400 { 1386 compatible = "qcom,hdmi-phy-8960"; 1387 reg = <0x4a00400 0x60>, 1388 <0x4a00500 0x100>; 1389 reg-names = "hdmi_phy", 1390 "hdmi_pll"; 1391 1392 clocks = <&mmcc HDMI_S_AHB_CLK>; 1393 clock-names = "slave_iface"; 1394 #phy-cells = <0>; 1395 #clock-cells = <0>; 1396 1397 status = "disabled"; 1398 }; 1399 1400 mdp: display-controller@5100000 { 1401 compatible = "qcom,mdp4"; 1402 reg = <0x05100000 0xf0000>; 1403 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&mmcc MDP_CLK>, 1405 <&mmcc MDP_AHB_CLK>, 1406 <&mmcc MDP_AXI_CLK>, 1407 <&mmcc MDP_LUT_CLK>, 1408 <&mmcc HDMI_TV_CLK>, 1409 <&mmcc MDP_TV_CLK>; 1410 clock-names = "core_clk", 1411 "iface_clk", 1412 "bus_clk", 1413 "lut_clk", 1414 "hdmi_clk", 1415 "tv_clk"; 1416 1417 iommus = <&mdp_port0 0 1418 &mdp_port0 2 1419 &mdp_port1 0 1420 &mdp_port1 2>; 1421 1422 ports { 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 port@0 { 1427 reg = <0>; 1428 mdp_lvds_out: endpoint { 1429 }; 1430 }; 1431 1432 port@1 { 1433 reg = <1>; 1434 mdp_dsi1_out: endpoint { 1435 }; 1436 }; 1437 1438 port@2 { 1439 reg = <2>; 1440 mdp_dsi2_out: endpoint { 1441 }; 1442 }; 1443 1444 port@3 { 1445 reg = <3>; 1446 mdp_dtv_out: endpoint { 1447 }; 1448 }; 1449 }; 1450 }; 1451 1452 riva: riva-pil@3200800 { 1453 compatible = "qcom,riva-pil"; 1454 1455 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1456 reg-names = "ccu", "dxe", "pmu"; 1457 1458 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1459 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1460 interrupt-names = "wdog", "fatal"; 1461 1462 memory-region = <&wcnss_mem>; 1463 1464 status = "disabled"; 1465 1466 iris { 1467 compatible = "qcom,wcn3660"; 1468 1469 clocks = <&cxo_board>; 1470 clock-names = "xo"; 1471 }; 1472 1473 smd-edge { 1474 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1475 1476 qcom,ipc = <&l2cc 8 25>; 1477 qcom,smd-edge = <6>; 1478 1479 label = "riva"; 1480 1481 wcnss { 1482 compatible = "qcom,wcnss"; 1483 qcom,smd-channels = "WCNSS_CTRL"; 1484 1485 qcom,mmio = <&riva>; 1486 1487 bluetooth { 1488 compatible = "qcom,wcnss-bt"; 1489 }; 1490 1491 wifi { 1492 compatible = "qcom,wcnss-wlan"; 1493 1494 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "tx", "rx"; 1497 1498 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1499 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1500 }; 1501 }; 1502 }; 1503 }; 1504 1505 etb@1a01000 { 1506 compatible = "arm,coresight-etb10", "arm,primecell"; 1507 reg = <0x1a01000 0x1000>; 1508 1509 clocks = <&rpmcc RPM_QDSS_CLK>; 1510 clock-names = "apb_pclk"; 1511 1512 in-ports { 1513 port { 1514 etb_in: endpoint { 1515 remote-endpoint = <&replicator_out0>; 1516 }; 1517 }; 1518 }; 1519 }; 1520 1521 tpiu@1a03000 { 1522 compatible = "arm,coresight-tpiu", "arm,primecell"; 1523 reg = <0x1a03000 0x1000>; 1524 1525 clocks = <&rpmcc RPM_QDSS_CLK>; 1526 clock-names = "apb_pclk"; 1527 1528 in-ports { 1529 port { 1530 tpiu_in: endpoint { 1531 remote-endpoint = <&replicator_out1>; 1532 }; 1533 }; 1534 }; 1535 }; 1536 1537 replicator { 1538 compatible = "arm,coresight-static-replicator"; 1539 1540 clocks = <&rpmcc RPM_QDSS_CLK>; 1541 clock-names = "apb_pclk"; 1542 1543 out-ports { 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 1547 port@0 { 1548 reg = <0>; 1549 replicator_out0: endpoint { 1550 remote-endpoint = <&etb_in>; 1551 }; 1552 }; 1553 port@1 { 1554 reg = <1>; 1555 replicator_out1: endpoint { 1556 remote-endpoint = <&tpiu_in>; 1557 }; 1558 }; 1559 }; 1560 1561 in-ports { 1562 port { 1563 replicator_in: endpoint { 1564 remote-endpoint = <&funnel_out>; 1565 }; 1566 }; 1567 }; 1568 }; 1569 1570 funnel@1a04000 { 1571 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1572 reg = <0x1a04000 0x1000>; 1573 1574 clocks = <&rpmcc RPM_QDSS_CLK>; 1575 clock-names = "apb_pclk"; 1576 1577 in-ports { 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 1581 /* 1582 * Not described input ports: 1583 * 2 - connected to STM component 1584 * 3 - not-connected 1585 * 6 - not-connected 1586 * 7 - not-connected 1587 */ 1588 port@0 { 1589 reg = <0>; 1590 funnel_in0: endpoint { 1591 remote-endpoint = <&etm0_out>; 1592 }; 1593 }; 1594 port@1 { 1595 reg = <1>; 1596 funnel_in1: endpoint { 1597 remote-endpoint = <&etm1_out>; 1598 }; 1599 }; 1600 port@4 { 1601 reg = <4>; 1602 funnel_in4: endpoint { 1603 remote-endpoint = <&etm2_out>; 1604 }; 1605 }; 1606 port@5 { 1607 reg = <5>; 1608 funnel_in5: endpoint { 1609 remote-endpoint = <&etm3_out>; 1610 }; 1611 }; 1612 }; 1613 1614 out-ports { 1615 port { 1616 funnel_out: endpoint { 1617 remote-endpoint = <&replicator_in>; 1618 }; 1619 }; 1620 }; 1621 }; 1622 1623 etm@1a1c000 { 1624 compatible = "arm,coresight-etm3x", "arm,primecell"; 1625 reg = <0x1a1c000 0x1000>; 1626 1627 clocks = <&rpmcc RPM_QDSS_CLK>; 1628 clock-names = "apb_pclk"; 1629 1630 cpu = <&CPU0>; 1631 1632 out-ports { 1633 port { 1634 etm0_out: endpoint { 1635 remote-endpoint = <&funnel_in0>; 1636 }; 1637 }; 1638 }; 1639 }; 1640 1641 etm@1a1d000 { 1642 compatible = "arm,coresight-etm3x", "arm,primecell"; 1643 reg = <0x1a1d000 0x1000>; 1644 1645 clocks = <&rpmcc RPM_QDSS_CLK>; 1646 clock-names = "apb_pclk"; 1647 1648 cpu = <&CPU1>; 1649 1650 out-ports { 1651 port { 1652 etm1_out: endpoint { 1653 remote-endpoint = <&funnel_in1>; 1654 }; 1655 }; 1656 }; 1657 }; 1658 1659 etm@1a1e000 { 1660 compatible = "arm,coresight-etm3x", "arm,primecell"; 1661 reg = <0x1a1e000 0x1000>; 1662 1663 clocks = <&rpmcc RPM_QDSS_CLK>; 1664 clock-names = "apb_pclk"; 1665 1666 cpu = <&CPU2>; 1667 1668 out-ports { 1669 port { 1670 etm2_out: endpoint { 1671 remote-endpoint = <&funnel_in4>; 1672 }; 1673 }; 1674 }; 1675 }; 1676 1677 etm@1a1f000 { 1678 compatible = "arm,coresight-etm3x", "arm,primecell"; 1679 reg = <0x1a1f000 0x1000>; 1680 1681 clocks = <&rpmcc RPM_QDSS_CLK>; 1682 clock-names = "apb_pclk"; 1683 1684 cpu = <&CPU3>; 1685 1686 out-ports { 1687 port { 1688 etm3_out: endpoint { 1689 remote-endpoint = <&funnel_in5>; 1690 }; 1691 }; 1692 }; 1693 }; 1694 }; 1695}; 1696#include "qcom-apq8064-pins.dtsi" 1697