1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Copyright 2013 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6#include "vf610.dtsi" 7 8/ { 9 model = "VF610 Tower Board"; 10 compatible = "fsl,vf610-twr", "fsl,vf610"; 11 12 chosen { 13 bootargs = "console=ttyLP1,115200"; 14 }; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x8000000>; 19 }; 20 21 audio_ext: mclk_osc { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24576000>; 25 }; 26 27 enet_ext: eth_osc { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <50000000>; 31 }; 32 33 34 reg_3p3v: regulator-3p3v { 35 compatible = "regulator-fixed"; 36 regulator-name = "3P3V"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-always-on; 40 }; 41 42 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { 43 compatible = "regulator-fixed"; 44 regulator-name = "vcc_3v3_mcu"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 }; 48 49 sound { 50 compatible = "simple-audio-card"; 51 simple-audio-card,format = "i2s"; 52 simple-audio-card,widgets = 53 "Microphone", "Microphone Jack", 54 "Headphone", "Headphone Jack", 55 "Speaker", "Speaker Ext", 56 "Line", "Line In Jack"; 57 simple-audio-card,routing = 58 "MIC_IN", "Microphone Jack", 59 "Microphone Jack", "Mic Bias", 60 "LINE_IN", "Line In Jack", 61 "Headphone Jack", "HP_OUT", 62 "Speaker Ext", "LINE_OUT"; 63 64 simple-audio-card,cpu { 65 sound-dai = <&sai2>; 66 frame-master; 67 bitclock-master; 68 }; 69 70 simple-audio-card,codec { 71 sound-dai = <&codec>; 72 frame-master; 73 bitclock-master; 74 }; 75 }; 76}; 77 78&adc0 { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_adc0_ad5>; 81 vref-supply = <®_vcc_3v3_mcu>; 82 status = "okay"; 83}; 84 85&clks { 86 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; 87 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; 88 assigned-clocks = <&clks VF610_CLK_ENET_SEL>, 89 <&clks VF610_CLK_ENET_TS_SEL>; 90 assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, 91 <&clks VF610_CLK_ENET_EXT>; 92}; 93 94&dspi0 { 95 bus-num = <0>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_dspi0>; 98 status = "okay"; 99 100 sflash: at26df081a@0 { 101 #address-cells = <1>; 102 #size-cells = <1>; 103 compatible = "atmel,at26df081a"; 104 spi-max-frequency = <16000000>; 105 spi-cpol; 106 spi-cpha; 107 reg = <0>; 108 }; 109}; 110 111&edma0 { 112 status = "okay"; 113}; 114 115&esdhc1 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_esdhc1>; 118 bus-width = <4>; 119 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; 120 status = "okay"; 121}; 122 123&fec0 { 124 phy-mode = "rmii"; 125 phy-handle = <ðphy0>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_fec0>; 128 status = "okay"; 129 130 mdio { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 ethphy0: ethernet-phy@0 { 135 reg = <0>; 136 }; 137 138 ethphy1: ethernet-phy@1 { 139 reg = <1>; 140 }; 141 }; 142}; 143 144&fec1 { 145 phy-mode = "rmii"; 146 phy-handle = <ðphy1>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_fec1>; 149 status = "okay"; 150}; 151 152&i2c0 { 153 clock-frequency = <100000>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_i2c0>; 156 status = "okay"; 157 158 codec: sgtl5000@a { 159 #sound-dai-cells = <0>; 160 compatible = "fsl,sgtl5000"; 161 reg = <0x0a>; 162 VDDA-supply = <®_3p3v>; 163 VDDIO-supply = <®_3p3v>; 164 clocks = <&clks VF610_CLK_SAI2>; 165 }; 166}; 167 168&iomuxc { 169 pinctrl_adc0_ad5: adc0ad5grp { 170 fsl,pins = < 171 VF610_PAD_PTC30__ADC0_SE5 0xa1 172 >; 173 }; 174 175 pinctrl_dspi0: dspi0grp { 176 fsl,pins = < 177 VF610_PAD_PTB19__DSPI0_CS0 0x1182 178 VF610_PAD_PTB20__DSPI0_SIN 0x1181 179 VF610_PAD_PTB21__DSPI0_SOUT 0x1182 180 VF610_PAD_PTB22__DSPI0_SCK 0x1182 181 >; 182 }; 183 184 pinctrl_esdhc1: esdhc1grp { 185 fsl,pins = < 186 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 187 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 188 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 189 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 190 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 191 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 192 VF610_PAD_PTA7__GPIO_134 0x219d 193 >; 194 }; 195 196 pinctrl_fec0: fec0grp { 197 fsl,pins = < 198 VF610_PAD_PTA6__RMII_CLKIN 0x30d1 199 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 200 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 201 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 202 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 203 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 204 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 205 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 206 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 207 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 208 >; 209 }; 210 211 pinctrl_fec1: fec1grp { 212 fsl,pins = < 213 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 214 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 215 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 216 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 217 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 218 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 219 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 220 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 221 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 222 >; 223 }; 224 225 pinctrl_i2c0: i2c0grp { 226 fsl,pins = < 227 VF610_PAD_PTB14__I2C0_SCL 0x30d3 228 VF610_PAD_PTB15__I2C0_SDA 0x30d3 229 >; 230 }; 231 232 pinctrl_nfc: nfcgrp { 233 fsl,pins = < 234 VF610_PAD_PTD31__NF_IO15 0x28df 235 VF610_PAD_PTD30__NF_IO14 0x28df 236 VF610_PAD_PTD29__NF_IO13 0x28df 237 VF610_PAD_PTD28__NF_IO12 0x28df 238 VF610_PAD_PTD27__NF_IO11 0x28df 239 VF610_PAD_PTD26__NF_IO10 0x28df 240 VF610_PAD_PTD25__NF_IO9 0x28df 241 VF610_PAD_PTD24__NF_IO8 0x28df 242 VF610_PAD_PTD23__NF_IO7 0x28df 243 VF610_PAD_PTD22__NF_IO6 0x28df 244 VF610_PAD_PTD21__NF_IO5 0x28df 245 VF610_PAD_PTD20__NF_IO4 0x28df 246 VF610_PAD_PTD19__NF_IO3 0x28df 247 VF610_PAD_PTD18__NF_IO2 0x28df 248 VF610_PAD_PTD17__NF_IO1 0x28df 249 VF610_PAD_PTD16__NF_IO0 0x28df 250 VF610_PAD_PTB24__NF_WE_B 0x28c2 251 VF610_PAD_PTB25__NF_CE0_B 0x28c2 252 VF610_PAD_PTB27__NF_RE_B 0x28c2 253 VF610_PAD_PTC26__NF_RB_B 0x283d 254 VF610_PAD_PTC27__NF_ALE 0x28c2 255 VF610_PAD_PTC28__NF_CLE 0x28c2 256 >; 257 }; 258 259 pinctrl_pwm0: pwm0grp { 260 fsl,pins = < 261 VF610_PAD_PTB0__FTM0_CH0 0x1582 262 VF610_PAD_PTB1__FTM0_CH1 0x1582 263 VF610_PAD_PTB2__FTM0_CH2 0x1582 264 VF610_PAD_PTB3__FTM0_CH3 0x1582 265 >; 266 }; 267 268 pinctrl_sai2: sai2grp { 269 fsl,pins = < 270 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed 271 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee 272 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed 273 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed 274 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed 275 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed 276 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed 277 >; 278 }; 279 280 pinctrl_uart1: uart1grp { 281 fsl,pins = < 282 VF610_PAD_PTB4__UART1_TX 0x21a2 283 VF610_PAD_PTB5__UART1_RX 0x21a1 284 >; 285 }; 286 287 pinctrl_uart2: uart2grp { 288 fsl,pins = < 289 VF610_PAD_PTB6__UART2_TX 0x21a2 290 VF610_PAD_PTB7__UART2_RX 0x21a1 291 >; 292 }; 293}; 294 295&nfc { 296 assigned-clocks = <&clks VF610_CLK_NFC>; 297 assigned-clock-rates = <33000000>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_nfc>; 300 status = "okay"; 301 302 nand@0 { 303 compatible = "fsl,vf610-nfc-nandcs"; 304 reg = <0>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 nand-bus-width = <16>; 308 nand-ecc-mode = "hw"; 309 nand-ecc-strength = <24>; 310 nand-ecc-step-size = <2048>; 311 nand-on-flash-bbt; 312 }; 313}; 314 315&pwm0 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_pwm0>; 318 status = "okay"; 319}; 320 321&sai2 { 322 #sound-dai-cells = <0>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_sai2>; 325 status = "okay"; 326}; 327 328&uart1 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart1>; 331 status = "okay"; 332}; 333 334&uart2 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart2>; 337 status = "okay"; 338}; 339 340&usbdev0 { 341 disable-over-current; 342 status = "okay"; 343}; 344 345&usbh1 { 346 disable-over-current; 347 status = "okay"; 348}; 349 350&usbmisc0 { 351 status = "okay"; 352}; 353 354&usbmisc1 { 355 status = "okay"; 356}; 357 358&usbphy0 { 359 status = "okay"; 360}; 361 362&usbphy1 { 363 status = "okay"; 364}; 365