1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/thermal/thermal.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 interrupt-parent = <&gic>; 13 14 aliases { 15 crypto = &crypto; 16 ethernet0 = &enet0; 17 ethernet1 = &enet1; 18 ethernet2 = &enet2; 19 rtc1 = &ftm_alarm0; 20 serial0 = &lpuart0; 21 serial1 = &lpuart1; 22 serial2 = &lpuart2; 23 serial3 = &lpuart3; 24 serial4 = &lpuart4; 25 serial5 = &lpuart5; 26 sysclk = &sysclk; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@f00 { 34 compatible = "arm,cortex-a7"; 35 device_type = "cpu"; 36 reg = <0xf00>; 37 clocks = <&clockgen 1 0>; 38 #cooling-cells = <2>; 39 }; 40 41 cpu1: cpu@f01 { 42 compatible = "arm,cortex-a7"; 43 device_type = "cpu"; 44 reg = <0xf01>; 45 clocks = <&clockgen 1 0>; 46 #cooling-cells = <2>; 47 }; 48 }; 49 50 memory@0 { 51 device_type = "memory"; 52 reg = <0x0 0x0 0x0 0x0>; 53 }; 54 55 sysclk: sysclk { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <100000000>; 59 clock-output-names = "sysclk"; 60 }; 61 62 timer { 63 compatible = "arm,armv7-timer"; 64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a7-pmu"; 72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 74 interrupt-affinity = <&cpu0>, <&cpu1>; 75 }; 76 77 reboot { 78 compatible = "syscon-reboot"; 79 regmap = <&dcfg>; 80 offset = <0xb0>; 81 mask = <0x02>; 82 }; 83 84 soc { 85 compatible = "simple-bus"; 86 #address-cells = <2>; 87 #size-cells = <2>; 88 device_type = "soc"; 89 interrupt-parent = <&gic>; 90 ranges; 91 92 ddr: memory-controller@1080000 { 93 compatible = "fsl,qoriq-memory-controller"; 94 reg = <0x0 0x1080000 0x0 0x1000>; 95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 98 gic: interrupt-controller@1401000 { 99 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 100 #interrupt-cells = <3>; 101 interrupt-controller; 102 reg = <0x0 0x1401000 0x0 0x1000>, 103 <0x0 0x1402000 0x0 0x2000>, 104 <0x0 0x1404000 0x0 0x2000>, 105 <0x0 0x1406000 0x0 0x2000>; 106 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 107 108 }; 109 110 msi1: msi-controller@1570e00 { 111 compatible = "fsl,ls1021a-msi"; 112 reg = <0x0 0x1570e00 0x0 0x8>; 113 msi-controller; 114 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 117 msi2: msi-controller@1570e08 { 118 compatible = "fsl,ls1021a-msi"; 119 reg = <0x0 0x1570e08 0x0 0x8>; 120 msi-controller; 121 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 ifc: memory-controller@1530000 { 125 compatible = "fsl,ifc"; 126 reg = <0x0 0x1530000 0x0 0x10000>; 127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 128 status = "disabled"; 129 }; 130 131 sfp: efuse@1e80000 { 132 compatible = "fsl,ls1021a-sfp"; 133 reg = <0x0 0x1e80000 0x0 0x10000>; 134 clocks = <&clockgen 4 3>; 135 clock-names = "sfp"; 136 }; 137 138 dcfg: dcfg@1ee0000 { 139 compatible = "fsl,ls1021a-dcfg", "syscon"; 140 reg = <0x0 0x1ee0000 0x0 0x1000>; 141 big-endian; 142 }; 143 144 qspi: spi@1550000 { 145 compatible = "fsl,ls1021a-qspi"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 reg = <0x0 0x1550000 0x0 0x10000>, 149 <0x0 0x40000000 0x0 0x20000000>; 150 reg-names = "QuadSPI", "QuadSPI-memory"; 151 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 152 clock-names = "qspi_en", "qspi"; 153 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 154 status = "disabled"; 155 }; 156 157 esdhc: mmc@1560000 { 158 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 159 reg = <0x0 0x1560000 0x0 0x10000>; 160 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 161 clock-frequency = <0>; 162 voltage-ranges = <1800 1800 3300 3300>; 163 sdhci,auto-cmd12; 164 bus-width = <4>; 165 status = "disabled"; 166 }; 167 168 sata: sata@3200000 { 169 compatible = "fsl,ls1021a-ahci"; 170 reg = <0x0 0x3200000 0x0 0x10000>, 171 <0x0 0x20220520 0x0 0x4>; 172 reg-names = "ahci", "sata-ecc"; 173 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&clockgen 4 1>; 175 dma-coherent; 176 status = "disabled"; 177 }; 178 179 scfg: scfg@1570000 { 180 compatible = "fsl,ls1021a-scfg", "syscon"; 181 reg = <0x0 0x1570000 0x0 0x10000>; 182 big-endian; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 ranges = <0x0 0x0 0x1570000 0x10000>; 186 187 extirq: interrupt-controller@1ac { 188 compatible = "fsl,ls1021a-extirq"; 189 #interrupt-cells = <2>; 190 #address-cells = <0>; 191 interrupt-controller; 192 reg = <0x1ac 4>; 193 interrupt-map = 194 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 195 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 196 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 197 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 198 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 199 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-map-mask = <0x7 0x0>; 201 }; 202 }; 203 204 crypto: crypto@1700000 { 205 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 206 fsl,sec-era = <7>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 reg = <0x0 0x1700000 0x0 0x100000>; 210 ranges = <0x0 0x0 0x1700000 0x100000>; 211 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 212 dma-coherent; 213 214 sec_jr0: jr@10000 { 215 compatible = "fsl,sec-v5.0-job-ring", 216 "fsl,sec-v4.0-job-ring"; 217 reg = <0x10000 0x10000>; 218 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 sec_jr1: jr@20000 { 222 compatible = "fsl,sec-v5.0-job-ring", 223 "fsl,sec-v4.0-job-ring"; 224 reg = <0x20000 0x10000>; 225 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 226 }; 227 228 sec_jr2: jr@30000 { 229 compatible = "fsl,sec-v5.0-job-ring", 230 "fsl,sec-v4.0-job-ring"; 231 reg = <0x30000 0x10000>; 232 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 233 }; 234 235 sec_jr3: jr@40000 { 236 compatible = "fsl,sec-v5.0-job-ring", 237 "fsl,sec-v4.0-job-ring"; 238 reg = <0x40000 0x10000>; 239 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 240 }; 241 242 }; 243 244 clockgen: clocking@1ee1000 { 245 compatible = "fsl,ls1021a-clockgen"; 246 reg = <0x0 0x1ee1000 0x0 0x1000>; 247 #clock-cells = <2>; 248 clocks = <&sysclk>; 249 }; 250 251 tmu: tmu@1f00000 { 252 compatible = "fsl,qoriq-tmu"; 253 reg = <0x0 0x1f00000 0x0 0x10000>; 254 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 255 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; 256 fsl,tmu-calibration = <0x00000000 0x00000020>, 257 <0x00000001 0x00000024>, 258 <0x00000002 0x0000002a>, 259 <0x00000003 0x00000032>, 260 <0x00000004 0x00000038>, 261 <0x00000005 0x0000003e>, 262 <0x00000006 0x00000043>, 263 <0x00000007 0x0000004a>, 264 <0x00000008 0x00000050>, 265 <0x00000009 0x00000059>, 266 <0x0000000a 0x0000005f>, 267 <0x0000000b 0x00000066>, 268 269 <0x00010000 0x00000023>, 270 <0x00010001 0x0000002b>, 271 <0x00010002 0x00000033>, 272 <0x00010003 0x0000003a>, 273 <0x00010004 0x00000042>, 274 <0x00010005 0x0000004a>, 275 <0x00010006 0x00000054>, 276 <0x00010007 0x0000005c>, 277 <0x00010008 0x00000065>, 278 <0x00010009 0x0000006f>, 279 280 <0x00020000 0x00000029>, 281 <0x00020001 0x00000033>, 282 <0x00020002 0x0000003d>, 283 <0x00020003 0x00000048>, 284 <0x00020004 0x00000054>, 285 <0x00020005 0x00000060>, 286 <0x00020006 0x0000006c>, 287 288 <0x00030000 0x00000025>, 289 <0x00030001 0x00000033>, 290 <0x00030002 0x00000043>, 291 <0x00030003 0x00000055>; 292 #thermal-sensor-cells = <1>; 293 }; 294 295 dspi0: spi@2100000 { 296 compatible = "fsl,ls1021a-v1.0-dspi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x2100000 0x0 0x10000>; 300 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 301 clock-names = "dspi"; 302 clocks = <&clockgen 4 1>; 303 spi-num-chipselects = <6>; 304 big-endian; 305 status = "disabled"; 306 }; 307 308 dspi1: spi@2110000 { 309 compatible = "fsl,ls1021a-v1.0-dspi"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 reg = <0x0 0x2110000 0x0 0x10000>; 313 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 314 clock-names = "dspi"; 315 clocks = <&clockgen 4 1>; 316 spi-num-chipselects = <6>; 317 big-endian; 318 status = "disabled"; 319 }; 320 321 i2c0: i2c@2180000 { 322 compatible = "fsl,vf610-i2c"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x0 0x2180000 0x0 0x10000>; 326 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clockgen 4 1>; 328 dma-names = "rx", "tx"; 329 dmas = <&edma0 1 38>, <&edma0 1 39>; 330 status = "disabled"; 331 }; 332 333 i2c1: i2c@2190000 { 334 compatible = "fsl,vf610-i2c"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0x0 0x2190000 0x0 0x10000>; 338 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clockgen 4 1>; 340 dma-names = "rx", "tx"; 341 dmas = <&edma0 1 36>, <&edma0 1 37>; 342 status = "disabled"; 343 }; 344 345 i2c2: i2c@21a0000 { 346 compatible = "fsl,vf610-i2c"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <0x0 0x21a0000 0x0 0x10000>; 350 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clockgen 4 1>; 352 dma-names = "rx", "tx"; 353 dmas = <&edma0 1 34>, <&edma0 1 35>; 354 status = "disabled"; 355 }; 356 357 uart0: serial@21c0500 { 358 compatible = "fsl,16550-FIFO64", "ns16550a"; 359 reg = <0x0 0x21c0500 0x0 0x100>; 360 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 361 clock-frequency = <0>; 362 fifo-size = <15>; 363 status = "disabled"; 364 }; 365 366 uart1: serial@21c0600 { 367 compatible = "fsl,16550-FIFO64", "ns16550a"; 368 reg = <0x0 0x21c0600 0x0 0x100>; 369 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 370 clock-frequency = <0>; 371 fifo-size = <15>; 372 status = "disabled"; 373 }; 374 375 uart2: serial@21d0500 { 376 compatible = "fsl,16550-FIFO64", "ns16550a"; 377 reg = <0x0 0x21d0500 0x0 0x100>; 378 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 379 clock-frequency = <0>; 380 fifo-size = <15>; 381 status = "disabled"; 382 }; 383 384 uart3: serial@21d0600 { 385 compatible = "fsl,16550-FIFO64", "ns16550a"; 386 reg = <0x0 0x21d0600 0x0 0x100>; 387 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 388 clock-frequency = <0>; 389 fifo-size = <15>; 390 status = "disabled"; 391 }; 392 393 counter0: counter@29d0000 { 394 compatible = "fsl,ftm-quaddec"; 395 reg = <0x0 0x29d0000 0x0 0x10000>; 396 big-endian; 397 status = "disabled"; 398 }; 399 400 counter1: counter@29e0000 { 401 compatible = "fsl,ftm-quaddec"; 402 reg = <0x0 0x29e0000 0x0 0x10000>; 403 big-endian; 404 status = "disabled"; 405 }; 406 407 counter2: counter@29f0000 { 408 compatible = "fsl,ftm-quaddec"; 409 reg = <0x0 0x29f0000 0x0 0x10000>; 410 big-endian; 411 status = "disabled"; 412 }; 413 414 counter3: counter@2a00000 { 415 compatible = "fsl,ftm-quaddec"; 416 reg = <0x0 0x2a00000 0x0 0x10000>; 417 big-endian; 418 status = "disabled"; 419 }; 420 421 gpio0: gpio@2300000 { 422 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 423 reg = <0x0 0x2300000 0x0 0x10000>; 424 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 gpio1: gpio@2310000 { 432 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 433 reg = <0x0 0x2310000 0x0 0x10000>; 434 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 }; 440 441 gpio2: gpio@2320000 { 442 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 443 reg = <0x0 0x2320000 0x0 0x10000>; 444 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 }; 450 451 gpio3: gpio@2330000 { 452 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 453 reg = <0x0 0x2330000 0x0 0x10000>; 454 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 }; 460 461 lpuart0: serial@2950000 { 462 compatible = "fsl,ls1021a-lpuart"; 463 reg = <0x0 0x2950000 0x0 0x1000>; 464 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&sysclk>; 466 clock-names = "ipg"; 467 status = "disabled"; 468 }; 469 470 lpuart1: serial@2960000 { 471 compatible = "fsl,ls1021a-lpuart"; 472 reg = <0x0 0x2960000 0x0 0x1000>; 473 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clockgen 4 1>; 475 clock-names = "ipg"; 476 status = "disabled"; 477 }; 478 479 lpuart2: serial@2970000 { 480 compatible = "fsl,ls1021a-lpuart"; 481 reg = <0x0 0x2970000 0x0 0x1000>; 482 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clockgen 4 1>; 484 clock-names = "ipg"; 485 status = "disabled"; 486 }; 487 488 lpuart3: serial@2980000 { 489 compatible = "fsl,ls1021a-lpuart"; 490 reg = <0x0 0x2980000 0x0 0x1000>; 491 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clockgen 4 1>; 493 clock-names = "ipg"; 494 status = "disabled"; 495 }; 496 497 lpuart4: serial@2990000 { 498 compatible = "fsl,ls1021a-lpuart"; 499 reg = <0x0 0x2990000 0x0 0x1000>; 500 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&clockgen 4 1>; 502 clock-names = "ipg"; 503 status = "disabled"; 504 }; 505 506 lpuart5: serial@29a0000 { 507 compatible = "fsl,ls1021a-lpuart"; 508 reg = <0x0 0x29a0000 0x0 0x1000>; 509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clockgen 4 1>; 511 clock-names = "ipg"; 512 status = "disabled"; 513 }; 514 515 pwm0: pwm@29d0000 { 516 compatible = "fsl,vf610-ftm-pwm"; 517 #pwm-cells = <3>; 518 reg = <0x0 0x29d0000 0x0 0x10000>; 519 clock-names = "ftm_sys", "ftm_ext", 520 "ftm_fix", "ftm_cnt_clk_en"; 521 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 522 <&clockgen 4 1>, <&clockgen 4 1>; 523 big-endian; 524 status = "disabled"; 525 }; 526 527 pwm1: pwm@29e0000 { 528 compatible = "fsl,vf610-ftm-pwm"; 529 #pwm-cells = <3>; 530 reg = <0x0 0x29e0000 0x0 0x10000>; 531 clock-names = "ftm_sys", "ftm_ext", 532 "ftm_fix", "ftm_cnt_clk_en"; 533 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 534 <&clockgen 4 1>, <&clockgen 4 1>; 535 big-endian; 536 status = "disabled"; 537 }; 538 539 pwm2: pwm@29f0000 { 540 compatible = "fsl,vf610-ftm-pwm"; 541 #pwm-cells = <3>; 542 reg = <0x0 0x29f0000 0x0 0x10000>; 543 clock-names = "ftm_sys", "ftm_ext", 544 "ftm_fix", "ftm_cnt_clk_en"; 545 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 546 <&clockgen 4 1>, <&clockgen 4 1>; 547 big-endian; 548 status = "disabled"; 549 }; 550 551 pwm3: pwm@2a00000 { 552 compatible = "fsl,vf610-ftm-pwm"; 553 #pwm-cells = <3>; 554 reg = <0x0 0x2a00000 0x0 0x10000>; 555 clock-names = "ftm_sys", "ftm_ext", 556 "ftm_fix", "ftm_cnt_clk_en"; 557 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 558 <&clockgen 4 1>, <&clockgen 4 1>; 559 big-endian; 560 status = "disabled"; 561 }; 562 563 pwm4: pwm@2a10000 { 564 compatible = "fsl,vf610-ftm-pwm"; 565 #pwm-cells = <3>; 566 reg = <0x0 0x2a10000 0x0 0x10000>; 567 clock-names = "ftm_sys", "ftm_ext", 568 "ftm_fix", "ftm_cnt_clk_en"; 569 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 570 <&clockgen 4 1>, <&clockgen 4 1>; 571 big-endian; 572 status = "disabled"; 573 }; 574 575 pwm5: pwm@2a20000 { 576 compatible = "fsl,vf610-ftm-pwm"; 577 #pwm-cells = <3>; 578 reg = <0x0 0x2a20000 0x0 0x10000>; 579 clock-names = "ftm_sys", "ftm_ext", 580 "ftm_fix", "ftm_cnt_clk_en"; 581 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 582 <&clockgen 4 1>, <&clockgen 4 1>; 583 big-endian; 584 status = "disabled"; 585 }; 586 587 pwm6: pwm@2a30000 { 588 compatible = "fsl,vf610-ftm-pwm"; 589 #pwm-cells = <3>; 590 reg = <0x0 0x2a30000 0x0 0x10000>; 591 clock-names = "ftm_sys", "ftm_ext", 592 "ftm_fix", "ftm_cnt_clk_en"; 593 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 594 <&clockgen 4 1>, <&clockgen 4 1>; 595 big-endian; 596 status = "disabled"; 597 }; 598 599 pwm7: pwm@2a40000 { 600 compatible = "fsl,vf610-ftm-pwm"; 601 #pwm-cells = <3>; 602 reg = <0x0 0x2a40000 0x0 0x10000>; 603 clock-names = "ftm_sys", "ftm_ext", 604 "ftm_fix", "ftm_cnt_clk_en"; 605 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 606 <&clockgen 4 1>, <&clockgen 4 1>; 607 big-endian; 608 status = "disabled"; 609 }; 610 611 wdog0: watchdog@2ad0000 { 612 compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; 613 reg = <0x0 0x2ad0000 0x0 0x10000>; 614 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clockgen 4 1>; 616 big-endian; 617 }; 618 619 sai1: sai@2b50000 { 620 #sound-dai-cells = <0>; 621 compatible = "fsl,vf610-sai"; 622 reg = <0x0 0x2b50000 0x0 0x10000>; 623 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 625 <&clockgen 4 1>, <&clockgen 4 1>; 626 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 627 dma-names = "rx", "tx"; 628 dmas = <&edma0 1 46>, 629 <&edma0 1 47>; 630 status = "disabled"; 631 }; 632 633 sai2: sai@2b60000 { 634 #sound-dai-cells = <0>; 635 compatible = "fsl,vf610-sai"; 636 reg = <0x0 0x2b60000 0x0 0x10000>; 637 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 639 <&clockgen 4 1>, <&clockgen 4 1>; 640 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 641 dma-names = "rx", "tx"; 642 dmas = <&edma0 1 44>, 643 <&edma0 1 45>; 644 status = "disabled"; 645 }; 646 647 edma0: dma-controller@2c00000 { 648 #dma-cells = <2>; 649 compatible = "fsl,vf610-edma"; 650 reg = <0x0 0x2c00000 0x0 0x10000>, 651 <0x0 0x2c10000 0x0 0x10000>, 652 <0x0 0x2c20000 0x0 0x10000>; 653 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "edma-tx", "edma-err"; 656 dma-channels = <32>; 657 big-endian; 658 clock-names = "dmamux0", "dmamux1"; 659 clocks = <&clockgen 4 1>, 660 <&clockgen 4 1>; 661 }; 662 663 dcu: dcu@2ce0000 { 664 compatible = "fsl,ls1021a-dcu"; 665 reg = <0x0 0x2ce0000 0x0 0x10000>; 666 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&clockgen 4 0>, 668 <&clockgen 4 0>; 669 clock-names = "dcu", "pix"; 670 big-endian; 671 status = "disabled"; 672 }; 673 674 mdio0: mdio@2d24000 { 675 compatible = "gianfar"; 676 device_type = "mdio"; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 reg = <0x0 0x2d24000 0x0 0x4000>, 680 <0x0 0x2d10030 0x0 0x4>; 681 }; 682 683 mdio1: mdio@2d64000 { 684 compatible = "gianfar"; 685 device_type = "mdio"; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 reg = <0x0 0x2d64000 0x0 0x4000>, 689 <0x0 0x2d50030 0x0 0x4>; 690 }; 691 692 ptp_clock@2d10e00 { 693 compatible = "fsl,etsec-ptp"; 694 reg = <0x0 0x2d10e00 0x0 0xb0>; 695 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 696 fsl,tclk-period = <5>; 697 fsl,tmr-prsc = <2>; 698 fsl,tmr-add = <0xaaaaaaab>; 699 fsl,tmr-fiper1 = <999999995>; 700 fsl,tmr-fiper2 = <999999995>; 701 fsl,max-adj = <499999999>; 702 fsl,extts-fifo; 703 }; 704 705 enet0: ethernet@2d10000 { 706 compatible = "fsl,etsec2"; 707 reg = <0x0 0x2d10000 0x0 0x5000>; 708 device_type = "network"; 709 #address-cells = <2>; 710 #size-cells = <2>; 711 interrupt-parent = <&gic>; 712 model = "eTSEC"; 713 fsl,magic-packet; 714 ranges; 715 dma-coherent; 716 717 queue-group@2d10000 { 718 reg = <0x0 0x2d10000 0x0 0x1000>; 719 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 722 }; 723 724 queue-group@2d14000 { 725 reg = <0x0 0x2d14000 0x0 0x1000>; 726 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 729 }; 730 }; 731 732 enet1: ethernet@2d50000 { 733 compatible = "fsl,etsec2"; 734 reg = <0x0 0x2d50000 0x0 0x5000>; 735 device_type = "network"; 736 #address-cells = <2>; 737 #size-cells = <2>; 738 interrupt-parent = <&gic>; 739 model = "eTSEC"; 740 ranges; 741 dma-coherent; 742 743 queue-group@2d50000 { 744 reg = <0x0 0x2d50000 0x0 0x1000>; 745 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 queue-group@2d54000 { 751 reg = <0x0 0x2d54000 0x0 0x1000>; 752 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 755 }; 756 }; 757 758 enet2: ethernet@2d90000 { 759 compatible = "fsl,etsec2"; 760 reg = <0x0 0x2d90000 0x0 0x5000>; 761 device_type = "network"; 762 #address-cells = <2>; 763 #size-cells = <2>; 764 interrupt-parent = <&gic>; 765 model = "eTSEC"; 766 ranges; 767 dma-coherent; 768 769 queue-group@2d90000 { 770 reg = <0x0 0x2d90000 0x0 0x1000>; 771 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 774 }; 775 776 queue-group@2d94000 { 777 reg = <0x0 0x2d94000 0x0 0x1000>; 778 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 781 }; 782 }; 783 784 usb2: usb@8600000 { 785 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 786 reg = <0x0 0x8600000 0x0 0x1000>; 787 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 788 dr_mode = "host"; 789 phy_type = "ulpi"; 790 }; 791 792 usb3: usb@3100000 { 793 compatible = "snps,dwc3"; 794 reg = <0x0 0x3100000 0x0 0x10000>; 795 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 796 dr_mode = "host"; 797 snps,quirk-frame-length-adjustment = <0x20>; 798 snps,dis_rxdet_inp3_quirk; 799 usb3-lpm-capable; 800 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 801 }; 802 803 pcie@3400000 { 804 compatible = "fsl,ls1021a-pcie"; 805 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ 806 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 807 reg-names = "regs", "config"; 808 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 809 fsl,pcie-scfg = <&scfg 0>; 810 #address-cells = <3>; 811 #size-cells = <2>; 812 device_type = "pci"; 813 num-viewport = <6>; 814 bus-range = <0x0 0xff>; 815 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ 816 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 817 msi-parent = <&msi1>, <&msi2>; 818 #interrupt-cells = <1>; 819 interrupt-map-mask = <0 0 0 7>; 820 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 821 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 822 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 823 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 824 status = "disabled"; 825 }; 826 827 pcie@3500000 { 828 compatible = "fsl,ls1021a-pcie"; 829 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ 830 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 831 reg-names = "regs", "config"; 832 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 833 fsl,pcie-scfg = <&scfg 1>; 834 #address-cells = <3>; 835 #size-cells = <2>; 836 device_type = "pci"; 837 num-viewport = <6>; 838 bus-range = <0x0 0xff>; 839 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ 840 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 841 msi-parent = <&msi1>, <&msi2>; 842 #interrupt-cells = <1>; 843 interrupt-map-mask = <0 0 0 7>; 844 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 845 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 846 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 847 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 848 status = "disabled"; 849 }; 850 851 can0: can@2a70000 { 852 compatible = "fsl,ls1021ar2-flexcan"; 853 reg = <0x0 0x2a70000 0x0 0x1000>; 854 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 856 clock-names = "ipg", "per"; 857 big-endian; 858 status = "disabled"; 859 }; 860 861 can1: can@2a80000 { 862 compatible = "fsl,ls1021ar2-flexcan"; 863 reg = <0x0 0x2a80000 0x0 0x1000>; 864 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 866 clock-names = "ipg", "per"; 867 big-endian; 868 status = "disabled"; 869 }; 870 871 can2: can@2a90000 { 872 compatible = "fsl,ls1021ar2-flexcan"; 873 reg = <0x0 0x2a90000 0x0 0x1000>; 874 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 876 clock-names = "ipg", "per"; 877 big-endian; 878 status = "disabled"; 879 }; 880 881 can3: can@2aa0000 { 882 compatible = "fsl,ls1021ar2-flexcan"; 883 reg = <0x0 0x2aa0000 0x0 0x1000>; 884 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 886 clock-names = "ipg", "per"; 887 big-endian; 888 status = "disabled"; 889 }; 890 891 ocram1: sram@10000000 { 892 compatible = "mmio-sram"; 893 reg = <0x0 0x10000000 0x0 0x10000>; 894 #address-cells = <1>; 895 #size-cells = <1>; 896 ranges = <0x0 0x0 0x10000000 0x10000>; 897 }; 898 899 ocram2: sram@10010000 { 900 compatible = "mmio-sram"; 901 reg = <0x0 0x10010000 0x0 0x10000>; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 ranges = <0x0 0x0 0x10010000 0x10000>; 905 }; 906 907 qdma: dma-controller@8388000 { 908 compatible = "fsl,ls1021a-qdma"; 909 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 910 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 911 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 912 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "qdma-error", 916 "qdma-queue0", "qdma-queue1"; 917 #dma-cells = <2>; 918 dma-channels = <8>; 919 block-number = <1>; 920 block-offset = <0x1000>; 921 fsl,dma-queues = <2>; 922 status-sizes = <64>; 923 queue-sizes = <64 64>; 924 big-endian; 925 }; 926 927 rcpm: wakeup-controller@1ee2140 { 928 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; 929 reg = <0x0 0x1ee2140 0x0 0x8>; 930 #fsl,rcpm-wakeup-cells = <2>; 931 }; 932 933 ftm_alarm0: rtc@29d0000 { 934 compatible = "fsl,ls1021a-ftm-alarm"; 935 reg = <0x0 0x29d0000 0x0 0x10000>; 936 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; 937 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 938 big-endian; 939 }; 940 }; 941 942 thermal-zones { 943 cpu_thermal: cpu-thermal { 944 polling-delay-passive = <1000>; 945 polling-delay = <5000>; 946 947 thermal-sensors = <&tmu 0>; 948 949 trips { 950 cpu_alert: cpu-alert { 951 temperature = <85000>; 952 hysteresis = <2000>; 953 type = "passive"; 954 }; 955 cpu_crit: cpu-crit { 956 temperature = <95000>; 957 hysteresis = <2000>; 958 type = "critical"; 959 }; 960 }; 961 962 cooling-maps { 963 map0 { 964 trip = <&cpu_alert>; 965 cooling-device = 966 <&cpu0 THERMAL_NO_LIMIT 967 THERMAL_NO_LIMIT>, 968 <&cpu1 THERMAL_NO_LIMIT 969 THERMAL_NO_LIMIT>; 970 }; 971 }; 972 }; 973 }; 974}; 975