1// SPDX-License-Identifier: GPL-2.0 2/* Copyright 2016-2018 NXP Semiconductors 3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> 4 */ 5 6/dts-v1/; 7#include "ls1021a.dtsi" 8 9/ { 10 model = "NXP LS1021A-TSN Board"; 11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a"; 12 13 sys_mclk: clock-mclk { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <24576000>; 17 }; 18 19 reg_vdda_codec: regulator-3V3 { 20 compatible = "regulator-fixed"; 21 regulator-name = "3P3V"; 22 regulator-min-microvolt = <3300000>; 23 regulator-max-microvolt = <3300000>; 24 regulator-always-on; 25 }; 26 27 reg_vddio_codec: regulator-2V5 { 28 compatible = "regulator-fixed"; 29 regulator-name = "2P5V"; 30 regulator-min-microvolt = <2500000>; 31 regulator-max-microvolt = <2500000>; 32 regulator-always-on; 33 }; 34}; 35 36&dspi0 { 37 bus-num = <0>; 38 status = "okay"; 39 40 /* ADG704BRMZ 1:4 SPI mux/demux */ 41 sja1105: ethernet-switch@1 { 42 reg = <0x1>; 43 compatible = "nxp,sja1105t"; 44 /* 12 MHz */ 45 spi-max-frequency = <12000000>; 46 /* Sample data on trailing clock edge */ 47 spi-cpha; 48 /* SPI controller settings for SJA1105 timing requirements */ 49 fsl,spi-cs-sck-delay = <1000>; 50 fsl,spi-sck-cs-delay = <1000>; 51 52 ports { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 port@0 { 57 /* ETH5 written on chassis */ 58 label = "swp5"; 59 phy-handle = <&rgmii_phy6>; 60 phy-mode = "rgmii-id"; 61 reg = <0>; 62 }; 63 64 port@1 { 65 /* ETH2 written on chassis */ 66 label = "swp2"; 67 phy-handle = <&rgmii_phy3>; 68 phy-mode = "rgmii-id"; 69 reg = <1>; 70 }; 71 72 port@2 { 73 /* ETH3 written on chassis */ 74 label = "swp3"; 75 phy-handle = <&rgmii_phy4>; 76 phy-mode = "rgmii-id"; 77 reg = <2>; 78 }; 79 80 port@3 { 81 /* ETH4 written on chassis */ 82 label = "swp4"; 83 phy-handle = <&rgmii_phy5>; 84 phy-mode = "rgmii-id"; 85 reg = <3>; 86 }; 87 88 port@4 { 89 /* Internal port connected to eth2 */ 90 ethernet = <&enet2>; 91 phy-mode = "rgmii"; 92 rx-internal-delay-ps = <0>; 93 tx-internal-delay-ps = <0>; 94 reg = <4>; 95 96 fixed-link { 97 speed = <1000>; 98 full-duplex; 99 }; 100 }; 101 }; 102 }; 103}; 104 105&enet0 { 106 tbi-handle = <&tbi0>; 107 phy-handle = <&sgmii_phy2>; 108 phy-mode = "sgmii"; 109 status = "okay"; 110}; 111 112&enet1 { 113 tbi-handle = <&tbi1>; 114 phy-handle = <&sgmii_phy1>; 115 phy-mode = "sgmii"; 116 status = "okay"; 117}; 118 119/* RGMII delays added via PCB traces */ 120&enet2 { 121 phy-mode = "rgmii"; 122 status = "okay"; 123 124 fixed-link { 125 speed = <1000>; 126 full-duplex; 127 }; 128}; 129 130&esdhc { 131 status = "okay"; 132}; 133 134&i2c0 { 135 status = "okay"; 136 137 /* 3 axis accelerometer */ 138 accelerometer@1e { 139 compatible = "fsl,fxls8471"; 140 reg = <0x1e>; 141 }; 142 143 /* Audio codec (SAI2) */ 144 audio-codec@2a { 145 compatible = "fsl,sgtl5000"; 146 VDDIO-supply = <®_vddio_codec>; 147 VDDA-supply = <®_vdda_codec>; 148 #sound-dai-cells = <0>; 149 clocks = <&sys_mclk>; 150 reg = <0x2a>; 151 }; 152 153 /* Current sensing circuit for 1V VDDCORE PMIC rail */ 154 current-sensor@44 { 155 compatible = "ti,ina220"; 156 shunt-resistor = <1000>; 157 reg = <0x44>; 158 }; 159 160 /* Current sensing circuit for 12V VCC rail */ 161 current-sensor@45 { 162 compatible = "ti,ina220"; 163 shunt-resistor = <1000>; 164 reg = <0x45>; 165 }; 166 167 /* Thermal monitor - case */ 168 temperature-sensor@48 { 169 compatible = "national,lm75"; 170 reg = <0x48>; 171 }; 172 173 /* Thermal monitor - chip */ 174 temperature-sensor@4c { 175 compatible = "ti,tmp451"; 176 reg = <0x4c>; 177 }; 178 179 eeprom@51 { 180 compatible = "atmel,24c32"; 181 reg = <0x51>; 182 }; 183 184 /* Unsupported devices: 185 * - FXAS21002C Gyroscope at 0x20 186 * - TI ADS7924 4-channel ADC at 0x49 187 */ 188}; 189 190&ifc { 191 status = "disabled"; 192}; 193 194&lpuart0 { 195 status = "okay"; 196}; 197 198&lpuart3 { 199 status = "okay"; 200}; 201 202&mdio0 { 203 /* AR8031 */ 204 sgmii_phy1: ethernet-phy@1 { 205 reg = <0x1>; 206 /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ 207 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; 208 }; 209 210 /* AR8031 */ 211 sgmii_phy2: ethernet-phy@2 { 212 reg = <0x2>; 213 /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ 214 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; 215 }; 216 217 /* BCM5464 quad PHY */ 218 rgmii_phy3: ethernet-phy@3 { 219 reg = <0x3>; 220 }; 221 222 rgmii_phy4: ethernet-phy@4 { 223 reg = <0x4>; 224 }; 225 226 rgmii_phy5: ethernet-phy@5 { 227 reg = <0x5>; 228 }; 229 230 rgmii_phy6: ethernet-phy@6 { 231 reg = <0x6>; 232 }; 233 234 /* SGMII PCS for enet0 */ 235 tbi0: tbi-phy@1f { 236 reg = <0x1f>; 237 device_type = "tbi-phy"; 238 }; 239}; 240 241&mdio1 { 242 /* SGMII PCS for enet1 */ 243 tbi1: tbi-phy@1f { 244 reg = <0x1f>; 245 device_type = "tbi-phy"; 246 }; 247}; 248 249&qspi { 250 status = "okay"; 251 252 flash@0 { 253 /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ 254 compatible = "jedec,spi-nor"; 255 spi-max-frequency = <20000000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 reg = <0>; 259 260 partitions { 261 compatible = "fixed-partitions"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 265 partition@0 { 266 label = "RCW"; 267 reg = <0x0 0x40000>; 268 }; 269 270 partition@40000 { 271 label = "U-Boot"; 272 reg = <0x40000 0x300000>; 273 }; 274 275 partition@340000 { 276 label = "U-Boot Env"; 277 reg = <0x340000 0x100000>; 278 }; 279 }; 280 }; 281}; 282 283&sai2 { 284 status = "okay"; 285}; 286 287&sata { 288 status = "okay"; 289}; 290 291&uart0 { 292 status = "okay"; 293}; 294