1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NXP LPC32xx SoC 4 * 5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com> 6 * Copyright 2012 Roland Stigge <stigge@antcom.de> 7 */ 8 9#include <dt-bindings/clock/lpc32xx-clock.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 compatible = "nxp,lpc3220"; 16 interrupt-parent = <&mic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu@0 { 23 compatible = "arm,arm926ej-s"; 24 device_type = "cpu"; 25 reg = <0x0>; 26 }; 27 }; 28 29 clocks { 30 xtal_32k: xtal_32k { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <32768>; 34 clock-output-names = "xtal_32k"; 35 }; 36 37 xtal: xtal { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <13000000>; 41 clock-output-names = "xtal"; 42 }; 43 }; 44 45 ahb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 compatible = "simple-bus"; 49 ranges = <0x00000000 0x00000000 0x10000000>, 50 <0x20000000 0x20000000 0x30000000>, 51 <0xe0000000 0xe0000000 0x04000000>; 52 53 iram: sram@8000000 { 54 compatible = "mmio-sram"; 55 reg = <0x08000000 0x20000>; 56 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges = <0x00000000 0x08000000 0x20000>; 60 }; 61 62 /* 63 * Enable either SLC or MLC 64 */ 65 slc: flash@20020000 { 66 compatible = "nxp,lpc3220-slc"; 67 reg = <0x20020000 0x1000>; 68 clocks = <&clk LPC32XX_CLK_SLC>; 69 status = "disabled"; 70 }; 71 72 mlc: flash@200a8000 { 73 compatible = "nxp,lpc3220-mlc"; 74 reg = <0x200a8000 0x11000>; 75 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 76 clocks = <&clk LPC32XX_CLK_MLC>; 77 status = "disabled"; 78 }; 79 80 dma: dma-controller@31000000 { 81 compatible = "arm,pl080", "arm,primecell"; 82 reg = <0x31000000 0x1000>; 83 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 84 clocks = <&clk LPC32XX_CLK_DMA>; 85 clock-names = "apb_pclk"; 86 #dma-cells = <2>; 87 }; 88 89 usb { 90 #address-cells = <1>; 91 #size-cells = <1>; 92 compatible = "simple-bus"; 93 ranges = <0x0 0x31020000 0x00001000>; 94 95 /* 96 * Enable either ohci or usbd (gadget)! 97 */ 98 ohci: usb@0 { 99 compatible = "nxp,ohci-nxp", "usb-ohci"; 100 reg = <0x0 0x300>; 101 interrupt-parent = <&sic1>; 102 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&usbclk LPC32XX_USB_CLK_HOST>; 104 status = "disabled"; 105 }; 106 107 usbd: usbd@0 { 108 compatible = "nxp,lpc3220-udc"; 109 reg = <0x0 0x300>; 110 interrupt-parent = <&sic1>; 111 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, 112 <30 IRQ_TYPE_LEVEL_HIGH>, 113 <28 IRQ_TYPE_LEVEL_HIGH>, 114 <26 IRQ_TYPE_LEVEL_LOW>; 115 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; 116 status = "disabled"; 117 }; 118 119 i2cusb: i2c@300 { 120 compatible = "nxp,pnx-i2c"; 121 reg = <0x300 0x100>; 122 interrupt-parent = <&sic1>; 123 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&usbclk LPC32XX_USB_CLK_I2C>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 }; 128 129 usbclk: clock-controller@f00 { 130 compatible = "nxp,lpc3220-usb-clk"; 131 reg = <0xf00 0x100>; 132 #clock-cells = <1>; 133 }; 134 }; 135 136 clcd: clcd@31040000 { 137 compatible = "arm,pl111", "arm,primecell"; 138 reg = <0x31040000 0x1000>; 139 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; 141 clock-names = "clcdclk", "apb_pclk"; 142 status = "disabled"; 143 }; 144 145 mac: ethernet@31060000 { 146 compatible = "nxp,lpc-eth"; 147 reg = <0x31060000 0x1000>; 148 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&clk LPC32XX_CLK_MAC>; 150 status = "disabled"; 151 }; 152 153 emc: memory-controller@31080000 { 154 compatible = "arm,pl175", "arm,primecell"; 155 reg = <0x31080000 0x1000>; 156 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; 157 clock-names = "mpmcclk", "apb_pclk"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 161 ranges = <0 0xe0000000 0x01000000>, 162 <1 0xe1000000 0x01000000>, 163 <2 0xe2000000 0x01000000>, 164 <3 0xe3000000 0x01000000>; 165 status = "disabled"; 166 }; 167 168 apb { 169 #address-cells = <1>; 170 #size-cells = <1>; 171 compatible = "simple-bus"; 172 ranges = <0x20000000 0x20000000 0x30000000>; 173 174 /* 175 * ssp0 and spi1 are shared pins; 176 * enable one in your board dts, as needed. 177 */ 178 ssp0: spi@20084000 { 179 compatible = "arm,pl022", "arm,primecell"; 180 reg = <0x20084000 0x1000>; 181 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&clk LPC32XX_CLK_SSP0>; 183 clock-names = "apb_pclk"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 status = "disabled"; 187 }; 188 189 spi1: spi@20088000 { 190 compatible = "nxp,lpc3220-spi"; 191 reg = <0x20088000 0x1000>; 192 clocks = <&clk LPC32XX_CLK_SPI1>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 status = "disabled"; 196 }; 197 198 /* 199 * ssp1 and spi2 are shared pins; 200 * enable one in your board dts, as needed. 201 */ 202 ssp1: spi@2008c000 { 203 compatible = "arm,pl022", "arm,primecell"; 204 reg = <0x2008c000 0x1000>; 205 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clk LPC32XX_CLK_SSP1>; 207 clock-names = "apb_pclk"; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 spi2: spi@20090000 { 214 compatible = "nxp,lpc3220-spi"; 215 reg = <0x20090000 0x1000>; 216 clocks = <&clk LPC32XX_CLK_SPI2>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 status = "disabled"; 220 }; 221 222 i2s0: i2s@20094000 { 223 compatible = "nxp,lpc3220-i2s"; 224 reg = <0x20094000 0x1000>; 225 status = "disabled"; 226 }; 227 228 sd: mmc@20098000 { 229 compatible = "arm,pl180", "arm,primecell"; 230 reg = <0x20098000 0x1000>; 231 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 232 <13 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clk LPC32XX_CLK_SD>; 234 clock-names = "apb_pclk"; 235 status = "disabled"; 236 }; 237 238 i2s1: i2s@2009c000 { 239 compatible = "nxp,lpc3220-i2s"; 240 reg = <0x2009c000 0x1000>; 241 status = "disabled"; 242 }; 243 244 /* UART5 first since it is the default console, ttyS0 */ 245 uart5: serial@40090000 { 246 /* actually, ns16550a w/ 64 byte fifos! */ 247 compatible = "nxp,lpc3220-uart"; 248 reg = <0x40090000 0x1000>; 249 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 250 reg-shift = <2>; 251 clocks = <&clk LPC32XX_CLK_UART5>; 252 status = "disabled"; 253 }; 254 255 uart3: serial@40080000 { 256 compatible = "nxp,lpc3220-uart"; 257 reg = <0x40080000 0x1000>; 258 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 259 reg-shift = <2>; 260 clocks = <&clk LPC32XX_CLK_UART3>; 261 status = "disabled"; 262 }; 263 264 uart4: serial@40088000 { 265 compatible = "nxp,lpc3220-uart"; 266 reg = <0x40088000 0x1000>; 267 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 268 reg-shift = <2>; 269 clocks = <&clk LPC32XX_CLK_UART4>; 270 status = "disabled"; 271 }; 272 273 uart6: serial@40098000 { 274 compatible = "nxp,lpc3220-uart"; 275 reg = <0x40098000 0x1000>; 276 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 277 reg-shift = <2>; 278 clocks = <&clk LPC32XX_CLK_UART6>; 279 status = "disabled"; 280 }; 281 282 i2c1: i2c@400a0000 { 283 compatible = "nxp,pnx-i2c"; 284 reg = <0x400a0000 0x100>; 285 interrupt-parent = <&sic1>; 286 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&clk LPC32XX_CLK_I2C1>; 290 }; 291 292 i2c2: i2c@400a8000 { 293 compatible = "nxp,pnx-i2c"; 294 reg = <0x400a8000 0x100>; 295 interrupt-parent = <&sic1>; 296 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&clk LPC32XX_CLK_I2C2>; 300 }; 301 302 mpwm: pwm@400e8000 { 303 compatible = "nxp,lpc3220-motor-pwm"; 304 reg = <0x400e8000 0x78>; 305 #pwm-cells = <3>; 306 status = "disabled"; 307 }; 308 }; 309 310 fab { 311 #address-cells = <1>; 312 #size-cells = <1>; 313 compatible = "simple-bus"; 314 ranges = <0x20000000 0x20000000 0x30000000>; 315 316 /* System Control Block */ 317 scb { 318 compatible = "simple-bus"; 319 ranges = <0x0 0x40004000 0x00001000>; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 323 clk: clock-controller@0 { 324 compatible = "nxp,lpc3220-clk"; 325 reg = <0x00 0x114>; 326 #clock-cells = <1>; 327 328 clocks = <&xtal_32k>, <&xtal>; 329 clock-names = "xtal_32k", "xtal"; 330 }; 331 }; 332 333 mic: interrupt-controller@40008000 { 334 compatible = "nxp,lpc3220-mic"; 335 reg = <0x40008000 0x4000>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 sic1: interrupt-controller@4000c000 { 341 compatible = "nxp,lpc3220-sic"; 342 reg = <0x4000c000 0x4000>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 346 interrupt-parent = <&mic>; 347 interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 348 <30 IRQ_TYPE_LEVEL_LOW>; 349 }; 350 351 sic2: interrupt-controller@40010000 { 352 compatible = "nxp,lpc3220-sic"; 353 reg = <0x40010000 0x4000>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 357 interrupt-parent = <&mic>; 358 interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 359 <31 IRQ_TYPE_LEVEL_LOW>; 360 }; 361 362 uart1: serial@40014000 { 363 compatible = "nxp,lpc3220-hsuart"; 364 reg = <0x40014000 0x1000>; 365 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; 366 status = "disabled"; 367 }; 368 369 uart2: serial@40018000 { 370 compatible = "nxp,lpc3220-hsuart"; 371 reg = <0x40018000 0x1000>; 372 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; 373 status = "disabled"; 374 }; 375 376 uart7: serial@4001c000 { 377 compatible = "nxp,lpc3220-hsuart"; 378 reg = <0x4001c000 0x1000>; 379 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 380 status = "disabled"; 381 }; 382 383 rtc: rtc@40024000 { 384 compatible = "nxp,lpc3220-rtc"; 385 reg = <0x40024000 0x1000>; 386 interrupt-parent = <&sic1>; 387 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clk LPC32XX_CLK_RTC>; 389 }; 390 391 gpio: gpio@40028000 { 392 compatible = "nxp,lpc3220-gpio"; 393 reg = <0x40028000 0x1000>; 394 gpio-controller; 395 #gpio-cells = <3>; /* bank, pin, flags */ 396 }; 397 398 timer4: timer@4002c000 { 399 compatible = "nxp,lpc3220-timer"; 400 reg = <0x4002c000 0x1000>; 401 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&clk LPC32XX_CLK_TIMER4>; 403 clock-names = "timerclk"; 404 status = "disabled"; 405 }; 406 407 timer5: timer@40030000 { 408 compatible = "nxp,lpc3220-timer"; 409 reg = <0x40030000 0x1000>; 410 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 411 clocks = <&clk LPC32XX_CLK_TIMER5>; 412 clock-names = "timerclk"; 413 status = "disabled"; 414 }; 415 416 watchdog: watchdog@4003c000 { 417 compatible = "nxp,pnx4008-wdt"; 418 reg = <0x4003c000 0x1000>; 419 clocks = <&clk LPC32XX_CLK_WDOG>; 420 }; 421 422 timer0: timer@40044000 { 423 compatible = "nxp,lpc3220-timer"; 424 reg = <0x40044000 0x1000>; 425 clocks = <&clk LPC32XX_CLK_TIMER0>; 426 clock-names = "timerclk"; 427 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 428 }; 429 430 /* 431 * TSC vs. ADC: Since those two share the same 432 * hardware, you need to choose from one of the 433 * following two and do 'status = "okay";' for one of 434 * them 435 */ 436 437 adc: adc@40048000 { 438 compatible = "nxp,lpc3220-adc"; 439 reg = <0x40048000 0x1000>; 440 interrupt-parent = <&sic1>; 441 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk LPC32XX_CLK_ADC>; 443 status = "disabled"; 444 }; 445 446 tsc: tsc@40048000 { 447 compatible = "nxp,lpc3220-tsc"; 448 reg = <0x40048000 0x1000>; 449 interrupt-parent = <&sic1>; 450 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clk LPC32XX_CLK_ADC>; 452 status = "disabled"; 453 }; 454 455 timer1: timer@4004c000 { 456 compatible = "nxp,lpc3220-timer"; 457 reg = <0x4004c000 0x1000>; 458 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 459 clocks = <&clk LPC32XX_CLK_TIMER1>; 460 clock-names = "timerclk"; 461 }; 462 463 key: key@40050000 { 464 compatible = "nxp,lpc3220-key"; 465 reg = <0x40050000 0x1000>; 466 clocks = <&clk LPC32XX_CLK_KEY>; 467 interrupt-parent = <&sic1>; 468 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 469 status = "disabled"; 470 }; 471 472 timer2: timer@40058000 { 473 compatible = "nxp,lpc3220-timer"; 474 reg = <0x40058000 0x1000>; 475 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 476 clocks = <&clk LPC32XX_CLK_TIMER2>; 477 clock-names = "timerclk"; 478 status = "disabled"; 479 }; 480 481 pwm1: pwm@4005c000 { 482 compatible = "nxp,lpc3220-pwm"; 483 reg = <0x4005c000 0x4>; 484 clocks = <&clk LPC32XX_CLK_PWM1>; 485 #pwm-cells = <3>; 486 assigned-clocks = <&clk LPC32XX_CLK_PWM1>; 487 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 488 status = "disabled"; 489 }; 490 491 pwm2: pwm@4005c004 { 492 compatible = "nxp,lpc3220-pwm"; 493 reg = <0x4005c004 0x4>; 494 clocks = <&clk LPC32XX_CLK_PWM2>; 495 #pwm-cells = <3>; 496 assigned-clocks = <&clk LPC32XX_CLK_PWM2>; 497 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 498 status = "disabled"; 499 }; 500 501 timer3: timer@40060000 { 502 compatible = "nxp,lpc3220-timer"; 503 reg = <0x40060000 0x1000>; 504 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 505 clocks = <&clk LPC32XX_CLK_TIMER3>; 506 clock-names = "timerclk"; 507 status = "disabled"; 508 }; 509 }; 510 }; 511}; 512