xref: /linux/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Embedded Artists LPC3250 board
4 *
5 * Copyright 2012 Roland Stigge <stigge@antcom.de>
6 */
7
8/dts-v1/;
9#include "lpc32xx.dtsi"
10
11/ {
12	model = "Embedded Artists LPC3250 board based on NXP LPC3250";
13	compatible = "ea,ea3250", "nxp,lpc3250";
14
15	memory@80000000 {
16		device_type = "memory";
17		reg = <0x80000000 0x4000000>;
18	};
19
20	gpio-keys {
21		compatible = "gpio-keys";
22		autorepeat;
23
24		button {
25			label = "Interrupt Key";
26			linux,code = <103>;
27			gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
28		};
29
30		key1 {
31			label = "KEY1";
32			linux,code = <1>;
33			gpios = <&pca9532 0 0>;
34		};
35
36		key2 {
37			label = "KEY2";
38			linux,code = <2>;
39			gpios = <&pca9532 1 0>;
40		};
41
42		key3 {
43			label = "KEY3";
44			linux,code = <3>;
45			gpios = <&pca9532 2 0>;
46		};
47
48		key4 {
49			label = "KEY4";
50			linux,code = <4>;
51			gpios = <&pca9532 3 0>;
52		};
53
54		joy0 {
55			label = "Joystick Key 0";
56			linux,code = <10>;
57			gpios = <&gpio 2 0 0>; /* P2.0 */
58		};
59
60		joy1 {
61			label = "Joystick Key 1";
62			linux,code = <11>;
63			gpios = <&gpio 2 1 0>; /* P2.1 */
64		};
65
66		joy2 {
67			label = "Joystick Key 2";
68			linux,code = <12>;
69			gpios = <&gpio 2 2 0>; /* P2.2 */
70		};
71
72		joy3 {
73			label = "Joystick Key 3";
74			linux,code = <13>;
75			gpios = <&gpio 2 3 0>; /* P2.3 */
76		};
77
78		joy4 {
79			label = "Joystick Key 4";
80			linux,code = <14>;
81			gpios = <&gpio 2 4 0>; /* P2.4 */
82		};
83	};
84
85	leds {
86		compatible = "gpio-leds";
87
88		/* LEDs on OEM Board */
89
90		led1 {
91			gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
92			linux,default-trigger = "timer";
93			default-state = "off";
94		};
95
96		led2 {
97			gpios = <&gpio 2 10 1>; /* P2.10, active low */
98			default-state = "off";
99		};
100
101		led3 {
102			gpios = <&gpio 2 11 1>; /* P2.11, active low */
103			default-state = "off";
104		};
105
106		led4 {
107			gpios = <&gpio 2 12 1>; /* P2.12, active low */
108			default-state = "off";
109		};
110
111		/* LEDs on Base Board */
112
113		lede1 {
114			gpios = <&pca9532 8 0>;
115			default-state = "off";
116		};
117		lede2 {
118			gpios = <&pca9532 9 0>;
119			default-state = "off";
120		};
121		lede3 {
122			gpios = <&pca9532 10 0>;
123			default-state = "off";
124		};
125		lede4 {
126			gpios = <&pca9532 11 0>;
127			default-state = "off";
128		};
129		lede5 {
130			gpios = <&pca9532 12 0>;
131			default-state = "off";
132		};
133		lede6 {
134			gpios = <&pca9532 13 0>;
135			default-state = "off";
136		};
137		lede7 {
138			gpios = <&pca9532 14 0>;
139			default-state = "off";
140		};
141		lede8 {
142			gpios = <&pca9532 15 0>;
143			default-state = "off";
144		};
145	};
146};
147
148/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
149&adc {
150	status = "okay";
151};
152
153&i2c1 {
154	clock-frequency = <100000>;
155
156	uda1380: uda1380@18 {
157		compatible = "nxp,uda1380";
158		reg = <0x18>;
159		power-gpio = <&gpio 3 10 0>;
160		reset-gpio = <&gpio 3 2 0>;
161		dac-clk = "wspll";
162	};
163
164	eeprom@50 {
165		compatible = "atmel,24c256";
166		reg = <0x50>;
167	};
168
169	eeprom@57 {
170		compatible = "atmel,24c64";
171		reg = <0x57>;
172	};
173
174	pca9532: pca9532@60 {
175		compatible = "nxp,pca9532";
176		gpio-controller;
177		#gpio-cells = <2>;
178		reg = <0x60>;
179	};
180};
181
182&i2c2 {
183	clock-frequency = <100000>;
184};
185
186&i2cusb {
187	clock-frequency = <100000>;
188
189	isp1301: usb-transceiver@2d {
190		compatible = "nxp,isp1301";
191		reg = <0x2d>;
192	};
193};
194
195&mac {
196	phy-mode = "rmii";
197	use-iram;
198	status = "okay";
199};
200
201/* Here, choose exactly one from: ohci, usbd */
202&ohci /* &usbd */ {
203	transceiver = <&isp1301>;
204	status = "okay";
205};
206
207&sd {
208	wp-gpios = <&pca9532 5 0>;
209	cd-gpios = <&pca9532 4 0>;
210	cd-inverted;
211	bus-width = <4>;
212	status = "okay";
213};
214
215/* 128MB Flash via SLC NAND controller */
216&slc {
217	status = "okay";
218
219	nxp,wdr-clks = <14>;
220	nxp,wwidth = <260000000>;
221	nxp,whold = <104000000>;
222	nxp,wsetup = <200000000>;
223	nxp,rdr-clks = <14>;
224	nxp,rwidth = <34666666>;
225	nxp,rhold = <104000000>;
226	nxp,rsetup = <200000000>;
227	nand-on-flash-bbt;
228	gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
229
230	partitions {
231		compatible = "fixed-partitions";
232		#address-cells = <1>;
233		#size-cells = <1>;
234
235		mtd0@0 {
236			label = "ea3250-boot";
237			reg = <0x00000000 0x00080000>;
238			read-only;
239		};
240
241		mtd1@80000 {
242			label = "ea3250-uboot";
243			reg = <0x00080000 0x000c0000>;
244			read-only;
245		};
246
247		mtd2@140000 {
248			label = "ea3250-kernel";
249			reg = <0x00140000 0x00400000>;
250		};
251
252		mtd3@540000 {
253			label = "ea3250-rootfs";
254			reg = <0x00540000 0x07ac0000>;
255		};
256	};
257};
258
259&uart1 {
260	status = "okay";
261};
262
263&uart3 {
264	status = "okay";
265};
266
267&uart5 {
268	status = "okay";
269};
270
271&uart6 {
272	status = "okay";
273};
274