1/* 2 * Common base for NXP LPC18xx and LPC43xx devices. 3 * 4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com> 5 * 6 * This code is released using a dual license strategy: BSD/GPL 7 * You can choose the licence that better fits your requirements. 8 * 9 * Released under the terms of 3-clause BSD License 10 * Released under the terms of GNU General Public License Version 2.0 11 * 12 */ 13 14#include "../../armv7-m.dtsi" 15 16#include "dt-bindings/clock/lpc18xx-cgu.h" 17#include "dt-bindings/clock/lpc18xx-ccu.h" 18 19#define LPC_PIN(port, pin) (0x##port * 32 + pin) 20#define LPC_GPIO(port, pin) (port * 32 + pin) 21 22/ { 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 compatible = "arm,cortex-m3"; 32 device_type = "cpu"; 33 reg = <0x0>; 34 clocks = <&ccu1 CLK_CPU_CORE>; 35 }; 36 }; 37 38 clocks { 39 xtal: xtal { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <12000000>; 43 }; 44 45 xtal32: xtal32 { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 }; 50 51 enet_rx_clk: enet_rx_clk { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <0>; 55 clock-output-names = "enet_rx_clk"; 56 }; 57 58 enet_tx_clk: enet_tx_clk { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <0>; 62 clock-output-names = "enet_tx_clk"; 63 }; 64 65 gp_clkin: gp_clkin { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <0>; 69 clock-output-names = "gp_clkin"; 70 }; 71 }; 72 73 soc { 74 sct_pwm: pwm@40000000 { 75 compatible = "nxp,lpc1850-sct-pwm"; 76 reg = <0x40000000 0x1000>; 77 clocks = <&ccu1 CLK_CPU_SCT>; 78 clock-names = "pwm"; 79 resets = <&rgu 37>; 80 #pwm-cells = <3>; 81 status = "disabled"; 82 }; 83 84 dmac: dma-controller@40002000 { 85 compatible = "arm,pl080", "arm,primecell"; 86 arm,primecell-periphid = <0x00041080>; 87 reg = <0x40002000 0x1000>; 88 interrupts = <2>; 89 clocks = <&ccu1 CLK_CPU_DMA>; 90 clock-names = "apb_pclk"; 91 resets = <&rgu 19>; 92 #dma-cells = <2>; 93 dma-channels = <8>; 94 dma-requests = <16>; 95 lli-bus-interface-ahb1; 96 lli-bus-interface-ahb2; 97 mem-bus-interface-ahb1; 98 mem-bus-interface-ahb2; 99 memcpy-burst-size = <256>; 100 memcpy-bus-width = <32>; 101 }; 102 103 spifi: spi@40003000 { 104 compatible = "nxp,lpc1773-spifi"; 105 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 106 reg-names = "spifi", "flash"; 107 interrupts = <30>; 108 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 109 clock-names = "spifi", "reg"; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 resets = <&rgu 53>; 113 status = "disabled"; 114 }; 115 116 mmcsd: mmc@40004000 { 117 compatible = "snps,dw-mshc"; 118 reg = <0x40004000 0x1000>; 119 interrupts = <6>; 120 clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>; 121 clock-names = "biu", "ciu"; 122 resets = <&rgu 20>; 123 status = "disabled"; 124 }; 125 126 usb0: usb@40006100 { 127 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 128 reg = <0x40006100 0x100>; 129 interrupts = <8>; 130 clocks = <&ccu1 CLK_CPU_USB0>; 131 resets = <&rgu 17>; 132 phys = <&usb0_otg_phy>; 133 phy-names = "usb"; 134 has-transaction-translator; 135 status = "disabled"; 136 }; 137 138 usb1: usb@40007100 { 139 compatible = "nxp,lpc1850-ehci", "generic-ehci"; 140 reg = <0x40007100 0x100>; 141 interrupts = <9>; 142 clocks = <&ccu1 CLK_CPU_USB1>; 143 resets = <&rgu 18>; 144 status = "disabled"; 145 }; 146 147 emc: memory-controller@40005000 { 148 compatible = "arm,pl172", "arm,primecell"; 149 reg = <0x40005000 0x1000>; 150 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 151 clock-names = "mpmcclk", "apb_pclk"; 152 resets = <&rgu 21>; 153 #address-cells = <2>; 154 #size-cells = <1>; 155 ranges = <0 0 0x1c000000 0x1000000 156 1 0 0x1d000000 0x1000000 157 2 0 0x1e000000 0x1000000 158 3 0 0x1f000000 0x1000000>; 159 status = "disabled"; 160 }; 161 162 lcdc: lcd-controller@40008000 { 163 compatible = "arm,pl111", "arm,primecell"; 164 reg = <0x40008000 0x1000>; 165 interrupts = <7>; 166 interrupt-names = "combined"; 167 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; 168 clock-names = "clcdclk", "apb_pclk"; 169 resets = <&rgu 16>; 170 status = "disabled"; 171 }; 172 173 eeprom: eeprom@4000e000 { 174 compatible = "nxp,lpc1857-eeprom"; 175 reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; 176 reg-names = "reg", "mem"; 177 clocks = <&ccu1 CLK_CPU_EEPROM>; 178 clock-names = "eeprom"; 179 resets = <&rgu 27>; 180 interrupts = <4>; 181 status = "disabled"; 182 }; 183 184 mac: ethernet@40010000 { 185 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 186 reg = <0x40010000 0x2000>; 187 interrupts = <5>; 188 interrupt-names = "macirq"; 189 clocks = <&ccu1 CLK_CPU_ETHERNET>; 190 clock-names = "stmmaceth"; 191 resets = <&rgu 22>; 192 reset-names = "stmmaceth"; 193 rx-fifo-depth = <256>; 194 tx-fifo-depth = <256>; 195 snps,pbl = <4>; /* 32 (8x mode) */ 196 snps,force_thresh_dma_mode; 197 status = "disabled"; 198 }; 199 200 creg: syscon@40043000 { 201 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; 202 reg = <0x40043000 0x1000>; 203 clocks = <&ccu1 CLK_CPU_CREG>; 204 resets = <&rgu 5>; 205 206 creg_clk: clock-controller { 207 compatible = "nxp,lpc1850-creg-clk"; 208 clocks = <&xtal32>; 209 #clock-cells = <1>; 210 }; 211 212 usb0_otg_phy: phy { 213 compatible = "nxp,lpc1850-usb-otg-phy"; 214 clocks = <&ccu1 CLK_USB0>; 215 #phy-cells = <0>; 216 }; 217 218 dmamux: dma-mux { 219 compatible = "nxp,lpc1850-dmamux"; 220 #dma-cells = <3>; 221 dma-requests = <64>; 222 dma-masters = <&dmac>; 223 }; 224 }; 225 226 rtc: rtc@40046000 { 227 compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; 228 reg = <0x40046000 0x1000>; 229 interrupts = <47>; 230 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; 231 clock-names = "rtc", "reg"; 232 }; 233 234 cgu: clock-controller@40050000 { 235 compatible = "nxp,lpc1850-cgu"; 236 reg = <0x40050000 0x1000>; 237 #clock-cells = <1>; 238 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; 239 }; 240 241 ccu1: clock-controller@40051000 { 242 compatible = "nxp,lpc1850-ccu"; 243 reg = <0x40051000 0x1000>; 244 #clock-cells = <1>; 245 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 246 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 247 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 248 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 249 clock-names = "base_apb3_clk", "base_apb1_clk", 250 "base_spifi_clk", "base_cpu_clk", 251 "base_periph_clk", "base_usb0_clk", 252 "base_usb1_clk", "base_spi_clk"; 253 }; 254 255 ccu2: clock-controller@40052000 { 256 compatible = "nxp,lpc1850-ccu"; 257 reg = <0x40052000 0x1000>; 258 #clock-cells = <1>; 259 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 260 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 261 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 262 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; 263 clock-names = "base_audio_clk", "base_uart3_clk", 264 "base_uart2_clk", "base_uart1_clk", 265 "base_uart0_clk", "base_ssp1_clk", 266 "base_ssp0_clk", "base_sdio_clk"; 267 }; 268 269 rgu: reset-controller@40053000 { 270 compatible = "nxp,lpc1850-rgu"; 271 reg = <0x40053000 0x1000>; 272 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 273 clock-names = "delay", "reg"; 274 #reset-cells = <1>; 275 }; 276 277 watchdog@40080000 { 278 compatible = "nxp,lpc1850-wwdt"; 279 reg = <0x40080000 0x24>; 280 interrupts = <49>; 281 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; 282 clock-names = "wdtclk", "reg"; 283 }; 284 285 uart0: serial@40081000 { 286 compatible = "nxp,lpc1850-uart", "ns16550a"; 287 reg = <0x40081000 0x1000>; 288 reg-shift = <2>; 289 interrupts = <24>; 290 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; 291 clock-names = "uartclk", "reg"; 292 resets = <&rgu 44>; 293 dmas = <&dmamux 1 1 2 294 &dmamux 2 1 2 295 &dmamux 11 2 2 296 &dmamux 12 2 2>; 297 dma-names = "tx", "rx", "tx", "rx"; 298 status = "disabled"; 299 }; 300 301 uart1: serial@40082000 { 302 compatible = "nxp,lpc1850-uart", "ns16550a"; 303 reg = <0x40082000 0x1000>; 304 reg-shift = <2>; 305 interrupts = <25>; 306 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; 307 clock-names = "uartclk", "reg"; 308 resets = <&rgu 45>; 309 dmas = <&dmamux 3 1 2 310 &dmamux 4 1 2>; 311 dma-names = "tx", "rx"; 312 status = "disabled"; 313 }; 314 315 ssp0: spi@40083000 { 316 compatible = "arm,pl022", "arm,primecell"; 317 reg = <0x40083000 0x1000>; 318 interrupts = <22>; 319 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; 320 clock-names = "sspclk", "apb_pclk"; 321 resets = <&rgu 50>; 322 dmas = <&dmamux 9 0 2 323 &dmamux 10 0 2>; 324 dma-names = "rx", "tx"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 timer0: timer@40084000 { 331 compatible = "nxp,lpc3220-timer"; 332 reg = <0x40084000 0x1000>; 333 interrupts = <12>; 334 clocks = <&ccu1 CLK_CPU_TIMER0>; 335 clock-names = "timerclk"; 336 resets = <&rgu 32>; 337 }; 338 339 timer1: timer@40085000 { 340 compatible = "nxp,lpc3220-timer"; 341 reg = <0x40085000 0x1000>; 342 interrupts = <13>; 343 clocks = <&ccu1 CLK_CPU_TIMER1>; 344 clock-names = "timerclk"; 345 resets = <&rgu 33>; 346 }; 347 348 pinctrl: pinctrl@40086000 { 349 compatible = "nxp,lpc1850-scu"; 350 reg = <0x40086000 0x1000>; 351 clocks = <&ccu1 CLK_CPU_SCU>; 352 }; 353 354 i2c0: i2c@400a1000 { 355 compatible = "nxp,lpc1788-i2c"; 356 reg = <0x400a1000 0x1000>; 357 interrupts = <18>; 358 clocks = <&ccu1 CLK_APB1_I2C0>; 359 resets = <&rgu 48>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 can1: can@400a4000 { 366 compatible = "bosch,c_can"; 367 reg = <0x400a4000 0x1000>; 368 interrupts = <43>; 369 clocks = <&ccu1 CLK_APB1_CAN1>; 370 resets = <&rgu 54>; 371 status = "disabled"; 372 }; 373 374 uart2: serial@400c1000 { 375 compatible = "nxp,lpc1850-uart", "ns16550a"; 376 reg = <0x400c1000 0x1000>; 377 reg-shift = <2>; 378 interrupts = <26>; 379 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; 380 clock-names = "uartclk", "reg"; 381 resets = <&rgu 46>; 382 dmas = <&dmamux 5 1 2 383 &dmamux 6 1 2>; 384 dma-names = "tx", "rx"; 385 status = "disabled"; 386 }; 387 388 uart3: serial@400c2000 { 389 compatible = "nxp,lpc1850-uart", "ns16550a"; 390 reg = <0x400c2000 0x1000>; 391 reg-shift = <2>; 392 interrupts = <27>; 393 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; 394 clock-names = "uartclk", "reg"; 395 resets = <&rgu 47>; 396 dmas = <&dmamux 7 1 2 397 &dmamux 8 1 2 398 &dmamux 13 3 2 399 &dmamux 14 3 2>; 400 dma-names = "tx", "rx", "rx", "tx"; 401 status = "disabled"; 402 }; 403 404 timer2: timer@400c3000 { 405 compatible = "nxp,lpc3220-timer"; 406 reg = <0x400c3000 0x1000>; 407 interrupts = <14>; 408 clocks = <&ccu1 CLK_CPU_TIMER2>; 409 clock-names = "timerclk"; 410 resets = <&rgu 34>; 411 }; 412 413 timer3: timer@400c4000 { 414 compatible = "nxp,lpc3220-timer"; 415 reg = <0x400c4000 0x1000>; 416 interrupts = <15>; 417 clocks = <&ccu1 CLK_CPU_TIMER3>; 418 clock-names = "timerclk"; 419 resets = <&rgu 35>; 420 }; 421 422 ssp1: spi@400c5000 { 423 compatible = "arm,pl022", "arm,primecell"; 424 reg = <0x400c5000 0x1000>; 425 interrupts = <23>; 426 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; 427 clock-names = "sspclk", "apb_pclk"; 428 resets = <&rgu 51>; 429 dmas = <&dmamux 11 2 2 430 &dmamux 12 2 2 431 &dmamux 3 3 2 432 &dmamux 4 3 2 433 &dmamux 5 2 2 434 &dmamux 6 2 2 435 &dmamux 13 2 2 436 &dmamux 14 2 2>; 437 dma-names = "rx", "tx", "tx", "rx", 438 "tx", "rx", "rx", "tx"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 i2c1: i2c@400e0000 { 445 compatible = "nxp,lpc1788-i2c"; 446 reg = <0x400e0000 0x1000>; 447 interrupts = <19>; 448 clocks = <&ccu1 CLK_APB3_I2C1>; 449 resets = <&rgu 49>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 dac: dac@400e1000 { 456 compatible = "nxp,lpc1850-dac"; 457 reg = <0x400e1000 0x1000>; 458 interrupts = <0>; 459 clocks = <&ccu1 CLK_APB3_DAC>; 460 resets = <&rgu 42>; 461 status = "disabled"; 462 }; 463 464 can0: can@400e2000 { 465 compatible = "bosch,c_can"; 466 reg = <0x400e2000 0x1000>; 467 interrupts = <51>; 468 clocks = <&ccu1 CLK_APB3_CAN0>; 469 resets = <&rgu 55>; 470 status = "disabled"; 471 }; 472 473 adc0: adc@400e3000 { 474 compatible = "nxp,lpc1850-adc"; 475 reg = <0x400e3000 0x1000>; 476 interrupts = <17>; 477 clocks = <&ccu1 CLK_APB3_ADC0>; 478 resets = <&rgu 40>; 479 status = "disabled"; 480 }; 481 482 adc1: adc@400e4000 { 483 compatible = "nxp,lpc1850-adc"; 484 reg = <0x400e4000 0x1000>; 485 interrupts = <21>; 486 clocks = <&ccu1 CLK_APB3_ADC1>; 487 resets = <&rgu 41>; 488 status = "disabled"; 489 }; 490 491 gpio: gpio@400f4000 { 492 compatible = "nxp,lpc1850-gpio"; 493 reg = <0x400f4000 0x4000>; 494 clocks = <&ccu1 CLK_CPU_GPIO>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, 498 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, 499 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, 500 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, 501 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, 502 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, 503 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, 504 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, 505 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, 506 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, 507 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, 508 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, 509 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, 510 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, 511 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, 512 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, 513 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, 514 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, 515 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, 516 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, 517 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, 518 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, 519 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, 520 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, 521 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, 522 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, 523 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, 524 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, 525 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, 526 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, 527 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, 528 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, 529 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, 530 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, 531 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, 532 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, 533 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, 534 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, 535 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, 536 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; 537 }; 538 }; 539}; 540 541&nvic { 542 arm,num-irq-priority-bits = <3>; 543}; 544