1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2018-2022 TQ-Systems GmbH 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5 */ 6 7/ { 8 model = "TQ-Systems MBA6ULx Baseboard"; 9 10 aliases { 11 mmc0 = &usdhc2; 12 mmc1 = &usdhc1; 13 rtc0 = &rtc0; 14 rtc1 = &snvs_rtc; 15 }; 16 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 power-supply = <®_mba6ul_3v3>; 24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; 25 status = "disabled"; 26 }; 27 28 beeper: beeper { 29 compatible = "gpio-beeper"; 30 gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; 31 }; 32 33 gpio_buttons: gpio-keys { 34 compatible = "gpio-keys"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_buttons>; 37 38 button-1 { 39 label = "s14"; 40 linux,code = <KEY_1>; 41 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; 42 wakeup-source; 43 }; 44 45 button-2 { 46 label = "s6"; 47 linux,code = <KEY_2>; 48 gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; 49 wakeup-source; 50 }; 51 52 button-3 { 53 label = "s7"; 54 linux,code = <KEY_3>; 55 gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; 56 wakeup-source; 57 }; 58 59 power-button { 60 label = "POWER"; 61 linux,code = <KEY_POWER>; 62 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 63 wakeup-source; 64 }; 65 }; 66 67 gpio-leds { 68 compatible = "gpio-leds"; 69 status = "okay"; 70 71 led1 { 72 label = "led1"; 73 gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; 74 linux,default-trigger = "default-on"; 75 }; 76 77 led2 { 78 label = "led2"; 79 gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; 80 linux,default-trigger = "heartbeat"; 81 }; 82 }; 83 84 reg_lcd_pwr: regulator-lcd-pwr { 85 compatible = "regulator-fixed"; 86 regulator-name = "lcd-pwr"; 87 gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; 88 enable-active-high; 89 status = "disabled"; 90 }; 91 92 reg_mba6ul_3v3: regulator-mba6ul-3v3 { 93 compatible = "regulator-fixed"; 94 regulator-name = "supply-mba6ul-3v3"; 95 regulator-min-microvolt = <3300000>; 96 regulator-max-microvolt = <3300000>; 97 regulator-always-on; 98 }; 99 100 reg_mba6ul_5v0: regulator-mba6ul-5v0 { 101 compatible = "regulator-fixed"; 102 regulator-name = "supply-mba6ul-5v0"; 103 regulator-min-microvolt = <5000000>; 104 regulator-max-microvolt = <5000000>; 105 regulator-always-on; 106 }; 107 108 reg_mpcie: regulator-mpcie-3v3 { 109 compatible = "regulator-fixed"; 110 regulator-name = "mpcie-3v3"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; 114 enable-active-high; 115 regulator-always-on; 116 startup-delay-us = <500000>; 117 vin-supply = <®_mba6ul_3v3>; 118 }; 119 120 reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { 121 compatible = "regulator-fixed"; 122 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 regulator-name = "otg2-vbus-supply-5v0"; 125 regulator-min-microvolt = <5000000>; 126 regulator-max-microvolt = <5000000>; 127 vin-supply = <®_mpcie>; 128 }; 129 130 reserved-memory { 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges; 134 135 linux,cma { 136 compatible = "shared-dma-pool"; 137 reusable; 138 size = <0x6000000>; 139 linux,cma-default; 140 }; 141 }; 142 143 sound { 144 compatible = "fsl,imx-audio-tlv320aic32x4"; 145 model = "tqm-tlv320aic32"; 146 ssi-controller = <&sai1>; 147 audio-codec = <&tlv320aic32x4>; 148 audio-asrc = <&asrc>; 149 audio-routing = 150 "IN3_L", "Mic Jack", 151 "Mic Jack", "Mic Bias", 152 "IN1_L", "Line In Jack", 153 "IN1_R", "Line In Jack", 154 "Line Out Jack", "LOL", 155 "Line Out Jack", "LOR"; 156 }; 157}; 158 159&can1 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_flexcan1>; 162 xceiver-supply = <®_mba6ul_3v3>; 163 status = "okay"; 164}; 165 166&can2 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_flexcan2>; 169 xceiver-supply = <®_mba6ul_3v3>; 170 status = "okay"; 171}; 172 173&clks { 174 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 175 assigned-clock-rates = <768000000>; 176}; 177 178&ecspi2 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_ecspi2>; 181 num-cs = <1>; 182 status = "okay"; 183}; 184 185&fec1 { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_enet1>; 188 phy-mode = "rmii"; 189 phy-handle = <ðphy0>; 190 phy-supply = <®_mba6ul_3v3>; 191 phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; 192 phy-reset-duration = <25>; 193 phy-reset-post-delay = <1>; 194 status = "okay"; 195}; 196 197&fec2 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; 200 phy-mode = "rmii"; 201 phy-handle = <ðphy1>; 202 phy-supply = <®_mba6ul_3v3>; 203 phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; 204 phy-reset-duration = <25>; 205 phy-reset-post-delay = <1>; 206 status = "okay"; 207 208 mdio { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 ethphy0: ethernet-phy@0 { 213 compatible = "ethernet-phy-ieee802.3-c22"; 214 clocks = <&clks IMX6UL_CLK_ENET_REF>; 215 reg = <0>; 216 max-speed = <100>; 217 }; 218 219 ethphy1: ethernet-phy@1 { 220 compatible = "ethernet-phy-ieee802.3-c22"; 221 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 222 reg = <1>; 223 max-speed = <100>; 224 }; 225 }; 226}; 227 228&i2c4 { 229 tlv320aic32x4: audio-codec@18 { 230 compatible = "ti,tlv320aic32x4"; 231 reg = <0x18>; 232 clocks = <&clks IMX6UL_CLK_SAI1>; 233 clock-names = "mclk"; 234 ldoin-supply = <®_mba6ul_3v3>; 235 iov-supply = <®_mba6ul_3v3>; 236 }; 237 238 jc42: temperature-sensor@19 { 239 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 240 reg = <0x19>; 241 }; 242 243 expander_out0: gpio-expander@20 { 244 compatible = "nxp,pca9554"; 245 reg = <0x20>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 vcc-supply = <®_mba6ul_3v3>; 249 }; 250 251 expander_in0: gpio-expander@21 { 252 compatible = "nxp,pca9554"; 253 reg = <0x21>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_expander_in0>; 256 interrupt-parent = <&gpio4>; 257 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 vcc-supply = <®_mba6ul_3v3>; 263 264 enet1_int-hog { 265 gpio-hog; 266 gpios = <6 0>; 267 input; 268 }; 269 270 enet2_int-hog { 271 gpio-hog; 272 gpios = <7 0>; 273 input; 274 }; 275 }; 276 277 expander_out1: gpio-expander@22 { 278 compatible = "nxp,pca9554"; 279 reg = <0x22>; 280 gpio-controller; 281 #gpio-cells = <2>; 282 vcc-supply = <®_mba6ul_3v3>; 283 }; 284 285 analog_touch: touchscreen@41 { 286 compatible = "st,stmpe811"; 287 reg = <0x41>; 288 interrupts = <21 IRQ_TYPE_EDGE_FALLING>; 289 interrupt-parent = <&gpio4>; 290 status = "disabled"; 291 292 touchscreen { 293 compatible = "st,stmpe-ts"; 294 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ 295 st,ave-ctrl = <3>; /* 8 sample average control */ 296 st,fraction-z = <7>; /* 7 length fractional part in z */ 297 /* 298 * 50 mA typical 80 mA max touchscreen drivers 299 * current limit value 300 */ 301 st,i-drive = <1>; 302 st,mod-12b = <1>; /* 12-bit ADC */ 303 st,ref-sel = <0>; /* internal ADC reference */ 304 st,sample-time = <4>; /* ADC converstion time: 80 clocks */ 305 st,settling = <3>; /* 1 ms panel driver settling time */ 306 st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ 307 }; 308 }; 309 310 /* NXP SE97BTP with temperature sensor + eeprom */ 311 se97b: eeprom@51 { 312 compatible = "nxp,se97b", "atmel,24c02"; 313 reg = <0x51>; 314 pagesize = <16>; 315 vcc-supply = <®_mba6ul_3v3>; 316 }; 317}; 318 319&pwm2 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_pwm2>; 322 status = "okay"; 323}; 324 325&sai1 { 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_sai1>; 328 assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, 329 <&clks IMX6UL_CLK_SAI1>; 330 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 331 assigned-clock-rates = <0>, <24000000>; 332 fsl,sai-mclk-direction-output; 333 status = "okay"; 334}; 335 336&uart1 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_uart1>; 339 status = "okay"; 340}; 341 342&uart3 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_uart3>; 345 status = "okay"; 346}; 347 348&uart6 { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_uart6>; 351 /* for DTE mode, add below change */ 352 /* fsl,dte-mode; */ 353 /* pinctrl-0 = <&pinctrl_uart6dte>; */ 354 uart-has-rtscts; 355 linux,rs485-enabled-at-boot-time; 356 rs485-rts-active-low; 357 rs485-rx-during-tx; 358 status = "okay"; 359}; 360 361/* otg-port */ 362&usbotg1 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_usb_otg1>; 365 power-active-high; 366 over-current-active-low; 367 /* we implement only dual role but not a fully featured OTG */ 368 hnp-disable; 369 srp-disable; 370 adp-disable; 371 dr_mode = "otg"; 372 status = "okay"; 373}; 374 375/* 7-port usb hub */ 376/* id, pwr, oc pins not connected */ 377&usbotg2 { 378 disable-over-current; 379 vbus-supply = <®_otg2vbus_5v0>; 380 dr_mode = "host"; 381 status = "okay"; 382}; 383 384&usdhc1 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_usdhc1>; 387 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 388 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 389 bus-width = <4>; 390 vmmc-supply = <®_mba6ul_3v3>; 391 vqmmc-supply = <®_vccsd>; 392 no-1-8-v; 393 no-mmc; 394 no-sdio; 395 status = "okay"; 396}; 397 398&wdog1 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_wdog1>; 401 fsl,ext-reset-output; 402 status = "okay"; 403}; 404 405&iomuxc { 406 pinctrl_buttons: buttonsgrp { 407 fsl,pins = < 408 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 409 >; 410 }; 411 412 pinctrl_ecspi2: ecspi2grp { 413 fsl,pins = < 414 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 415 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 416 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 417 MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 418 >; 419 }; 420 421 pinctrl_enet1: enet1grp { 422 fsl,pins = < 423 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 424 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 425 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 426 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 427 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 428 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 429 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 430 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 431 >; 432 }; 433 434 pinctrl_enet2: enet2grp { 435 fsl,pins = < 436 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 437 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 438 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 439 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 440 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 441 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 442 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 443 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 444 >; 445 }; 446 447 pinctrl_enet2_mdc: enet2mdcgrp { 448 fsl,pins = < 449 /* mdio */ 450 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 451 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 452 >; 453 }; 454 455 pinctrl_expander_in0: expanderin0grp { 456 fsl,pins = < 457 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 458 >; 459 }; 460 461 pinctrl_flexcan1: flexcan1grp { 462 fsl,pins = < 463 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 464 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 465 >; 466 }; 467 468 pinctrl_flexcan2: flexcan2grp { 469 fsl,pins = < 470 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 471 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 472 >; 473 }; 474 475 pinctrl_pwm2: pwm2grp { 476 fsl,pins = < 477 /* 100 k PD, DSE 120 OHM, SPEED LO */ 478 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 479 >; 480 }; 481 482 pinctrl_sai1: sai1grp { 483 fsl,pins = < 484 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 485 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 486 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 487 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 488 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 489 >; 490 }; 491 492 pinctrl_uart1: uart1grp { 493 fsl,pins = < 494 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 495 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 496 >; 497 }; 498 499 pinctrl_uart3: uart3grp { 500 fsl,pins = < 501 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 502 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 503 >; 504 }; 505 506 pinctrl_uart6: uart6grp { 507 fsl,pins = < 508 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 509 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 510 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 511 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 512 >; 513 }; 514 515 pinctrl_uart6dte: uart6dtegrp { 516 fsl,pins = < 517 MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 518 MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 519 MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 520 MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 521 >; 522 }; 523 524 pinctrl_usb_otg1: usbotg1grp { 525 fsl,pins = < 526 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 527 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 528 MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 529 >; 530 }; 531 532 pinctrl_usdhc1: usdhc1grp { 533 fsl,pins = < 534 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 535 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 536 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 537 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 538 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 539 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 540 /* WP */ 541 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 542 /* CD */ 543 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 544 >; 545 }; 546 547 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 548 fsl,pins = < 549 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 550 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 551 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 552 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 553 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 554 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 555 /* WP */ 556 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 557 /* CD */ 558 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 559 >; 560 }; 561 562 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 563 fsl,pins = < 564 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 565 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 566 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 567 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 568 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 569 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 570 /* WP */ 571 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 572 /* CD */ 573 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 574 >; 575 }; 576 577 pinctrl_wdog1: wdog1grp { 578 fsl,pins = < 579 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 580 >; 581 }; 582}; 583