1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2019 NXP 4 5/dts-v1/; 6 7#include "imx7ulp.dtsi" 8#include <dt-bindings/input/input.h> 9 10/ { 11 model = "Embedded Artists i.MX7ULP COM"; 12 compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; 13 14 chosen { 15 stdout-path = &lpuart4; 16 }; 17 18 memory@60000000 { 19 device_type = "memory"; 20 reg = <0x60000000 0x4000000>; 21 }; 22}; 23 24&lpuart4 { 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_lpuart4>; 27 status = "okay"; 28}; 29 30&usbotg1 { 31 pinctrl-names = "default"; 32 pinctrl-0 = <&pinctrl_usbotg1_id>; 33 srp-disable; 34 hnp-disable; 35 adp-disable; 36 status = "okay"; 37}; 38 39&usdhc0 { 40 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; 41 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_usdhc0>; 44 non-removable; 45 bus-width = <8>; 46 no-1-8-v; 47 status = "okay"; 48}; 49 50&iomuxc1 { 51 pinctrl_lpuart4: lpuart4grp { 52 fsl,pins = < 53 IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 54 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 55 >; 56 }; 57 58 pinctrl_usbotg1_id: otg1idgrp { 59 fsl,pins = < 60 IMX7ULP_PAD_PTC13__USB0_ID 0x10003 61 >; 62 }; 63 64 pinctrl_usdhc0: usdhc0grp { 65 fsl,pins = < 66 IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 67 IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 68 IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 69 IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 70 IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 71 IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 72 IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 73 IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 74 IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 75 IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 76 IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 77 >; 78 }; 79}; 80