1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 #cooling-cells = <2>; 81 nvmem-cells = <&fuse_grade>; 82 nvmem-cell-names = "speed_grade"; 83 }; 84 }; 85 86 cpu0_opp_table: opp-table { 87 compatible = "operating-points-v2"; 88 opp-shared; 89 90 opp-792000000 { 91 opp-hz = /bits/ 64 <792000000>; 92 opp-microvolt = <1000000>; 93 clock-latency-ns = <150000>; 94 opp-supported-hw = <0xf>, <0xf>; 95 }; 96 }; 97 98 ckil: clock-cki { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32768>; 102 clock-output-names = "ckil"; 103 }; 104 105 osc: clock-osc { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <24000000>; 109 clock-output-names = "osc"; 110 }; 111 112 usbphynop1: usbphynop1 { 113 compatible = "usb-nop-xceiv"; 114 clocks = <&clks IMX7D_USB_PHY1_CLK>; 115 clock-names = "main_clk"; 116 #phy-cells = <0>; 117 }; 118 119 usbphynop3: usbphynop3 { 120 compatible = "usb-nop-xceiv"; 121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 122 clock-names = "main_clk"; 123 power-domains = <&pgc_hsic_phy>; 124 #phy-cells = <0>; 125 }; 126 127 pmu { 128 compatible = "arm,cortex-a7-pmu"; 129 interrupt-parent = <&gpc>; 130 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&cpu0>; 132 }; 133 134 replicator { 135 /* 136 * non-configurable replicators don't show up on the 137 * AMBA bus. As such no need to add "arm,primecell" 138 */ 139 compatible = "arm,coresight-static-replicator"; 140 141 out-ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 /* replicator output ports */ 145 port@0 { 146 reg = <0>; 147 replicator_out_port0: endpoint { 148 remote-endpoint = <&tpiu_in_port>; 149 }; 150 }; 151 152 port@1 { 153 reg = <1>; 154 replicator_out_port1: endpoint { 155 remote-endpoint = <&etr_in_port>; 156 }; 157 }; 158 }; 159 160 in-ports { 161 port { 162 replicator_in_port0: endpoint { 163 remote-endpoint = <&etf_out_port>; 164 }; 165 }; 166 }; 167 }; 168 169 timer { 170 compatible = "arm,armv7-timer"; 171 arm,cpu-registers-not-fw-configured; 172 interrupt-parent = <&intc>; 173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 177 }; 178 179 soc: soc { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 compatible = "simple-bus"; 183 interrupt-parent = <&gpc>; 184 ranges; 185 186 ocram: sram@900000 { 187 compatible = "mmio-sram"; 188 reg = <0x00900000 0x20000>; 189 ranges = <0 0x00900000 0x20000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 clocks = <&clks IMX7D_OCRAM_CLK>; 193 }; 194 195 funnel@30041000 { 196 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 197 reg = <0x30041000 0x1000>; 198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 199 clock-names = "apb_pclk"; 200 201 ca_funnel_in_ports: in-ports { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 205 port@0 { 206 reg = <0>; 207 ca_funnel_in_port0: endpoint { 208 remote-endpoint = <&etm0_out_port>; 209 }; 210 }; 211 212 /* the other input ports are not connect to anything */ 213 }; 214 215 out-ports { 216 port { 217 ca_funnel_out_port0: endpoint { 218 remote-endpoint = <&hugo_funnel_in_port0>; 219 }; 220 }; 221 222 }; 223 }; 224 225 etm@3007c000 { 226 compatible = "arm,coresight-etm3x", "arm,primecell"; 227 reg = <0x3007c000 0x1000>; 228 cpu = <&cpu0>; 229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 230 clock-names = "apb_pclk"; 231 232 out-ports { 233 port { 234 etm0_out_port: endpoint { 235 remote-endpoint = <&ca_funnel_in_port0>; 236 }; 237 }; 238 }; 239 }; 240 241 funnel@30083000 { 242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 243 reg = <0x30083000 0x1000>; 244 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 245 clock-names = "apb_pclk"; 246 247 in-ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 port@0 { 252 reg = <0>; 253 hugo_funnel_in_port0: endpoint { 254 remote-endpoint = <&ca_funnel_out_port0>; 255 }; 256 }; 257 258 port@1 { 259 reg = <1>; 260 hugo_funnel_in_port1: endpoint { 261 /* M4 input */ 262 }; 263 }; 264 /* the other input ports are not connect to anything */ 265 }; 266 267 out-ports { 268 port { 269 hugo_funnel_out_port0: endpoint { 270 remote-endpoint = <&etf_in_port>; 271 }; 272 }; 273 }; 274 }; 275 276 etf@30084000 { 277 compatible = "arm,coresight-tmc", "arm,primecell"; 278 reg = <0x30084000 0x1000>; 279 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 280 clock-names = "apb_pclk"; 281 282 in-ports { 283 port { 284 etf_in_port: endpoint { 285 remote-endpoint = <&hugo_funnel_out_port0>; 286 }; 287 }; 288 }; 289 290 out-ports { 291 port { 292 etf_out_port: endpoint { 293 remote-endpoint = <&replicator_in_port0>; 294 }; 295 }; 296 }; 297 }; 298 299 etr@30086000 { 300 compatible = "arm,coresight-tmc", "arm,primecell"; 301 reg = <0x30086000 0x1000>; 302 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 303 clock-names = "apb_pclk"; 304 305 in-ports { 306 port { 307 etr_in_port: endpoint { 308 remote-endpoint = <&replicator_out_port1>; 309 }; 310 }; 311 }; 312 }; 313 314 tpiu@30087000 { 315 compatible = "arm,coresight-tpiu", "arm,primecell"; 316 reg = <0x30087000 0x1000>; 317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 318 clock-names = "apb_pclk"; 319 320 in-ports { 321 port { 322 tpiu_in_port: endpoint { 323 remote-endpoint = <&replicator_out_port0>; 324 }; 325 }; 326 }; 327 }; 328 329 intc: interrupt-controller@31001000 { 330 compatible = "arm,cortex-a7-gic"; 331 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 332 #interrupt-cells = <3>; 333 interrupt-controller; 334 interrupt-parent = <&intc>; 335 reg = <0x31001000 0x1000>, 336 <0x31002000 0x2000>, 337 <0x31004000 0x2000>, 338 <0x31006000 0x2000>; 339 }; 340 341 aips1: bus@30000000 { 342 compatible = "fsl,aips-bus", "simple-bus"; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 reg = <0x30000000 0x400000>; 346 ranges; 347 348 gpio1: gpio@30200000 { 349 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 350 reg = <0x30200000 0x10000>; 351 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 352 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 353 gpio-controller; 354 #gpio-cells = <2>; 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 358 }; 359 360 gpio2: gpio@30210000 { 361 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 362 reg = <0x30210000 0x10000>; 363 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 gpio-ranges = <&iomuxc 0 13 32>; 370 }; 371 372 gpio3: gpio@30220000 { 373 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 374 reg = <0x30220000 0x10000>; 375 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 377 gpio-controller; 378 #gpio-cells = <2>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 gpio-ranges = <&iomuxc 0 45 29>; 382 }; 383 384 gpio4: gpio@30230000 { 385 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 386 reg = <0x30230000 0x10000>; 387 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 gpio-ranges = <&iomuxc 0 74 24>; 394 }; 395 396 gpio5: gpio@30240000 { 397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 398 reg = <0x30240000 0x10000>; 399 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 gpio-ranges = <&iomuxc 0 98 18>; 406 }; 407 408 gpio6: gpio@30250000 { 409 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 410 reg = <0x30250000 0x10000>; 411 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 gpio-ranges = <&iomuxc 0 116 23>; 418 }; 419 420 gpio7: gpio@30260000 { 421 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 422 reg = <0x30260000 0x10000>; 423 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 gpio-ranges = <&iomuxc 0 139 16>; 430 }; 431 432 wdog1: watchdog@30280000 { 433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 434 reg = <0x30280000 0x10000>; 435 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 437 }; 438 439 wdog2: watchdog@30290000 { 440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 441 reg = <0x30290000 0x10000>; 442 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 444 status = "disabled"; 445 }; 446 447 wdog3: watchdog@302a0000 { 448 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 449 reg = <0x302a0000 0x10000>; 450 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 452 status = "disabled"; 453 }; 454 455 wdog4: watchdog@302b0000 { 456 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 457 reg = <0x302b0000 0x10000>; 458 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 460 status = "disabled"; 461 }; 462 463 iomuxc_lpsr: pinctrl@302c0000 { 464 compatible = "fsl,imx7d-iomuxc-lpsr"; 465 reg = <0x302c0000 0x10000>; 466 fsl,input-sel = <&iomuxc>; 467 }; 468 469 gpt1: timer@302d0000 { 470 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 471 reg = <0x302d0000 0x10000>; 472 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 474 <&clks IMX7D_GPT1_ROOT_CLK>; 475 clock-names = "ipg", "per"; 476 }; 477 478 gpt2: timer@302e0000 { 479 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 480 reg = <0x302e0000 0x10000>; 481 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 483 <&clks IMX7D_GPT2_ROOT_CLK>; 484 clock-names = "ipg", "per"; 485 status = "disabled"; 486 }; 487 488 gpt3: timer@302f0000 { 489 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 490 reg = <0x302f0000 0x10000>; 491 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 493 <&clks IMX7D_GPT3_ROOT_CLK>; 494 clock-names = "ipg", "per"; 495 status = "disabled"; 496 }; 497 498 gpt4: timer@30300000 { 499 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 500 reg = <0x30300000 0x10000>; 501 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 503 <&clks IMX7D_GPT4_ROOT_CLK>; 504 clock-names = "ipg", "per"; 505 status = "disabled"; 506 }; 507 508 kpp: keypad@30320000 { 509 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 510 reg = <0x30320000 0x10000>; 511 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 513 status = "disabled"; 514 }; 515 516 iomuxc: pinctrl@30330000 { 517 compatible = "fsl,imx7d-iomuxc"; 518 reg = <0x30330000 0x10000>; 519 }; 520 521 gpr: iomuxc-gpr@30340000 { 522 compatible = "fsl,imx7d-iomuxc-gpr", 523 "fsl,imx6q-iomuxc-gpr", "syscon", 524 "simple-mfd"; 525 reg = <0x30340000 0x10000>; 526 527 mux: mux-controller { 528 compatible = "mmio-mux"; 529 #mux-control-cells = <1>; 530 mux-reg-masks = <0x14 0x00000010>; 531 }; 532 533 video_mux: csi-mux { 534 compatible = "video-mux"; 535 mux-controls = <&mux 0>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 540 port@0 { 541 reg = <0>; 542 }; 543 544 port@1 { 545 reg = <1>; 546 547 csi_mux_from_mipi_vc0: endpoint { 548 remote-endpoint = <&mipi_vc0_to_csi_mux>; 549 }; 550 }; 551 552 port@2 { 553 reg = <2>; 554 555 csi_mux_to_csi: endpoint { 556 remote-endpoint = <&csi_from_csi_mux>; 557 }; 558 }; 559 }; 560 }; 561 562 ocotp: efuse@30350000 { 563 #address-cells = <1>; 564 #size-cells = <1>; 565 compatible = "fsl,imx7d-ocotp", "syscon"; 566 reg = <0x30350000 0x10000>; 567 clocks = <&clks IMX7D_OCOTP_CLK>; 568 569 tempmon_calib: calib@3c { 570 reg = <0x3c 0x4>; 571 }; 572 573 fuse_grade: fuse-grade@10 { 574 reg = <0x10 0x4>; 575 }; 576 }; 577 578 anatop: anatop@30360000 { 579 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 580 "syscon", "simple-mfd"; 581 reg = <0x30360000 0x10000>; 582 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 584 585 reg_1p0d: regulator-vdd1p0d { 586 compatible = "fsl,anatop-regulator"; 587 regulator-name = "vdd1p0d"; 588 regulator-min-microvolt = <800000>; 589 regulator-max-microvolt = <1200000>; 590 anatop-reg-offset = <0x210>; 591 anatop-vol-bit-shift = <8>; 592 anatop-vol-bit-width = <5>; 593 anatop-min-bit-val = <8>; 594 anatop-min-voltage = <800000>; 595 anatop-max-voltage = <1200000>; 596 anatop-enable-bit = <0>; 597 }; 598 599 reg_1p2: regulator-vdd1p2 { 600 compatible = "fsl,anatop-regulator"; 601 regulator-name = "vdd1p2"; 602 regulator-min-microvolt = <1100000>; 603 regulator-max-microvolt = <1300000>; 604 anatop-reg-offset = <0x220>; 605 anatop-vol-bit-shift = <8>; 606 anatop-vol-bit-width = <5>; 607 anatop-min-bit-val = <0x14>; 608 anatop-min-voltage = <1100000>; 609 anatop-max-voltage = <1300000>; 610 anatop-enable-bit = <0>; 611 }; 612 613 tempmon: tempmon { 614 compatible = "fsl,imx7d-tempmon"; 615 interrupt-parent = <&gpc>; 616 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 617 fsl,tempmon = <&anatop>; 618 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 619 nvmem-cell-names = "calib", "temp_grade"; 620 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 621 #thermal-sensor-cells = <0>; 622 }; 623 }; 624 625 snvs: snvs@30370000 { 626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 627 reg = <0x30370000 0x10000>; 628 629 snvs_rtc: snvs-rtc-lp { 630 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 631 regmap = <&snvs>; 632 offset = <0x34>; 633 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&clks IMX7D_SNVS_CLK>; 636 clock-names = "snvs-rtc"; 637 }; 638 639 snvs_pwrkey: snvs-powerkey { 640 compatible = "fsl,sec-v4.0-pwrkey"; 641 regmap = <&snvs>; 642 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&clks IMX7D_SNVS_CLK>; 644 clock-names = "snvs-pwrkey"; 645 linux,keycode = <KEY_POWER>; 646 wakeup-source; 647 status = "disabled"; 648 }; 649 }; 650 651 clks: clock-controller@30380000 { 652 compatible = "fsl,imx7d-ccm"; 653 reg = <0x30380000 0x10000>; 654 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 656 #clock-cells = <1>; 657 clocks = <&ckil>, <&osc>; 658 clock-names = "ckil", "osc"; 659 }; 660 661 src: reset-controller@30390000 { 662 compatible = "fsl,imx7d-src", "syscon"; 663 reg = <0x30390000 0x10000>; 664 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 665 #reset-cells = <1>; 666 }; 667 668 gpc: gpc@303a0000 { 669 compatible = "fsl,imx7d-gpc"; 670 reg = <0x303a0000 0x10000>; 671 interrupt-controller; 672 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 673 #interrupt-cells = <3>; 674 interrupt-parent = <&intc>; 675 676 pgc { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 pgc_mipi_phy: power-domain@0 { 681 #power-domain-cells = <0>; 682 reg = <0>; 683 power-supply = <®_1p0d>; 684 }; 685 686 pgc_pcie_phy: power-domain@1 { 687 #power-domain-cells = <0>; 688 reg = <1>; 689 power-supply = <®_1p0d>; 690 }; 691 692 pgc_hsic_phy: power-domain@2 { 693 #power-domain-cells = <0>; 694 reg = <2>; 695 power-supply = <®_1p2>; 696 }; 697 }; 698 }; 699 }; 700 701 aips2: bus@30400000 { 702 compatible = "fsl,aips-bus", "simple-bus"; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 reg = <0x30400000 0x400000>; 706 ranges; 707 708 adc1: adc@30610000 { 709 compatible = "fsl,imx7d-adc"; 710 reg = <0x30610000 0x10000>; 711 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 713 clock-names = "adc"; 714 #io-channel-cells = <1>; 715 status = "disabled"; 716 }; 717 718 adc2: adc@30620000 { 719 compatible = "fsl,imx7d-adc"; 720 reg = <0x30620000 0x10000>; 721 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 723 clock-names = "adc"; 724 #io-channel-cells = <1>; 725 status = "disabled"; 726 }; 727 728 ecspi4: spi@30630000 { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 732 reg = <0x30630000 0x10000>; 733 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 735 <&clks IMX7D_ECSPI4_ROOT_CLK>; 736 clock-names = "ipg", "per"; 737 dma-names = "rx", "tx"; 738 dmas = <&sdma 6 7 1>, <&sdma 7 7 2>; 739 status = "disabled"; 740 }; 741 742 ftm1: pwm@30640000 { 743 compatible = "fsl,vf610-ftm-pwm"; 744 reg = <0x30640000 0x10000>; 745 #pwm-cells = <3>; 746 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 747 clock-names = "ftm_sys", "ftm_ext", 748 "ftm_fix", "ftm_cnt_clk_en"; 749 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 750 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 751 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 752 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; 753 status = "disabled"; 754 }; 755 756 ftm2: pwm@30650000 { 757 compatible = "fsl,vf610-ftm-pwm"; 758 reg = <0x30650000 0x10000>; 759 #pwm-cells = <3>; 760 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 761 clock-names = "ftm_sys", "ftm_ext", 762 "ftm_fix", "ftm_cnt_clk_en"; 763 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 764 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 765 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 766 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; 767 status = "disabled"; 768 }; 769 770 pwm1: pwm@30660000 { 771 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 772 reg = <0x30660000 0x10000>; 773 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 775 <&clks IMX7D_PWM1_ROOT_CLK>; 776 clock-names = "ipg", "per"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 pwm2: pwm@30670000 { 782 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 783 reg = <0x30670000 0x10000>; 784 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 786 <&clks IMX7D_PWM2_ROOT_CLK>; 787 clock-names = "ipg", "per"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 pwm3: pwm@30680000 { 793 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 794 reg = <0x30680000 0x10000>; 795 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 797 <&clks IMX7D_PWM3_ROOT_CLK>; 798 clock-names = "ipg", "per"; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 803 pwm4: pwm@30690000 { 804 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 805 reg = <0x30690000 0x10000>; 806 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 808 <&clks IMX7D_PWM4_ROOT_CLK>; 809 clock-names = "ipg", "per"; 810 #pwm-cells = <3>; 811 status = "disabled"; 812 }; 813 814 csi: csi@30710000 { 815 compatible = "fsl,imx7-csi"; 816 reg = <0x30710000 0x10000>; 817 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>; 819 clock-names = "mclk"; 820 status = "disabled"; 821 822 port { 823 csi_from_csi_mux: endpoint { 824 remote-endpoint = <&csi_mux_to_csi>; 825 }; 826 }; 827 }; 828 829 lcdif: lcdif@30730000 { 830 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 831 reg = <0x30730000 0x10000>; 832 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 834 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 835 clock-names = "pix", "axi"; 836 status = "disabled"; 837 838 port { 839 #address-cells = <1>; 840 #size-cells = <0>; 841 842 lcdif_out_mipi_dsi: endpoint@0 { 843 reg = <0>; 844 remote-endpoint = <&mipi_dsi_in_lcdif>; 845 }; 846 }; 847 }; 848 849 mipi_csi: mipi-csi@30750000 { 850 compatible = "fsl,imx7-mipi-csi2"; 851 reg = <0x30750000 0x10000>; 852 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 854 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 855 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 856 clock-names = "pclk", "wrap", "phy"; 857 power-domains = <&pgc_mipi_phy>; 858 phy-supply = <®_1p0d>; 859 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 860 status = "disabled"; 861 862 ports { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 866 port@0 { 867 reg = <0>; 868 }; 869 870 port@1 { 871 reg = <1>; 872 873 mipi_vc0_to_csi_mux: endpoint { 874 remote-endpoint = <&csi_mux_from_mipi_vc0>; 875 }; 876 }; 877 }; 878 }; 879 880 mipi_dsi: dsi@30760000 { 881 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 reg = <0x30760000 0x400>; 885 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, 886 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 887 clock-names = "bus_clk", "sclk_mipi"; 888 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>, 889 <&clks IMX7D_PLL_SYS_PFD5_CLK>; 890 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>; 891 assigned-clock-rates = <0>, <333000000>; 892 power-domains = <&pgc_mipi_phy>; 893 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 894 samsung,burst-clock-frequency = <891000000>; 895 samsung,esc-clock-frequency = <20000000>; 896 samsung,pll-clock-frequency = <24000000>; 897 status = "disabled"; 898 899 ports { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 port@0 { 904 reg = <0>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 908 mipi_dsi_in_lcdif: endpoint@0 { 909 reg = <0>; 910 remote-endpoint = <&lcdif_out_mipi_dsi>; 911 }; 912 }; 913 }; 914 }; 915 }; 916 917 aips3: bus@30800000 { 918 compatible = "fsl,aips-bus", "simple-bus"; 919 #address-cells = <1>; 920 #size-cells = <1>; 921 reg = <0x30800000 0x400000>; 922 ranges; 923 924 spba-bus@30800000 { 925 compatible = "fsl,spba-bus", "simple-bus"; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 reg = <0x30800000 0x100000>; 929 ranges; 930 931 ecspi1: spi@30820000 { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 935 reg = <0x30820000 0x10000>; 936 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 938 <&clks IMX7D_ECSPI1_ROOT_CLK>; 939 clock-names = "ipg", "per"; 940 dma-names = "rx", "tx"; 941 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; 942 status = "disabled"; 943 }; 944 945 ecspi2: spi@30830000 { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 949 reg = <0x30830000 0x10000>; 950 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 952 <&clks IMX7D_ECSPI2_ROOT_CLK>; 953 clock-names = "ipg", "per"; 954 dma-names = "rx", "tx"; 955 dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; 956 status = "disabled"; 957 }; 958 959 ecspi3: spi@30840000 { 960 #address-cells = <1>; 961 #size-cells = <0>; 962 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 963 reg = <0x30840000 0x10000>; 964 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 966 <&clks IMX7D_ECSPI3_ROOT_CLK>; 967 clock-names = "ipg", "per"; 968 dma-names = "rx", "tx"; 969 dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; 970 status = "disabled"; 971 }; 972 973 uart1: serial@30860000 { 974 compatible = "fsl,imx7d-uart", 975 "fsl,imx6q-uart"; 976 reg = <0x30860000 0x10000>; 977 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 979 <&clks IMX7D_UART1_ROOT_CLK>; 980 clock-names = "ipg", "per"; 981 status = "disabled"; 982 }; 983 984 uart2: serial@30890000 { 985 compatible = "fsl,imx7d-uart", 986 "fsl,imx6q-uart"; 987 reg = <0x30890000 0x10000>; 988 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 990 <&clks IMX7D_UART2_ROOT_CLK>; 991 clock-names = "ipg", "per"; 992 status = "disabled"; 993 }; 994 995 uart3: serial@30880000 { 996 compatible = "fsl,imx7d-uart", 997 "fsl,imx6q-uart"; 998 reg = <0x30880000 0x10000>; 999 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 1001 <&clks IMX7D_UART3_ROOT_CLK>; 1002 clock-names = "ipg", "per"; 1003 status = "disabled"; 1004 }; 1005 1006 sai1: sai@308a0000 { 1007 #sound-dai-cells = <0>; 1008 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1009 reg = <0x308a0000 0x10000>; 1010 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 1012 <&clks IMX7D_SAI1_ROOT_CLK>, 1013 <&clks IMX7D_CLK_DUMMY>, 1014 <&clks IMX7D_CLK_DUMMY>; 1015 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1016 dma-names = "rx", "tx"; 1017 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 1018 status = "disabled"; 1019 }; 1020 1021 sai2: sai@308b0000 { 1022 #sound-dai-cells = <0>; 1023 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1024 reg = <0x308b0000 0x10000>; 1025 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 1027 <&clks IMX7D_SAI2_ROOT_CLK>, 1028 <&clks IMX7D_CLK_DUMMY>, 1029 <&clks IMX7D_CLK_DUMMY>; 1030 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1031 dma-names = "rx", "tx"; 1032 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 1033 status = "disabled"; 1034 }; 1035 1036 sai3: sai@308c0000 { 1037 #sound-dai-cells = <0>; 1038 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1039 reg = <0x308c0000 0x10000>; 1040 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 1042 <&clks IMX7D_SAI3_ROOT_CLK>, 1043 <&clks IMX7D_CLK_DUMMY>, 1044 <&clks IMX7D_CLK_DUMMY>; 1045 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1046 dma-names = "rx", "tx"; 1047 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 crypto: crypto@30900000 { 1053 compatible = "fsl,sec-v4.0"; 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 reg = <0x30900000 0x40000>; 1057 ranges = <0 0x30900000 0x40000>; 1058 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clks IMX7D_CAAM_CLK>, 1060 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 1061 clock-names = "ipg", "aclk"; 1062 1063 sec_jr0: jr@1000 { 1064 compatible = "fsl,sec-v4.0-job-ring"; 1065 reg = <0x1000 0x1000>; 1066 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1067 }; 1068 1069 sec_jr1: jr@2000 { 1070 compatible = "fsl,sec-v4.0-job-ring"; 1071 reg = <0x2000 0x1000>; 1072 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1073 }; 1074 1075 sec_jr2: jr@3000 { 1076 compatible = "fsl,sec-v4.0-job-ring"; 1077 reg = <0x3000 0x1000>; 1078 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1079 }; 1080 }; 1081 1082 flexcan1: can@30a00000 { 1083 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1084 reg = <0x30a00000 0x10000>; 1085 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clks IMX7D_CLK_DUMMY>, 1087 <&clks IMX7D_CAN1_ROOT_CLK>; 1088 clock-names = "ipg", "per"; 1089 fsl,stop-mode = <&gpr 0x10 1>; 1090 status = "disabled"; 1091 }; 1092 1093 flexcan2: can@30a10000 { 1094 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1095 reg = <0x30a10000 0x10000>; 1096 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&clks IMX7D_CLK_DUMMY>, 1098 <&clks IMX7D_CAN2_ROOT_CLK>; 1099 clock-names = "ipg", "per"; 1100 fsl,stop-mode = <&gpr 0x10 2>; 1101 status = "disabled"; 1102 }; 1103 1104 i2c1: i2c@30a20000 { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1108 reg = <0x30a20000 0x10000>; 1109 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c2: i2c@30a30000 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1118 reg = <0x30a30000 0x10000>; 1119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c3: i2c@30a40000 { 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1128 reg = <0x30a40000 0x10000>; 1129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1131 status = "disabled"; 1132 }; 1133 1134 i2c4: i2c@30a50000 { 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1138 reg = <0x30a50000 0x10000>; 1139 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1141 status = "disabled"; 1142 }; 1143 1144 uart4: serial@30a60000 { 1145 compatible = "fsl,imx7d-uart", 1146 "fsl,imx6q-uart"; 1147 reg = <0x30a60000 0x10000>; 1148 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1150 <&clks IMX7D_UART4_ROOT_CLK>; 1151 clock-names = "ipg", "per"; 1152 status = "disabled"; 1153 }; 1154 1155 uart5: serial@30a70000 { 1156 compatible = "fsl,imx7d-uart", 1157 "fsl,imx6q-uart"; 1158 reg = <0x30a70000 0x10000>; 1159 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1161 <&clks IMX7D_UART5_ROOT_CLK>; 1162 clock-names = "ipg", "per"; 1163 status = "disabled"; 1164 }; 1165 1166 uart6: serial@30a80000 { 1167 compatible = "fsl,imx7d-uart", 1168 "fsl,imx6q-uart"; 1169 reg = <0x30a80000 0x10000>; 1170 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1172 <&clks IMX7D_UART6_ROOT_CLK>; 1173 clock-names = "ipg", "per"; 1174 status = "disabled"; 1175 }; 1176 1177 uart7: serial@30a90000 { 1178 compatible = "fsl,imx7d-uart", 1179 "fsl,imx6q-uart"; 1180 reg = <0x30a90000 0x10000>; 1181 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1183 <&clks IMX7D_UART7_ROOT_CLK>; 1184 clock-names = "ipg", "per"; 1185 status = "disabled"; 1186 }; 1187 1188 mu0a: mailbox@30aa0000 { 1189 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1190 reg = <0x30aa0000 0x10000>; 1191 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1193 #mbox-cells = <2>; 1194 status = "disabled"; 1195 }; 1196 1197 mu0b: mailbox@30ab0000 { 1198 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1199 reg = <0x30ab0000 0x10000>; 1200 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1202 #mbox-cells = <2>; 1203 fsl,mu-side-b; 1204 status = "disabled"; 1205 }; 1206 1207 usbotg1: usb@30b10000 { 1208 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1209 reg = <0x30b10000 0x200>; 1210 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1212 fsl,usbphy = <&usbphynop1>; 1213 fsl,usbmisc = <&usbmisc1 0>; 1214 phy-clkgate-delay-us = <400>; 1215 status = "disabled"; 1216 }; 1217 1218 usbh: usb@30b30000 { 1219 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1220 reg = <0x30b30000 0x200>; 1221 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1223 fsl,usbphy = <&usbphynop3>; 1224 fsl,usbmisc = <&usbmisc3 0>; 1225 phy_type = "hsic"; 1226 dr_mode = "host"; 1227 phy-clkgate-delay-us = <400>; 1228 status = "disabled"; 1229 }; 1230 1231 usbmisc1: usbmisc@30b10200 { 1232 #index-cells = <1>; 1233 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1234 reg = <0x30b10200 0x200>; 1235 }; 1236 1237 usbmisc3: usbmisc@30b30200 { 1238 #index-cells = <1>; 1239 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1240 reg = <0x30b30200 0x200>; 1241 }; 1242 1243 usdhc1: mmc@30b40000 { 1244 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1245 reg = <0x30b40000 0x10000>; 1246 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1248 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1249 <&clks IMX7D_USDHC1_ROOT_CLK>; 1250 clock-names = "ipg", "ahb", "per"; 1251 bus-width = <4>; 1252 fsl,tuning-step = <2>; 1253 fsl,tuning-start-tap = <20>; 1254 status = "disabled"; 1255 }; 1256 1257 usdhc2: mmc@30b50000 { 1258 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1259 reg = <0x30b50000 0x10000>; 1260 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1262 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1263 <&clks IMX7D_USDHC2_ROOT_CLK>; 1264 clock-names = "ipg", "ahb", "per"; 1265 bus-width = <4>; 1266 fsl,tuning-step = <2>; 1267 fsl,tuning-start-tap = <20>; 1268 status = "disabled"; 1269 }; 1270 1271 usdhc3: mmc@30b60000 { 1272 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1273 reg = <0x30b60000 0x10000>; 1274 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1276 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1277 <&clks IMX7D_USDHC3_ROOT_CLK>; 1278 clock-names = "ipg", "ahb", "per"; 1279 bus-width = <4>; 1280 fsl,tuning-step = <2>; 1281 fsl,tuning-start-tap = <20>; 1282 status = "disabled"; 1283 }; 1284 1285 qspi: spi@30bb0000 { 1286 compatible = "fsl,imx7d-qspi"; 1287 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1288 reg-names = "QuadSPI", "QuadSPI-memory"; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1293 <&clks IMX7D_QSPI_ROOT_CLK>; 1294 clock-names = "qspi_en", "qspi"; 1295 status = "disabled"; 1296 }; 1297 1298 sdma: dma-controller@30bd0000 { 1299 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1300 reg = <0x30bd0000 0x10000>; 1301 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1303 <&clks IMX7D_SDMA_CORE_CLK>; 1304 clock-names = "ipg", "ahb"; 1305 #dma-cells = <3>; 1306 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1307 }; 1308 1309 fec1: ethernet@30be0000 { 1310 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1311 reg = <0x30be0000 0x10000>; 1312 interrupt-names = "int0", "int1", "int2", "pps"; 1313 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1318 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1319 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1320 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1321 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1322 clock-names = "ipg", "ahb", "ptp", 1323 "enet_clk_ref", "enet_out"; 1324 fsl,num-tx-queues = <3>; 1325 fsl,num-rx-queues = <3>; 1326 fsl,stop-mode = <&gpr 0x10 3>; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 dma_apbh: dma-controller@33000000 { 1332 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1333 reg = <0x33000000 0x2000>; 1334 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1338 #dma-cells = <1>; 1339 dma-channels = <4>; 1340 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1341 }; 1342 1343 gpmi: nand-controller@33002000 { 1344 compatible = "fsl,imx7d-gpmi-nand"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1348 reg-names = "gpmi-nand", "bch"; 1349 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1350 interrupt-names = "bch"; 1351 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1352 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1353 clock-names = "gpmi_io", "gpmi_bch_apb"; 1354 dmas = <&dma_apbh 0>; 1355 dma-names = "rx-tx"; 1356 status = "disabled"; 1357 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1358 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1359 }; 1360 }; 1361}; 1362