xref: /linux/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts (revision 71dfa617ea9f18e4585fe78364217cd32b1fc382) 
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 */
9
10/dts-v1/;
11
12#include "imx7d-tqma7.dtsi"
13#include "imx7-mba7.dtsi"
14
15/ {
16	model = "TQ-Systems TQMa7D board on MBa7 carrier board";
17	compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
18};
19
20&fec2 {
21	pinctrl-names = "default";
22	pinctrl-0 = <&pinctrl_enet2>;
23	phy-mode = "rgmii-id";
24	phy-supply = <&reg_fec2_pwdn>;
25	phy-handle = <&ethphy2_0>;
26	fsl,magic-packet;
27	status = "okay";
28
29	mdio {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		ethphy2_0: ethernet-phy@0 {
34			compatible = "ethernet-phy-ieee802.3-c22";
35			reg = <0>;
36			pinctrl-names = "default";
37			pinctrl-0 = <&pinctrl_enet2_phy>;
38			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
39			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
40			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
41			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
42			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
43			reset-assert-us = <1000>;
44			reset-deassert-us = <500>;
45		};
46	};
47};
48
49&gpio2 {
50	pcie-dis-hog {
51		gpio-hog;
52		gpios = <29 GPIO_ACTIVE_HIGH>;
53		output-high;
54		line-name = "pcie-dis";
55	};
56
57	pcie-rst-hog {
58		gpio-hog;
59		gpios = <12 GPIO_ACTIVE_HIGH>;
60		output-high;
61		line-name = "pcie-rst";
62	};
63};
64
65&iomuxc {
66	pinctrl-names = "default";
67	pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>;
68
69	pinctrl_enet2: enet2grp {
70		fsl,pins =
71			<MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x02>,
72			<MX7D_PAD_SD2_WP__ENET2_MDC			0x00>,
73			<MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x71>,
74			<MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x71>,
75			<MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x71>,
76			<MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x71>,
77			<MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x71>,
78			<MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x71>,
79			<MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x79>,
80			<MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x79>,
81			<MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79>,
82			<MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79>,
83			<MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79>,
84			<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x79>;
85	};
86
87	pinctrl_enet2_phy: enet2phygrp {
88		fsl,pins =
89			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
90			<MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070>,
91			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
92			<MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x40000078>;
93	};
94
95	pinctrl_hog_pcie: hogpciegrp {
96		fsl,pins =
97			/* #pcie_rst */
98			<MX7D_PAD_SD2_CLK__GPIO5_IO12			0x70>,
99			/* #pcie_dis */
100			<MX7D_PAD_EPDC_BDR1__GPIO2_IO29			0x70>;
101	};
102
103	pinctrl_pcie: pciegrp {
104		fsl,pins =
105			/* #pcie_wake */
106			<MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30		0x70>;
107	};
108};
109
110&iomuxc_lpsr {
111	pinctrl_usbotg2: usbotg2grp {
112		fsl,pins =
113			<MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC	0x5c>,
114			<MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x59>;
115	};
116};
117
118&pcie {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_pcie>;
121	/* 1.5V logically from 3.3V */
122	/* probe deferral not supported */
123	/* pcie-bus-supply = <&reg_mpcie_1v5>; */
124	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
125	status = "disabled";
126};
127
128&usbotg2 {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_usbotg2>;
131	vbus-supply = <&reg_usb_otg2_vbus>;
132	disable-over-current;
133	dr_mode = "host";
134	status = "okay";
135};
136