1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Device Tree Include file for TQ-Systems MBa7 carrier board. 4 * 5 * Copyright (C) 2016 TQ-Systems GmbH 6 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com> 8 * 9 * Note: This file does not include nodes for all peripheral devices. 10 * As device driver coverage increases additional nodes can be added. 11 */ 12 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/net/ti-dp83867.h> 15 16/ { 17 aliases { 18 mmc0 = &usdhc3; 19 mmc1 = &usdhc1; 20 /delete-property/ mmc2; 21 rtc0 = &ds1339; 22 rtc1 = &snvs_rtc; 23 }; 24 25 beeper { 26 compatible = "gpio-beeper"; 27 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; 28 }; 29 30 chosen { 31 stdout-path = &uart6; 32 }; 33 34 gpio_buttons: gpio-keys { 35 compatible = "gpio-keys"; 36 37 /* 38 * NOTE: These buttons are attached to a GPIO-expander. 39 * Enabling wakeup-source, enables wakeup on all inputs. 40 * If PE_GPIO[3..6] are used as inputs, they cause a 41 * wakeup as well. 42 */ 43 button-0 { 44 /* #SWITCH_A */ 45 label = "S11"; 46 linux,code = <KEY_1>; 47 gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; 48 wakeup-source; 49 }; 50 51 button-1 { 52 /* #SWITCH_B */ 53 label = "S12"; 54 linux,code = <KEY_2>; 55 gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; 56 wakeup-source; 57 }; 58 59 button-2 { 60 /* #SWITCH_C */ 61 label = "S13"; 62 linux,code = <KEY_3>; 63 gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; 64 wakeup-source; 65 }; 66 }; 67 68 gpio-leds { 69 compatible = "gpio-leds"; 70 71 led1 { 72 label = "led1"; 73 gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; 74 linux,default-trigger = "default-on"; 75 }; 76 77 led2 { 78 label = "led2"; 79 gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; 80 linux,default-trigger = "heartbeat"; 81 }; 82 }; 83 84 iio-hwmon { 85 compatible = "iio-hwmon"; 86 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, 87 <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>; 88 }; 89 90 reg_sd1_vmmc: regulator-sd1-vmmc { 91 compatible = "regulator-fixed"; 92 regulator-name = "VCC3V3_SD1"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 regulator-always-on; 96 }; 97 98 reg_fec1_pwdn: regulator-fec1-pwdn { 99 compatible = "regulator-fixed"; 100 regulator-name = "PWDN_FEC1"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-always-on; 104 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 105 enable-active-high; 106 }; 107 108 reg_fec2_pwdn: regulator-fec2-pwdn { 109 compatible = "regulator-fixed"; 110 regulator-name = "PWDN_FEC2"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 regulator-always-on; 114 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117 118 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 119 compatible = "regulator-fixed"; 120 regulator-name = "VBUS_USBOTG1"; 121 regulator-min-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>; 123 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 124 enable-active-high; 125 }; 126 127 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 128 compatible = "regulator-fixed"; 129 regulator-name = "VBUS_USBOTG2"; 130 regulator-min-microvolt = <5000000>; 131 regulator-max-microvolt = <5000000>; 132 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 133 enable-active-high; 134 }; 135 136 reg_mpcie_1v5: regulator-mpcie-1v5 { 137 compatible = "regulator-fixed"; 138 regulator-name = "VCC1V5_MPCIE"; 139 regulator-min-microvolt = <1500000>; 140 regulator-max-microvolt = <1500000>; 141 gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; 142 enable-active-high; 143 regulator-always-on; 144 }; 145 146 reg_mpcie_3v3: regulator-mpcie-3v3 { 147 compatible = "regulator-fixed"; 148 regulator-name = "VCC3V3_MPCIE"; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 regulator-always-on; 154 }; 155 156 reg_mba_12v0: regulator-mba-12v0 { 157 compatible = "regulator-fixed"; 158 regulator-name = "VCC12V0_MBA7"; 159 regulator-min-microvolt = <12000000>; 160 regulator-max-microvolt = <12000000>; 161 gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; 162 enable-active-high; 163 }; 164 165 reg_lvds_transmitter: regulator-lvds-transmitter { 166 compatible = "regulator-fixed"; 167 regulator-name = "#SHTDN_LVDS"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; 171 enable-active-high; 172 }; 173 174 reg_vref_1v8: regulator-vref-1v8 { 175 compatible = "regulator-fixed"; 176 regulator-name = "VCC1V8_REF"; 177 regulator-min-microvolt = <1800000>; 178 regulator-max-microvolt = <1800000>; 179 regulator-always-on; 180 vin-supply = <&sw2_reg>; 181 }; 182 183 reg_audio_3v3: regulator-audio-3v3 { 184 compatible = "regulator-fixed"; 185 regulator-name = "VCC3V3_AUDIO"; 186 regulator-min-microvolt = <3300000>; 187 regulator-max-microvolt = <3300000>; 188 regulator-always-on; 189 }; 190 191 reg_vcc_3v3: regulator-vcc-3v3 { 192 compatible = "regulator-fixed"; 193 regulator-name = "VCC3V3"; 194 regulator-min-microvolt = <3300000>; 195 regulator-max-microvolt = <3300000>; 196 regulator-always-on; 197 }; 198 199 sound { 200 compatible = "fsl,imx-audio-tlv320aic32x4"; 201 model = "imx-audio-tlv320aic32x4"; 202 ssi-controller = <&sai1>; 203 audio-codec = <&tlv320aic32x4>; 204 audio-routing = 205 "IN3_L", "Mic Jack", 206 "Mic Jack", "Mic Bias", 207 "IN1_L", "Line In Jack", 208 "IN1_R", "Line In Jack", 209 "Line Out Jack", "LOL", 210 "Line Out Jack", "LOR"; 211 }; 212}; 213 214&adc1 { 215 vref-supply = <®_vref_1v8>; 216 status = "okay"; 217}; 218 219&adc2 { 220 vref-supply = <®_vref_1v8>; 221 status = "okay"; 222}; 223 224&ecspi1 { 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>; 227 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, 228 <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; 229 status = "okay"; 230}; 231 232&ecspi2 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_ecspi2>; 235 status = "okay"; 236}; 237 238&fec1 { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_enet1>; 241 phy-mode = "rgmii-id"; 242 phy-supply = <®_fec1_pwdn>; 243 phy-handle = <ðphy1_0>; 244 fsl,magic-packet; 245 status = "okay"; 246 247 mdio { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 ethphy1_0: ethernet-phy@0 { 252 compatible = "ethernet-phy-ieee802.3-c22"; 253 reg = <0>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_enet1_phy>; 256 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 257 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 258 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 259 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 260 reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; 261 reset-assert-us = <1000>; 262 reset-deassert-us = <500>; 263 }; 264 }; 265}; 266 267&flash0 { 268 partitions { 269 compatible = "fixed-partitions"; 270 #address-cells = <1>; 271 #size-cells = <1>; 272 273 uboot@0 { 274 label = "U-Boot"; 275 reg = <0x0 0xd0000>; 276 }; 277 278 env1@d0000 { 279 label = "ENV1"; 280 reg = <0xd0000 0x10000>; 281 }; 282 283 env2@e0000 { 284 label = "ENV2"; 285 reg = <0xe0000 0x10000>; 286 }; 287 288 dtb@f0000 { 289 label = "DTB"; 290 reg = <0xf0000 0x10000>; 291 }; 292 293 linux@100000 { 294 label = "Linux"; 295 reg = <0x100000 0x700000>; 296 }; 297 298 rootfs@800000 { 299 label = "RootFS"; 300 reg = <0x800000 0x3800000>; 301 }; 302 }; 303}; 304 305&flexcan1 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_flexcan1>; 308 status = "okay"; 309}; 310 311&flexcan2 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_flexcan2>; 314 status = "okay"; 315}; 316 317&i2c1 { 318 lm75: temperature-sensor@49 { 319 compatible = "national,lm75a"; 320 reg = <0x49>; 321 vs-supply = <®_vcc_3v3>; 322 }; 323}; 324 325&i2c2 { 326 clock-frequency = <100000>; 327 pinctrl-names = "default", "gpio"; 328 pinctrl-0 = <&pinctrl_i2c2>; 329 pinctrl-1 = <&pinctrl_i2c2_recovery>; 330 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 331 sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 332 status = "okay"; 333 334 tlv320aic32x4: audio-codec@18 { 335 compatible = "ti,tlv320aic32x4"; 336 reg = <0x18>; 337 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 338 clock-names = "mclk"; 339 ldoin-supply = <®_audio_3v3>; 340 iov-supply = <®_audio_3v3>; 341 }; 342 343 pca9555: gpio-expander@20 { 344 compatible = "nxp,pca9555"; 345 reg = <0x20>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_pca9555>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-parent = <&gpio7>; 351 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 vcc-supply = <®_vcc_3v3>; 355 }; 356}; 357 358&i2c3 { 359 clock-frequency = <100000>; 360 pinctrl-names = "default", "gpio"; 361 pinctrl-0 = <&pinctrl_i2c3>; 362 pinctrl-1 = <&pinctrl_i2c3_recovery>; 363 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 364 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 365 status = "okay"; 366}; 367 368&iomuxc { 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_hog_mba7_1>; 371 372 pinctrl_ecspi1: ecspi1grp { 373 fsl,pins = 374 <MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>, 375 <MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>, 376 <MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>, 377 <MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>, 378 <MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>, 379 <MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>; 380 }; 381 382 pinctrl_ecspi1_ss0: ecspi1ss0grp { 383 fsl,pins = < 384 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74 385 >; 386 }; 387 388 pinctrl_ecspi2: ecspi2grp { 389 fsl,pins = 390 <MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>, 391 <MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>, 392 <MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>, 393 <MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>; 394 }; 395 396 pinctrl_enet1: enet1grp { 397 fsl,pins = 398 <MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>, 399 <MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>, 400 <MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>, 401 <MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>, 402 <MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>, 403 <MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>, 404 <MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>, 405 <MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>, 406 <MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>, 407 <MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>, 408 <MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>, 409 <MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>, 410 <MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>, 411 <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>; 412 }; 413 414 pinctrl_enet1_phy: enet1phygrp { 415 fsl,pins = 416 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ 417 <MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>, 418 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ 419 <MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>; 420 }; 421 422 pinctrl_flexcan1: flexcan1grp { 423 fsl,pins = 424 <MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>, 425 <MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>; 426 }; 427 428 pinctrl_flexcan2: flexcan2grp { 429 fsl,pins = 430 <MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>, 431 <MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>; 432 }; 433 434 pinctrl_hog_mba7_1: hogmba71grp { 435 fsl,pins = 436 /* Limitation: WDOG2_B / WDOG2_RESET not usable */ 437 <MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>, 438 <MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>, 439 /* #BOOT_EN */ 440 <MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>; 441 }; 442 443 pinctrl_i2c2: i2c2grp { 444 fsl,pins = 445 <MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>, 446 <MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>; 447 }; 448 449 pinctrl_i2c2_recovery: i2c2recoverygrp { 450 fsl,pins = 451 <MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>, 452 <MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>; 453 }; 454 455 pinctrl_i2c3: i2c3grp { 456 fsl,pins = 457 <MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>, 458 <MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>; 459 }; 460 461 pinctrl_i2c3_recovery: i2c3recoverygrp { 462 fsl,pins = 463 <MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>, 464 <MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>; 465 }; 466 467 pinctrl_pca9555: pca95550grp { 468 fsl,pins = 469 <MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>; 470 }; 471 472 pinctrl_sai1: sai1grp { 473 fsl,pins = 474 <MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>, 475 <MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>, 476 <MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>, 477 <MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>, 478 479 <MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>, 480 <MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>, 481 <MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>; 482 }; 483 484 pinctrl_uart3: uart3grp { 485 fsl,pins = 486 <MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>, 487 <MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>, 488 <MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>, 489 <MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>; 490 }; 491 492 pinctrl_uart4: uart4grp { 493 fsl,pins = 494 <MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>, 495 <MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>, 496 <MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>, 497 <MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>; 498 }; 499 500 pinctrl_uart5: uart5grp { 501 fsl,pins = 502 <MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>, 503 <MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>; 504 }; 505 506 pinctrl_uart6: uart6grp { 507 fsl,pins = 508 <MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>, 509 <MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>, 510 <MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>, 511 <MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>; 512 }; 513 514 pinctrl_uart7: uart7grp { 515 fsl,pins = 516 <MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>, 517 <MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>, 518 <MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>, 519 /* Limitation: RTS is not connected */ 520 <MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>; 521 }; 522 523 pinctrl_usdhc1_gpio: usdhc1_gpiogrp { 524 fsl,pins = 525 /* WP */ 526 <MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>, 527 /* CD */ 528 <MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>, 529 /* VSELECT */ 530 <MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>; 531 }; 532 533 pinctrl_usdhc1: usdhc1grp { 534 fsl,pins = 535 <MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>, 536 <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, 537 <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>, 538 <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>, 539 <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>, 540 <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>; 541 }; 542 543 pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp { 544 fsl,pins = 545 <MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>, 546 <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, 547 <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>, 548 <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>, 549 <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>, 550 <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>; 551 }; 552 553 pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp { 554 fsl,pins = 555 <MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>, 556 <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, 557 <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>, 558 <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>, 559 <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>, 560 <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>; 561 }; 562}; 563 564&iomuxc_lpsr { 565 pinctrl_pwm1: pwm1grp { 566 fsl,pins = 567 /* LCD_CONTRAST */ 568 <MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>; 569 }; 570 571 pinctrl_usbotg1: usbotg1grp { 572 fsl,pins = 573 <MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>, 574 <MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>; 575 }; 576 577 pinctrl_wdog1: wdog1grp { 578 fsl,pins = 579 <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>; 580 }; 581}; 582 583&pwm1 { 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_pwm1>; 586 status = "okay"; 587}; 588 589&sai1 { 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pinctrl_sai1>; 592 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 593 <&clks IMX7D_SAI1_ROOT_CLK>; 594 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 595 assigned-clock-rates = <0>, <36864000>; 596 status = "okay"; 597}; 598 599&snvs_pwrkey { 600 status = "okay"; 601}; 602 603&uart3 { 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_uart3>; 606 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 607 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 608 status = "okay"; 609}; 610 611&uart4 { 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_uart4>; 614 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; 615 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 616 status = "okay"; 617}; 618 619&uart5 { 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pinctrl_uart5>; 622 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; 623 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 624 status = "okay"; 625}; 626 627&uart6 { 628 pinctrl-names = "default"; 629 pinctrl-0 = <&pinctrl_uart6>; 630 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 631 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 632 status = "okay"; 633}; 634 635&uart7 { 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_uart7>; 638 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; 639 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 640 uart-has-rtscts; 641 linux,rs485-enabled-at-boot-time; 642 rs485-rts-active-low; 643 rs485-rx-during-tx; 644 status = "okay"; 645}; 646 647&usbh { 648 disable-over-current; 649 status = "okay"; 650}; 651 652&usbotg1 { 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_usbotg1>; 655 vbus-supply = <®_usb_otg1_vbus>; 656 srp-disable; 657 hnp-disable; 658 adp-disable; 659 over-current-active-low; 660 dr_mode = "otg"; 661 status = "okay"; 662}; 663 664&usdhc1 { 665 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 666 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 667 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 668 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 669 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 670 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 671 vmmc-supply = <®_sd1_vmmc>; 672 bus-width = <4>; 673 no-1-8-v; 674 no-sdio; 675 no-mmc; 676 status = "okay"; 677}; 678 679&wdog1 { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_wdog1>; 682 fsl,ext-reset-output; 683}; 684