xref: /linux/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi (revision b228ab57e51b62663a80ca820c87ba2650583f08) 
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8 *
9 * Note: This file does not include nodes for all peripheral devices.
10 * As device driver coverage increases additional nodes can be added.
11 */
12
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/net/ti-dp83867.h>
15
16/ {
17	aliases {
18		mmc0 = &usdhc3;
19		mmc1 = &usdhc1;
20		/delete-property/ mmc2;
21		rtc0 = &ds1339;
22		rtc1 = &snvs_rtc;
23	};
24
25	beeper {
26		compatible = "gpio-beeper";
27		gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
28	};
29
30	chosen {
31		stdout-path = &uart6;
32	};
33
34	gpio_buttons: gpio-keys {
35		compatible = "gpio-keys";
36
37		/*
38		 * NOTE: These buttons are attached to a GPIO-expander.
39		 * Enabling wakeup-source, enables wakeup on all inputs.
40		 * If PE_GPIO[3..6] are used as inputs, they cause a
41		 * wakeup as well.
42		 */
43		button-0 {
44			/* #SWITCH_A */
45			label = "S11";
46			linux,code = <KEY_1>;
47			gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
48			wakeup-source;
49		};
50
51		button-1 {
52			/* #SWITCH_B */
53			label = "S12";
54			linux,code = <KEY_2>;
55			gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
56			wakeup-source;
57		};
58
59		button-2 {
60			/* #SWITCH_C */
61			label = "S13";
62			linux,code = <KEY_3>;
63			gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
64			wakeup-source;
65		};
66	};
67
68	gpio-leds {
69		compatible = "gpio-leds";
70
71		led1 {
72			label = "led1";
73			gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
74			linux,default-trigger = "default-on";
75		};
76
77		led2 {
78			label = "led2";
79			gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
80			linux,default-trigger = "heartbeat";
81		};
82	};
83
84	reg_sd1_vmmc: regulator-sd1-vmmc {
85		compatible = "regulator-fixed";
86		regulator-name = "VCC3V3_SD1";
87		regulator-min-microvolt = <3300000>;
88		regulator-max-microvolt = <3300000>;
89		regulator-always-on;
90	};
91
92	reg_fec1_pwdn: regulator-fec1-pwdn {
93		compatible = "regulator-fixed";
94		regulator-name = "PWDN_FEC1";
95		regulator-min-microvolt = <3300000>;
96		regulator-max-microvolt = <3300000>;
97		regulator-always-on;
98		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
99		enable-active-high;
100	};
101
102	reg_fec2_pwdn: regulator-fec2-pwdn {
103		compatible = "regulator-fixed";
104		regulator-name = "PWDN_FEC2";
105		regulator-min-microvolt = <3300000>;
106		regulator-max-microvolt = <3300000>;
107		regulator-always-on;
108		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
109		enable-active-high;
110	};
111
112	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
113		compatible = "regulator-fixed";
114		regulator-name = "VBUS_USBOTG1";
115		regulator-min-microvolt = <5000000>;
116		regulator-max-microvolt = <5000000>;
117		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
118		enable-active-high;
119	};
120
121	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
122		compatible = "regulator-fixed";
123		regulator-name = "VBUS_USBOTG2";
124		regulator-min-microvolt = <5000000>;
125		regulator-max-microvolt = <5000000>;
126		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
127		enable-active-high;
128	};
129
130	reg_mpcie_1v5: regulator-mpcie-1v5 {
131		compatible = "regulator-fixed";
132		regulator-name = "VCC1V5_MPCIE";
133		regulator-min-microvolt = <1500000>;
134		regulator-max-microvolt = <1500000>;
135		gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
136		enable-active-high;
137		regulator-always-on;
138	};
139
140	reg_mpcie_3v3: regulator-mpcie-3v3 {
141		compatible = "regulator-fixed";
142		regulator-name = "VCC3V3_MPCIE";
143		regulator-min-microvolt = <3300000>;
144		regulator-max-microvolt = <3300000>;
145		gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
146		enable-active-high;
147		regulator-always-on;
148	};
149
150	reg_mba_12v0: regulator-mba-12v0 {
151		compatible = "regulator-fixed";
152		regulator-name = "VCC12V0_MBA7";
153		regulator-min-microvolt = <12000000>;
154		regulator-max-microvolt = <12000000>;
155		gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
156		enable-active-high;
157	};
158
159	reg_lvds_transmitter: regulator-lvds-transmitter {
160		compatible = "regulator-fixed";
161		regulator-name = "#SHTDN_LVDS";
162		regulator-min-microvolt = <3300000>;
163		regulator-max-microvolt = <3300000>;
164		gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
165		enable-active-high;
166	};
167
168	reg_vref_1v8: regulator-vref-1v8 {
169		compatible = "regulator-fixed";
170		regulator-name = "VCC1V8_REF";
171		regulator-min-microvolt = <1800000>;
172		regulator-max-microvolt = <1800000>;
173		regulator-always-on;
174		vin-supply = <&sw2_reg>;
175	};
176
177	reg_audio_3v3: regulator-audio-3v3 {
178		compatible = "regulator-fixed";
179		regulator-name = "VCC3V3_AUDIO";
180		regulator-min-microvolt = <3300000>;
181		regulator-max-microvolt = <3300000>;
182		regulator-always-on;
183	};
184
185	reg_vcc_3v3: regulator-vcc-3v3 {
186		compatible = "regulator-fixed";
187		regulator-name = "VCC3V3";
188		regulator-min-microvolt = <3300000>;
189		regulator-max-microvolt = <3300000>;
190		regulator-always-on;
191	};
192
193	sound {
194		compatible = "fsl,imx-audio-tlv320aic32x4";
195		model = "imx-audio-tlv320aic32x4";
196		ssi-controller = <&sai1>;
197		audio-codec = <&tlv320aic32x4>;
198		audio-routing =
199			"IN3_L", "Mic Jack",
200			"Mic Jack", "Mic Bias",
201			"IN1_L", "Line In Jack",
202			"IN1_R", "Line In Jack",
203			"Line Out Jack", "LOL",
204			"Line Out Jack", "LOR";
205	};
206};
207
208&adc1 {
209	vref-supply = <&reg_vref_1v8>;
210	status = "okay";
211};
212
213&adc2 {
214	vref-supply = <&reg_vref_1v8>;
215	status = "okay";
216};
217
218&ecspi1 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
221	cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
222		   <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
223	status = "okay";
224};
225
226&ecspi2 {
227	pinctrl-names = "default";
228	pinctrl-0 = <&pinctrl_ecspi2>;
229	status = "okay";
230};
231
232&fec1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_enet1>;
235	phy-mode = "rgmii-id";
236	phy-supply = <&reg_fec1_pwdn>;
237	phy-handle = <&ethphy1_0>;
238	fsl,magic-packet;
239	status = "okay";
240
241	mdio {
242		#address-cells = <1>;
243		#size-cells = <0>;
244
245		ethphy1_0: ethernet-phy@0 {
246			compatible = "ethernet-phy-ieee802.3-c22";
247			reg = <0>;
248			pinctrl-names = "default";
249			pinctrl-0 = <&pinctrl_enet1_phy>;
250			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
251			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
252			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
254			reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
255			reset-assert-us = <1000>;
256			reset-deassert-us = <500>;
257		};
258	};
259};
260
261&flash0 {
262	partitions {
263		compatible = "fixed-partitions";
264		#address-cells = <1>;
265		#size-cells = <1>;
266
267		uboot@0 {
268			label = "U-Boot";
269			reg = <0x0 0xd0000>;
270		};
271
272		env1@d0000 {
273			label = "ENV1";
274			reg = <0xd0000 0x10000>;
275		};
276
277		env2@e0000 {
278			label = "ENV2";
279			reg = <0xe0000 0x10000>;
280		};
281
282		dtb@f0000 {
283			label = "DTB";
284			reg = <0xf0000 0x10000>;
285		};
286
287		linux@100000 {
288			label = "Linux";
289			reg = <0x100000 0x700000>;
290		};
291
292		rootfs@800000 {
293			label = "RootFS";
294			reg = <0x800000 0x3800000>;
295		};
296	};
297};
298
299&flexcan1 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_flexcan1>;
302	status = "okay";
303};
304
305&flexcan2 {
306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_flexcan2>;
308	status = "okay";
309};
310
311&i2c1 {
312	lm75: temperature-sensor@49 {
313		compatible = "national,lm75";
314		reg = <0x49>;
315		vs-supply = <&reg_vcc_3v3>;
316	};
317};
318
319&i2c2 {
320	clock-frequency = <100000>;
321	pinctrl-names = "default", "gpio";
322	pinctrl-0 = <&pinctrl_i2c2>;
323	pinctrl-1 = <&pinctrl_i2c2_recovery>;
324	scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
325	sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
326	status = "okay";
327
328	tlv320aic32x4: audio-codec@18 {
329		compatible = "ti,tlv320aic32x4";
330		reg = <0x18>;
331		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
332		clock-names = "mclk";
333		ldoin-supply = <&reg_audio_3v3>;
334		iov-supply = <&reg_audio_3v3>;
335	};
336
337	pca9555: gpio-expander@20 {
338		compatible = "nxp,pca9555";
339		reg = <0x20>;
340		pinctrl-names = "default";
341		pinctrl-0 = <&pinctrl_pca9555>;
342		gpio-controller;
343		#gpio-cells = <2>;
344		interrupt-parent = <&gpio7>;
345		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
346		interrupt-controller;
347		#interrupt-cells = <2>;
348		vcc-supply = <&reg_vcc_3v3>;
349	};
350};
351
352&i2c3 {
353	clock-frequency = <100000>;
354	pinctrl-names = "default", "gpio";
355	pinctrl-0 = <&pinctrl_i2c3>;
356	pinctrl-1 = <&pinctrl_i2c3_recovery>;
357	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
358	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
359	status = "okay";
360};
361
362&iomuxc {
363	pinctrl-names = "default";
364	pinctrl-0 = <&pinctrl_hog_mba7_1>;
365
366	pinctrl_ecspi1: ecspi1grp {
367		fsl,pins =
368			<MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO		0x7c>,
369			<MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x74>,
370			<MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x74>,
371			<MX7D_PAD_UART1_RX_DATA__GPIO4_IO0		0x74>,
372			<MX7D_PAD_UART1_TX_DATA__GPIO4_IO1		0x74>,
373			<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2		0x74>;
374	};
375
376	pinctrl_ecspi1_ss0: ecspi1ss0grp {
377		fsl,pins = <
378			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19			0x74
379		>;
380	};
381
382	pinctrl_ecspi2: ecspi2grp {
383		fsl,pins =
384			<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO		0x7c>,
385			<MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI		0x74>,
386			<MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK		0x74>,
387			<MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0		0x74>;
388	};
389
390	pinctrl_enet1: enet1grp {
391		fsl,pins =
392			<MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x02>,
393			<MX7D_PAD_GPIO1_IO11__ENET1_MDC				0x00>,
394			<MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC		0x71>,
395			<MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0		0x71>,
396			<MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1		0x71>,
397			<MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2		0x71>,
398			<MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3		0x71>,
399			<MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71>,
400			<MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC		0x79>,
401			<MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0		0x79>,
402			<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x79>,
403			<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x79>,
404			<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x79>,
405			<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79>;
406	};
407
408	pinctrl_enet1_phy: enet1phygrp {
409		fsl,pins =
410			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
411			<MX7D_PAD_ENET1_COL__GPIO7_IO15				0x40000070>,
412			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
413			<MX7D_PAD_GPIO1_IO09__GPIO1_IO9				0x40000078>;
414	};
415
416	pinctrl_flexcan1: flexcan1grp {
417		fsl,pins =
418			<MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x5a>,
419			<MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x52>;
420	};
421
422	pinctrl_flexcan2: flexcan2grp {
423		fsl,pins =
424			<MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x5a>,
425			<MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x52>;
426	};
427
428	pinctrl_hog_mba7_1: hogmba71grp {
429		fsl,pins =
430			/* Limitation: WDOG2_B / WDOG2_RESET not usable */
431			<MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13	0x4000007c>,
432			<MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x40000074>,
433			/* #BOOT_EN */
434			<MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x40000010>;
435	};
436
437	pinctrl_i2c2: i2c2grp {
438		fsl,pins =
439			<MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000078>,
440			<MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000078>;
441	};
442
443	pinctrl_i2c2_recovery: i2c2recoverygrp {
444		fsl,pins =
445			<MX7D_PAD_I2C2_SCL__GPIO4_IO10		0x40000078>,
446			<MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x40000078>;
447	};
448
449	pinctrl_i2c3: i2c3grp {
450		fsl,pins =
451			<MX7D_PAD_I2C3_SCL__I2C3_SCL		0x40000078>,
452			<MX7D_PAD_I2C3_SDA__I2C3_SDA		0x40000078>;
453	};
454
455	pinctrl_i2c3_recovery: i2c3recoverygrp {
456		fsl,pins =
457			<MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x40000078>,
458			<MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x40000078>;
459	};
460
461	pinctrl_pca9555: pca95550grp {
462		fsl,pins =
463			<MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x78>;
464	};
465
466	pinctrl_sai1: sai1grp {
467		fsl,pins =
468			<MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x11>,
469			<MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK	0x1c>,
470			<MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1c>,
471			<MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC	0x1c>,
472
473			<MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1c>,
474			<MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x14>,
475			<MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x14>;
476	};
477
478	pinctrl_uart3: uart3grp {
479		fsl,pins =
480			<MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x7e>,
481			<MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x76>,
482			<MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x76>,
483			<MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x7e>;
484	};
485
486	pinctrl_uart4: uart4grp {
487		fsl,pins =
488			<MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX	0x7e>,
489			<MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX	0x76>,
490			<MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS	0x76>,
491			<MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS	0x7e>;
492	};
493
494	pinctrl_uart5: uart5grp {
495		fsl,pins =
496			<MX7D_PAD_I2C4_SCL__UART5_DCE_RX	0x7e>,
497			<MX7D_PAD_I2C4_SDA__UART5_DCE_TX	0x76>;
498	};
499
500	pinctrl_uart6: uart6grp {
501		fsl,pins =
502			<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x7d>,
503			<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x75>,
504			<MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x75>,
505			<MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x7d>;
506	};
507
508	pinctrl_uart7: uart7grp {
509		fsl,pins =
510			<MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x7e>,
511			<MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x76>,
512			<MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS	0x76>,
513			/* Limitation: RTS is not connected */
514			<MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS	0x7e>;
515	};
516
517	pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
518		fsl,pins =
519			/* WP */
520			<MX7D_PAD_SD1_WP__GPIO5_IO1		0x7c>,
521			/* CD */
522			<MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x7c>,
523			/* VSELECT */
524			<MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59>;
525	};
526
527	pinctrl_usdhc1: usdhc1grp {
528		fsl,pins =
529			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5e>,
530			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
531			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5e>,
532			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5e>,
533			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5e>,
534			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5e>;
535	};
536
537	pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
538		fsl,pins =
539			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5a>,
540			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
541			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a>,
542			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a>,
543			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a>,
544			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a>;
545	};
546
547	pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp {
548		fsl,pins =
549			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5b>,
550			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
551			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b>,
552			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b>,
553			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b>,
554			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b>;
555	};
556};
557
558&iomuxc_lpsr {
559	pinctrl_pwm1: pwm1grp {
560		fsl,pins =
561			/* LCD_CONTRAST */
562			<MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x50>;
563	};
564
565	pinctrl_usbotg1: usbotg1grp {
566		fsl,pins =
567			<MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x5c>,
568			<MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x59>;
569	};
570
571	pinctrl_wdog1: wdog1grp {
572		fsl,pins =
573			<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30>;
574	};
575};
576
577&pwm1 {
578	pinctrl-names = "default";
579	pinctrl-0 = <&pinctrl_pwm1>;
580	status = "okay";
581};
582
583&sai1 {
584	pinctrl-names = "default";
585	pinctrl-0 = <&pinctrl_sai1>;
586	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
587			  <&clks IMX7D_SAI1_ROOT_CLK>;
588	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
589	assigned-clock-rates = <0>, <36864000>;
590	status = "okay";
591};
592
593&snvs_pwrkey {
594	status = "okay";
595};
596
597&uart3 {
598	pinctrl-names = "default";
599	pinctrl-0 = <&pinctrl_uart3>;
600	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
601	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
602	status = "okay";
603};
604
605&uart4 {
606	pinctrl-names = "default";
607	pinctrl-0 = <&pinctrl_uart4>;
608	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
609	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
610	status = "okay";
611};
612
613&uart5 {
614	pinctrl-names = "default";
615	pinctrl-0 = <&pinctrl_uart5>;
616	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
617	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
618	status = "okay";
619};
620
621&uart6 {
622	pinctrl-names = "default";
623	pinctrl-0 = <&pinctrl_uart6>;
624	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
625	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
626	status = "okay";
627};
628
629&uart7 {
630	pinctrl-names = "default";
631	pinctrl-0 = <&pinctrl_uart7>;
632	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
633	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
634	uart-has-rtscts;
635	linux,rs485-enabled-at-boot-time;
636	rs485-rts-active-low;
637	rs485-rx-during-tx;
638	status = "okay";
639};
640
641&usbh {
642	disable-over-current;
643	status = "okay";
644};
645
646&usbotg1 {
647	pinctrl-names = "default";
648	pinctrl-0 = <&pinctrl_usbotg1>;
649	vbus-supply = <&reg_usb_otg1_vbus>;
650	srp-disable;
651	hnp-disable;
652	adp-disable;
653	over-current-active-low;
654	dr_mode = "otg";
655	status = "okay";
656};
657
658&usdhc1 {
659	pinctrl-names = "default", "state_100mhz", "state_200mhz";
660	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
661	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
662	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
663	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
664	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
665	vmmc-supply = <&reg_sd1_vmmc>;
666	bus-width = <4>;
667	no-1-8-v;
668	no-sdio;
669	no-emmc;
670	status = "okay";
671};
672
673&wdog1 {
674	pinctrl-names = "default";
675	pinctrl-0 = <&pinctrl_wdog1>;
676	fsl,ext-reset-output;
677};
678