xref: /linux/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2019 PHYTEC Messtechnik GmbH
4*724ba675SRob Herring * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
5*724ba675SRob Herring */
6*724ba675SRob Herring
7*724ba675SRob Herring#include "imx6ul-phytec-segin.dtsi"
8*724ba675SRob Herring
9*724ba675SRob Herring/ {
10*724ba675SRob Herring	model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
11*724ba675SRob Herring	compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
12*724ba675SRob Herring};
13*724ba675SRob Herring
14*724ba675SRob Herring&iomuxc {
15*724ba675SRob Herring	/delete-node/ flexcan1engrp;
16*724ba675SRob Herring	/delete-node/ rtcintgrp;
17*724ba675SRob Herring};
18*724ba675SRob Herring
19*724ba675SRob Herring&iomuxc_snvs {
20*724ba675SRob Herring	princtrl_flexcan1_en: flexcan1engrp {
21*724ba675SRob Herring		fsl,pins = <
22*724ba675SRob Herring			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
23*724ba675SRob Herring		>;
24*724ba675SRob Herring	};
25*724ba675SRob Herring
26*724ba675SRob Herring	pinctrl_rtc_int: rtcintgrp {
27*724ba675SRob Herring		fsl,pins = <
28*724ba675SRob Herring			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
29*724ba675SRob Herring		>;
30*724ba675SRob Herring	};
31*724ba675SRob Herring};
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