1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2018-2022 TQ-Systems GmbH 4*724ba675SRob Herring * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/* 8*724ba675SRob Herring * Common for 9*724ba675SRob Herring * - TQMa6ULx 10*724ba675SRob Herring * - TQMa6ULLx 11*724ba675SRob Herring */ 12*724ba675SRob Herring 13*724ba675SRob Herring&m24c64_50 { 14*724ba675SRob Herring vcc-supply = <®_sw2>; 15*724ba675SRob Herring}; 16*724ba675SRob Herring 17*724ba675SRob Herring&m24c02_52 { 18*724ba675SRob Herring vcc-supply = <®_sw2>; 19*724ba675SRob Herring}; 20*724ba675SRob Herring 21*724ba675SRob Herring®_sw2 { 22*724ba675SRob Herring regulator-boot-on; 23*724ba675SRob Herring regulator-always-on; 24*724ba675SRob Herring}; 25*724ba675SRob Herring 26*724ba675SRob Herring/* eMMC */ 27*724ba675SRob Herring&usdhc2 { 28*724ba675SRob Herring vmmc-supply = <®_sw2>; 29*724ba675SRob Herring vqmmc-supply = <®_vldo4>; 30*724ba675SRob Herring}; 31*724ba675SRob Herring 32*724ba675SRob Herring&iomuxc { 33*724ba675SRob Herring pinctrl_qspi: qspigrp { 34*724ba675SRob Herring fsl,pins = < 35*724ba675SRob Herring MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 36*724ba675SRob Herring MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 37*724ba675SRob Herring MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 38*724ba675SRob Herring MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 39*724ba675SRob Herring MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 40*724ba675SRob Herring MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 41*724ba675SRob Herring >; 42*724ba675SRob Herring }; 43*724ba675SRob Herring}; 44