1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2018-2022 TQ-Systems GmbH 4*724ba675SRob Herring * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring 9*724ba675SRob Herring#include "imx6ul-tqma6ul1.dtsi" 10*724ba675SRob Herring#include "mba6ulx.dtsi" 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; 14*724ba675SRob Herring compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; 15*724ba675SRob Herring}; 16*724ba675SRob Herring 17*724ba675SRob Herring/* 18*724ba675SRob Herring * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) 19*724ba675SRob Herring * and need to be disabled here again 20*724ba675SRob Herring */ 21*724ba675SRob Herring&can2 { 22*724ba675SRob Herring status = "disabled"; 23*724ba675SRob Herring}; 24*724ba675SRob Herring 25*724ba675SRob Herring&fec1 { 26*724ba675SRob Herring pinctrl-names = "default"; 27*724ba675SRob Herring pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; 28*724ba675SRob Herring status = "okay"; 29*724ba675SRob Herring 30*724ba675SRob Herring mdio { 31*724ba675SRob Herring #address-cells = <1>; 32*724ba675SRob Herring #size-cells = <0>; 33*724ba675SRob Herring 34*724ba675SRob Herring ethphy0: ethernet-phy@0 { 35*724ba675SRob Herring compatible = "ethernet-phy-ieee802.3-c22"; 36*724ba675SRob Herring max-speed = <100>; 37*724ba675SRob Herring reg = <0>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring }; 40*724ba675SRob Herring}; 41*724ba675SRob Herring 42*724ba675SRob Herring&fec2 { 43*724ba675SRob Herring /delete-property/ phy-handle; 44*724ba675SRob Herring /delete-node/ mdio; 45*724ba675SRob Herring}; 46*724ba675SRob Herring 47*724ba675SRob Herring&iomuxc { 48*724ba675SRob Herring pinctrl_enet1_mdc: enet1mdcgrp { 49*724ba675SRob Herring fsl,pins = < 50*724ba675SRob Herring /* mdio */ 51*724ba675SRob Herring MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 52*724ba675SRob Herring MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 53*724ba675SRob Herring >; 54*724ba675SRob Herring }; 55*724ba675SRob Herring}; 56