1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/media/video-interfaces.h> 6 7/ { 8 chosen { 9 stdout-path = &uart1; 10 }; 11 12 memory@80000000 { 13 device_type = "memory"; 14 reg = <0x80000000 0x20000000>; 15 }; 16 17 backlight_display: backlight-display { 18 compatible = "pwm-backlight"; 19 pwms = <&pwm1 0 5000000 0>; 20 brightness-levels = <0 4 8 16 32 64 128 255>; 21 default-brightness-level = <6>; 22 status = "okay"; 23 }; 24 25 reg_1v5: regulator-1v5 { 26 compatible = "regulator-fixed"; 27 regulator-name = "1v5"; 28 regulator-min-microvolt = <1500000>; 29 regulator-max-microvolt = <1500000>; 30 }; 31 32 reg_1v8: regulator-1v8 { 33 compatible = "regulator-fixed"; 34 regulator-name = "1v8"; 35 regulator-min-microvolt = <1800000>; 36 regulator-max-microvolt = <1800000>; 37 }; 38 39 reg_2v8: regulator-2v8 { 40 compatible = "regulator-fixed"; 41 regulator-name = "2v8"; 42 regulator-min-microvolt = <2800000>; 43 regulator-max-microvolt = <2800000>; 44 }; 45 46 reg_sd1_vmmc: regulator-sd1-vmmc { 47 compatible = "regulator-fixed"; 48 regulator-name = "VSD_3V3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 reg_peri_3v3: regulator-peri-3v3 { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_peri_3v3>; 59 regulator-name = "VPERI_3V3"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 63 /* 64 * If you want to want to make this dynamic please 65 * check schematics and test all affected peripherals: 66 * 67 * - sensors 68 * - ethernet phy 69 * - can 70 * - bluetooth 71 * - wm8960 audio codec 72 * - ov5640 camera 73 */ 74 regulator-always-on; 75 }; 76 77 reg_can_3v3: regulator-can-3v3 { 78 compatible = "regulator-fixed"; 79 regulator-name = "can-3v3"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 83 }; 84 85 reg_audio_5v: regulator-audio-pwr { 86 compatible = "regulator-fixed"; 87 regulator-name = "audio-5v"; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 regulator-always-on; 91 regulator-boot-on; 92 }; 93 94 reg_audio_3v3: regulator-audio-3v3 { 95 compatible = "regulator-fixed"; 96 regulator-name = "audio-3v3"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 regulator-always-on; 100 regulator-boot-on; 101 }; 102 103 reg_audio_1v8: regulator-audio-1v8 { 104 compatible = "regulator-fixed"; 105 regulator-name = "audio-1v8"; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 regulator-always-on; 109 regulator-boot-on; 110 }; 111 112 sound-wm8960 { 113 compatible = "fsl,imx-audio-wm8960"; 114 model = "wm8960-audio"; 115 audio-cpu = <&sai2>; 116 audio-codec = <&codec>; 117 audio-asrc = <&asrc>; 118 hp-det-gpios = <&gpio5 4 0>; 119 audio-routing = 120 "Headphone Jack", "HP_L", 121 "Headphone Jack", "HP_R", 122 "Ext Spk", "SPK_LP", 123 "Ext Spk", "SPK_LN", 124 "Ext Spk", "SPK_RP", 125 "Ext Spk", "SPK_RN", 126 "LINPUT2", "Mic Jack", 127 "LINPUT3", "Mic Jack", 128 "RINPUT1", "AMIC", 129 "RINPUT2", "AMIC", 130 "Mic Jack", "MICB", 131 "AMIC", "MICB"; 132 }; 133 134 spi-4 { 135 compatible = "spi-gpio"; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_spi4>; 138 status = "okay"; 139 sck-gpios = <&gpio5 11 0>; 140 mosi-gpios = <&gpio5 10 0>; 141 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; 142 num-chipselects = <1>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 gpio_spi: gpio@0 { 147 compatible = "fairchild,74hc595"; 148 gpio-controller; 149 #gpio-cells = <2>; 150 reg = <0>; 151 registers-number = <1>; 152 spi-max-frequency = <100000>; 153 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 154 }; 155 }; 156 157 panel { 158 compatible = "innolux,at043tn24"; 159 backlight = <&backlight_display>; 160 161 port { 162 panel_in: endpoint { 163 remote-endpoint = <&display_out>; 164 }; 165 }; 166 }; 167}; 168 169&clks { 170 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 171 assigned-clock-rates = <786432000>; 172}; 173 174&i2c2 { 175 clock-frequency = <100000>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_i2c2>; 178 status = "okay"; 179 180 codec: wm8960@1a { 181 #sound-dai-cells = <0>; 182 compatible = "wlf,wm8960"; 183 reg = <0x1a>; 184 wlf,shared-lrclk; 185 wlf,hp-cfg = <3 2 3>; 186 wlf,gpio-cfg = <1 3>; 187 clocks = <&clks IMX6UL_CLK_SAI2>; 188 clock-names = "mclk"; 189 AVDD-supply = <®_audio_3v3>; 190 DBVDD-supply = <®_audio_1v8>; 191 DCVDD-supply = <®_audio_1v8>; 192 SPKVDD1-supply = <®_audio_5v>; 193 SPKVDD2-supply = <®_audio_5v>; 194 }; 195 196 camera@3c { 197 compatible = "ovti,ov5640"; 198 reg = <0x3c>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_camera_clock>; 201 clocks = <&clks IMX6UL_CLK_CSI>; 202 clock-names = "xclk"; 203 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; 204 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; 205 AVDD-supply = <®_2v8>; 206 DVDD-supply = <®_1v5>; 207 DOVDD-supply = <®_1v8>; 208 209 port { 210 ov5640_to_parallel: endpoint { 211 remote-endpoint = <¶llel_from_ov5640>; 212 bus-width = <8>; 213 data-shift = <2>; /* lines 9:2 are used */ 214 hsync-active = <0>; 215 vsync-active = <0>; 216 pclk-sample = <1>; 217 }; 218 }; 219 }; 220}; 221 222&csi { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_csi1>; 225 status = "okay"; 226 227 port { 228 parallel_from_ov5640: endpoint { 229 remote-endpoint = <&ov5640_to_parallel>; 230 bus-type = <MEDIA_BUS_TYPE_PARALLEL>; 231 }; 232 }; 233}; 234 235&fec1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_enet1>; 238 phy-mode = "rmii"; 239 phy-handle = <ðphy0>; 240 phy-supply = <®_peri_3v3>; 241 status = "okay"; 242}; 243 244&fec2 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_enet2>; 247 phy-mode = "rmii"; 248 phy-handle = <ðphy1>; 249 phy-supply = <®_peri_3v3>; 250 status = "okay"; 251 252 mdio { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 ethphy0: ethernet-phy@2 { 257 compatible = "ethernet-phy-id0022.1560"; 258 reg = <2>; 259 micrel,led-mode = <1>; 260 clocks = <&clks IMX6UL_CLK_ENET_REF>; 261 clock-names = "rmii-ref"; 262 263 }; 264 265 ethphy1: ethernet-phy@1 { 266 compatible = "ethernet-phy-id0022.1560"; 267 reg = <1>; 268 micrel,led-mode = <1>; 269 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 270 clock-names = "rmii-ref"; 271 }; 272 }; 273}; 274 275&can1 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexcan1>; 278 xceiver-supply = <®_can_3v3>; 279 status = "okay"; 280}; 281 282&can2 { 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_flexcan2>; 285 xceiver-supply = <®_can_3v3>; 286 status = "okay"; 287}; 288 289&gpio_spi { 290 eth0-phy-hog { 291 gpio-hog; 292 gpios = <1 GPIO_ACTIVE_HIGH>; 293 output-high; 294 line-name = "eth0-phy"; 295 }; 296 297 eth1-phy-hog { 298 gpio-hog; 299 gpios = <2 GPIO_ACTIVE_HIGH>; 300 output-high; 301 line-name = "eth1-phy"; 302 }; 303}; 304 305&i2c1 { 306 clock-frequency = <100000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_i2c1>; 309 status = "okay"; 310 311 magnetometer@e { 312 compatible = "fsl,mag3110"; 313 reg = <0x0e>; 314 vdd-supply = <®_peri_3v3>; 315 vddio-supply = <®_peri_3v3>; 316 }; 317}; 318 319&lcdif { 320 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 321 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_lcdif_dat 324 &pinctrl_lcdif_ctrl>; 325 status = "okay"; 326 327 port { 328 display_out: endpoint { 329 remote-endpoint = <&panel_in>; 330 }; 331 }; 332}; 333 334&pwm1 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_pwm1>; 337 status = "okay"; 338}; 339 340&qspi { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_qspi>; 343 status = "okay"; 344 345 flash0: flash@0 { 346 #address-cells = <1>; 347 #size-cells = <1>; 348 compatible = "micron,n25q256a", "jedec,spi-nor"; 349 spi-max-frequency = <29000000>; 350 spi-rx-bus-width = <4>; 351 spi-tx-bus-width = <1>; 352 reg = <0>; 353 }; 354}; 355 356&sai2 { 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_sai2>; 359 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 360 <&clks IMX6UL_CLK_SAI2>; 361 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 362 assigned-clock-rates = <0>, <12288000>; 363 fsl,sai-mclk-direction-output; 364 status = "okay"; 365}; 366 367&snvs_poweroff { 368 status = "okay"; 369}; 370 371&snvs_pwrkey { 372 status = "okay"; 373}; 374 375&tsc { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_tsc>; 378 xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 379 measure-delay-time = <0xffff>; 380 pre-charge-time = <0xfff>; 381 status = "okay"; 382}; 383 384&uart1 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_uart1>; 387 status = "okay"; 388}; 389 390&uart2 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_uart2>; 393 uart-has-rtscts; 394 status = "okay"; 395}; 396 397&usbotg1 { 398 dr_mode = "otg"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_usb_otg1>; 401 status = "okay"; 402}; 403 404&usbotg2 { 405 dr_mode = "host"; 406 disable-over-current; 407 status = "okay"; 408}; 409 410&usbphy1 { 411 fsl,tx-d-cal = <106>; 412}; 413 414&usbphy2 { 415 fsl,tx-d-cal = <106>; 416}; 417 418&usdhc1 { 419 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 420 pinctrl-0 = <&pinctrl_usdhc1>; 421 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 422 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 423 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 424 keep-power-in-suspend; 425 wakeup-source; 426 vmmc-supply = <®_sd1_vmmc>; 427 status = "okay"; 428}; 429 430&usdhc2 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_usdhc2>; 433 no-1-8-v; 434 broken-cd; 435 keep-power-in-suspend; 436 wakeup-source; 437 status = "okay"; 438}; 439 440&wdog1 { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_wdog>; 443 fsl,ext-reset-output; 444}; 445 446&iomuxc { 447 pinctrl_camera_clock: cameraclockgrp { 448 fsl,pins = < 449 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 450 >; 451 }; 452 453 pinctrl_csi1: csi1grp { 454 fsl,pins = < 455 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 456 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 457 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 458 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 459 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 460 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 461 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 462 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 463 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 464 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 465 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 466 >; 467 }; 468 469 pinctrl_enet1: enet1grp { 470 fsl,pins = < 471 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 472 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 473 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 474 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 475 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 476 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 477 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 478 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 479 >; 480 }; 481 482 pinctrl_enet2: enet2grp { 483 fsl,pins = < 484 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 485 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 486 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 487 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 488 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 489 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 490 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 491 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 492 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 493 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 494 >; 495 }; 496 497 pinctrl_flexcan1: flexcan1grp { 498 fsl,pins = < 499 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 500 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 501 >; 502 }; 503 504 pinctrl_flexcan2: flexcan2grp { 505 fsl,pins = < 506 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 507 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 508 >; 509 }; 510 511 pinctrl_i2c1: i2c1grp { 512 fsl,pins = < 513 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 514 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 515 >; 516 }; 517 518 pinctrl_i2c2: i2c2grp { 519 fsl,pins = < 520 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 521 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 522 >; 523 }; 524 525 pinctrl_lcdif_dat: lcdifdatgrp { 526 fsl,pins = < 527 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 528 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 529 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 530 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 531 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 532 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 533 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 534 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 535 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 536 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 537 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 538 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 539 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 540 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 541 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 542 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 543 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 544 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 545 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 546 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 547 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 548 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 549 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 550 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 551 >; 552 }; 553 554 pinctrl_lcdif_ctrl: lcdifctrlgrp { 555 fsl,pins = < 556 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 557 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 558 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 559 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 560 /* used for lcd reset */ 561 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 562 >; 563 }; 564 565 pinctrl_qspi: qspigrp { 566 fsl,pins = < 567 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 568 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 569 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 570 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 571 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 572 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 573 >; 574 }; 575 576 pinctrl_sai2: sai2grp { 577 fsl,pins = < 578 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 579 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 580 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 581 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 582 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 583 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 584 >; 585 }; 586 587 pinctrl_peri_3v3: peri3v3grp { 588 fsl,pins = < 589 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 590 >; 591 }; 592 593 pinctrl_pwm1: pwm1grp { 594 fsl,pins = < 595 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 596 >; 597 }; 598 599 pinctrl_sim2: sim2grp { 600 fsl,pins = < 601 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 602 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 603 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 604 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 605 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 606 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 607 >; 608 }; 609 610 pinctrl_spi4: spi4grp { 611 fsl,pins = < 612 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 613 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 614 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 615 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 616 >; 617 }; 618 619 pinctrl_tsc: tscgrp { 620 fsl,pins = < 621 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 622 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 623 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 624 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 625 >; 626 }; 627 628 pinctrl_uart1: uart1grp { 629 fsl,pins = < 630 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 631 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 632 >; 633 }; 634 635 pinctrl_uart2: uart2grp { 636 fsl,pins = < 637 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 638 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 639 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 640 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 641 >; 642 }; 643 644 pinctrl_usb_otg1: usbotg1grp { 645 fsl,pins = < 646 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 647 >; 648 }; 649 650 pinctrl_usdhc1: usdhc1grp { 651 fsl,pins = < 652 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 653 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 654 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 655 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 656 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 657 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 658 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 659 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 660 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 661 >; 662 }; 663 664 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 665 fsl,pins = < 666 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 667 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 668 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 669 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 670 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 671 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 672 673 >; 674 }; 675 676 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 677 fsl,pins = < 678 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 679 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 680 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 681 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 682 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 683 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 684 >; 685 }; 686 687 pinctrl_usdhc2: usdhc2grp { 688 fsl,pins = < 689 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 690 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 691 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 692 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 693 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 694 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 695 >; 696 }; 697 698 pinctrl_wdog: wdoggrp { 699 fsl,pins = < 700 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 701 >; 702 }; 703}; 704