1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2014 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include "imx6sx.dtsi" 8 9/ { 10 model = "Freescale i.MX6 SoloX Sabre Auto Board"; 11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; 12 13 memory@80000000 { 14 device_type = "memory"; 15 reg = <0x80000000 0x80000000>; 16 }; 17 18 leds { 19 compatible = "gpio-leds"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_led>; 22 23 led-user { 24 label = "debug"; 25 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 26 linux,default-trigger = "heartbeat"; 27 }; 28 }; 29 30 vcc_sd3: regulator-vcc-sd3 { 31 compatible = "regulator-fixed"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_vcc_sd3>; 34 regulator-name = "VCC_SD3"; 35 regulator-min-microvolt = <3000000>; 36 regulator-max-microvolt = <3000000>; 37 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40 41 reg_can_wake: regulator-can-wake { 42 compatible = "regulator-fixed"; 43 regulator-name = "can-wake"; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; 47 enable-active-high; 48 }; 49 50 reg_can_en: regulator-can-en { 51 compatible = "regulator-fixed"; 52 regulator-name = "can-en"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; 56 enable-active-high; 57 vin-supply = <®_can_wake>; 58 }; 59 60 reg_can_stby: regulator-can-stby { 61 compatible = "regulator-fixed"; 62 regulator-name = "can-stby"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 vin-supply = <®_can_en>; 68 }; 69 70 reg_cs42888: cs42888_supply { 71 compatible = "regulator-fixed"; 72 regulator-name = "cs42888_supply"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-always-on; 76 }; 77 78 sound-cs42888 { 79 compatible = "fsl,imx6-sabreauto-cs42888", 80 "fsl,imx-audio-cs42888"; 81 model = "imx-cs42888"; 82 audio-cpu = <&esai>; 83 audio-asrc = <&asrc>; 84 audio-codec = <&cs42888>; 85 audio-routing = 86 "Line Out Jack", "AOUT1L", 87 "Line Out Jack", "AOUT1R", 88 "Line Out Jack", "AOUT2L", 89 "Line Out Jack", "AOUT2R", 90 "Line Out Jack", "AOUT3L", 91 "Line Out Jack", "AOUT3R", 92 "Line Out Jack", "AOUT4L", 93 "Line Out Jack", "AOUT4R", 94 "AIN1L", "Line In Jack", 95 "AIN1R", "Line In Jack", 96 "AIN2L", "Line In Jack", 97 "AIN2R", "Line In Jack"; 98 }; 99 100 spdif_in: spdif-in { 101 compatible = "linux,spdif-dir"; 102 #sound-dai-cells = <0>; 103 }; 104 105 sound-spdif { 106 compatible = "fsl,imx-audio-spdif"; 107 model = "imx-spdif"; 108 audio-cpu = <&spdif>; 109 audio-codec = <&spdif_in>; 110 }; 111}; 112 113&anaclk2 { 114 clock-frequency = <24576000>; 115}; 116 117&clks { 118 assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, 119 <&clks IMX6SX_PLL4_BYPASS>, 120 <&clks IMX6SX_CLK_PLL4_POST_DIV>; 121 assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, 122 <&clks IMX6SX_PLL4_BYPASS_SRC>; 123 assigned-clock-rates = <0>, <0>, <24576000>; 124}; 125 126&esai { 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_esai>; 129 assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, 130 <&clks IMX6SX_CLK_ESAI_EXTAL>; 131 assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; 132 assigned-clock-rates = <0>, <24576000>; 133 status = "okay"; 134}; 135 136&fec1 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_enet1>; 139 phy-mode = "rgmii-id"; 140 phy-handle = <ðphy1>; 141 fsl,magic-packet; 142 status = "okay"; 143 144 mdio { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 148 ethphy0: ethernet-phy@0 { 149 compatible = "ethernet-phy-ieee802.3-c22"; 150 reg = <0>; 151 }; 152 153 ethphy1: ethernet-phy@1 { 154 compatible = "ethernet-phy-ieee802.3-c22"; 155 reg = <1>; 156 }; 157 }; 158}; 159 160&fec2 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_enet2>; 163 phy-mode = "rgmii-id"; 164 phy-handle = <ðphy0>; 165 fsl,magic-packet; 166 status = "okay"; 167}; 168 169&flexcan1 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_flexcan1>; 172 xceiver-supply = <®_can_stby>; 173 status = "okay"; 174}; 175 176&flexcan2 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_flexcan2>; 179 xceiver-supply = <®_can_stby>; 180 status = "okay"; 181}; 182 183&uart1 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_uart1>; 186 status = "okay"; 187}; 188 189&usdhc3 { 190 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 191 pinctrl-0 = <&pinctrl_usdhc3>; 192 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 193 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 194 bus-width = <8>; 195 cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 196 wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 197 keep-power-in-suspend; 198 wakeup-source; 199 vmmc-supply = <&vcc_sd3>; 200 status = "okay"; 201}; 202 203&usdhc4 { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_usdhc4>; 206 bus-width = <8>; 207 cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; 208 no-1-8-v; 209 keep-power-in-suspend; 210 wakeup-source; 211 status = "okay"; 212}; 213 214&iomuxc { 215 pinctrl_egalax_int: egalax-intgrp { 216 fsl,pins = < 217 MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 218 >; 219 }; 220 221 pinctrl_enet1: enet1grp { 222 fsl,pins = < 223 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 224 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 225 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 226 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 227 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 228 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 229 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 230 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 231 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 232 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 233 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 234 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 235 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 236 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 237 >; 238 }; 239 240 pinctrl_enet2: enet2grp { 241 fsl,pins = < 242 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 243 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 244 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 245 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 246 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 247 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 248 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 249 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 250 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 251 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 252 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 253 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 254 >; 255 }; 256 257 pinctrl_esai: esaigrp { 258 fsl,pins = < 259 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 260 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 261 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 262 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 263 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 264 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 265 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 266 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 267 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 268 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 269 >; 270 }; 271 272 pinctrl_flexcan1: flexcan1grp { 273 fsl,pins = < 274 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 275 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 276 >; 277 }; 278 279 pinctrl_flexcan2: flexcan2grp { 280 fsl,pins = < 281 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 282 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 283 >; 284 }; 285 286 pinctrl_i2c2: i2c2grp { 287 fsl,pins = < 288 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 289 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 290 >; 291 }; 292 293 pinctrl_i2c3: i2c3grp { 294 fsl,pins = < 295 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 296 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 297 >; 298 }; 299 300 pinctrl_led: ledgrp { 301 fsl,pins = < 302 MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 303 >; 304 }; 305 306 pinctrl_spdif: spdifgrp { 307 fsl,pins = < 308 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 309 >; 310 }; 311 312 pinctrl_uart1: uart1grp { 313 fsl,pins = < 314 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 315 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 316 >; 317 }; 318 319 pinctrl_usdhc3: usdhc3grp { 320 fsl,pins = < 321 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 322 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 323 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 324 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 325 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 326 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 327 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 328 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 329 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 330 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 331 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 332 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 333 >; 334 }; 335 336 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 337 fsl,pins = < 338 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 339 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 340 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 341 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 342 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 343 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 344 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 345 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 346 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 347 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 348 >; 349 }; 350 351 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 352 fsl,pins = < 353 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 354 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 355 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 356 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 357 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 358 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 359 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 360 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 361 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 362 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 363 >; 364 }; 365 366 pinctrl_usdhc4: usdhc4grp { 367 fsl,pins = < 368 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 369 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 370 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 371 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 372 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 373 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 374 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 375 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 376 >; 377 }; 378 379 pinctrl_vcc_sd3: vccsd3grp { 380 fsl,pins = < 381 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 382 >; 383 }; 384 385 pinctrl_wdog: wdoggrp { 386 fsl,pins = < 387 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 388 >; 389 }; 390}; 391 392&i2c2 { 393 clock-frequency = <100000>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_i2c2>; 396 status = "okay"; 397 398 cs42888: cs42888@48 { 399 compatible = "cirrus,cs42888"; 400 reg = <0x48>; 401 clocks = <&anaclk2 0>; 402 clock-names = "mclk"; 403 VA-supply = <®_cs42888>; 404 VD-supply = <®_cs42888>; 405 VLS-supply = <®_cs42888>; 406 VLC-supply = <®_cs42888>; 407 }; 408 409 touchscreen@4 { 410 compatible = "eeti,egalax_ts"; 411 reg = <0x04>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_egalax_int>; 414 interrupt-parent = <&gpio6>; 415 interrupts = <22 IRQ_TYPE_EDGE_FALLING>; 416 wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; 417 }; 418 419 pfuze100: pmic@8 { 420 compatible = "fsl,pfuze100"; 421 reg = <0x08>; 422 423 regulators { 424 sw1a_reg: sw1ab { 425 regulator-min-microvolt = <300000>; 426 regulator-max-microvolt = <1875000>; 427 regulator-boot-on; 428 regulator-always-on; 429 regulator-ramp-delay = <6250>; 430 }; 431 432 sw1c_reg: sw1c { 433 regulator-min-microvolt = <300000>; 434 regulator-max-microvolt = <1875000>; 435 regulator-boot-on; 436 regulator-always-on; 437 regulator-ramp-delay = <6250>; 438 }; 439 440 sw2_reg: sw2 { 441 regulator-min-microvolt = <800000>; 442 regulator-max-microvolt = <3300000>; 443 regulator-boot-on; 444 regulator-always-on; 445 }; 446 447 sw3a_reg: sw3a { 448 regulator-min-microvolt = <400000>; 449 regulator-max-microvolt = <1975000>; 450 regulator-boot-on; 451 regulator-always-on; 452 }; 453 454 sw3b_reg: sw3b { 455 regulator-min-microvolt = <400000>; 456 regulator-max-microvolt = <1975000>; 457 regulator-boot-on; 458 regulator-always-on; 459 }; 460 461 sw4_reg: sw4 { 462 regulator-min-microvolt = <800000>; 463 regulator-max-microvolt = <3300000>; 464 regulator-always-on; 465 }; 466 467 swbst_reg: swbst { 468 regulator-min-microvolt = <5000000>; 469 regulator-max-microvolt = <5150000>; 470 }; 471 472 snvs_reg: vsnvs { 473 regulator-min-microvolt = <1000000>; 474 regulator-max-microvolt = <3000000>; 475 regulator-boot-on; 476 regulator-always-on; 477 }; 478 479 vref_reg: vrefddr { 480 regulator-boot-on; 481 regulator-always-on; 482 }; 483 484 vgen1_reg: vgen1 { 485 regulator-min-microvolt = <800000>; 486 regulator-max-microvolt = <1550000>; 487 regulator-always-on; 488 }; 489 490 vgen2_reg: vgen2 { 491 regulator-min-microvolt = <800000>; 492 regulator-max-microvolt = <1550000>; 493 }; 494 495 vgen3_reg: vgen3 { 496 regulator-min-microvolt = <1800000>; 497 regulator-max-microvolt = <3300000>; 498 regulator-always-on; 499 }; 500 501 vgen4_reg: vgen4 { 502 regulator-min-microvolt = <1800000>; 503 regulator-max-microvolt = <3300000>; 504 regulator-always-on; 505 }; 506 507 vgen5_reg: vgen5 { 508 regulator-min-microvolt = <1800000>; 509 regulator-max-microvolt = <3300000>; 510 regulator-always-on; 511 }; 512 513 vgen6_reg: vgen6 { 514 regulator-min-microvolt = <1800000>; 515 regulator-max-microvolt = <3300000>; 516 regulator-always-on; 517 }; 518 }; 519 }; 520 521 max7322: gpio@68 { 522 compatible = "maxim,max7322"; 523 reg = <0x68>; 524 gpio-controller; 525 #gpio-cells = <2>; 526 }; 527}; 528 529&i2c3 { 530 clock-frequency = <100000>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_i2c3>; 533 status = "okay"; 534 535 max7310_a: gpio@30 { 536 compatible = "maxim,max7310"; 537 reg = <0x30>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 }; 541 542 max7310_b: gpio@32 { 543 compatible = "maxim,max7310"; 544 reg = <0x32>; 545 gpio-controller; 546 #gpio-cells = <2>; 547 }; 548}; 549 550&spdif { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_spdif>; 553 assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; 554 assigned-clock-rates = <24576000>; 555 status = "okay"; 556}; 557 558&wdog1 { 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pinctrl_wdog>; 561 fsl,ext-reset-output; 562}; 563