1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring// 3*724ba675SRob Herring// Copyright 2011 Freescale Semiconductor, Inc. 4*724ba675SRob Herring// Copyright 2011 Linaro Ltd. 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/clock/imx6qdl-clock.h> 7*724ba675SRob Herring#include <dt-bindings/input/input.h> 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring #address-cells = <1>; 12*724ba675SRob Herring #size-cells = <1>; 13*724ba675SRob Herring /* 14*724ba675SRob Herring * The decompressor and also some bootloaders rely on a 15*724ba675SRob Herring * pre-existing /chosen node to be available to insert the 16*724ba675SRob Herring * command line and merge other ATAGS info. 17*724ba675SRob Herring */ 18*724ba675SRob Herring chosen {}; 19*724ba675SRob Herring 20*724ba675SRob Herring aliases { 21*724ba675SRob Herring ethernet0 = &fec; 22*724ba675SRob Herring can0 = &can1; 23*724ba675SRob Herring can1 = &can2; 24*724ba675SRob Herring gpio0 = &gpio1; 25*724ba675SRob Herring gpio1 = &gpio2; 26*724ba675SRob Herring gpio2 = &gpio3; 27*724ba675SRob Herring gpio3 = &gpio4; 28*724ba675SRob Herring gpio4 = &gpio5; 29*724ba675SRob Herring gpio5 = &gpio6; 30*724ba675SRob Herring gpio6 = &gpio7; 31*724ba675SRob Herring i2c0 = &i2c1; 32*724ba675SRob Herring i2c1 = &i2c2; 33*724ba675SRob Herring i2c2 = &i2c3; 34*724ba675SRob Herring ipu0 = &ipu1; 35*724ba675SRob Herring mmc0 = &usdhc1; 36*724ba675SRob Herring mmc1 = &usdhc2; 37*724ba675SRob Herring mmc2 = &usdhc3; 38*724ba675SRob Herring mmc3 = &usdhc4; 39*724ba675SRob Herring serial0 = &uart1; 40*724ba675SRob Herring serial1 = &uart2; 41*724ba675SRob Herring serial2 = &uart3; 42*724ba675SRob Herring serial3 = &uart4; 43*724ba675SRob Herring serial4 = &uart5; 44*724ba675SRob Herring spi0 = &ecspi1; 45*724ba675SRob Herring spi1 = &ecspi2; 46*724ba675SRob Herring spi2 = &ecspi3; 47*724ba675SRob Herring spi3 = &ecspi4; 48*724ba675SRob Herring usb0 = &usbotg; 49*724ba675SRob Herring usb1 = &usbh1; 50*724ba675SRob Herring usb2 = &usbh2; 51*724ba675SRob Herring usb3 = &usbh3; 52*724ba675SRob Herring usbphy0 = &usbphy1; 53*724ba675SRob Herring usbphy1 = &usbphy2; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring clocks { 57*724ba675SRob Herring ckil { 58*724ba675SRob Herring compatible = "fixed-clock"; 59*724ba675SRob Herring #clock-cells = <0>; 60*724ba675SRob Herring clock-frequency = <32768>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring ckih1 { 64*724ba675SRob Herring compatible = "fixed-clock"; 65*724ba675SRob Herring #clock-cells = <0>; 66*724ba675SRob Herring clock-frequency = <0>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring osc { 70*724ba675SRob Herring compatible = "fixed-clock"; 71*724ba675SRob Herring #clock-cells = <0>; 72*724ba675SRob Herring clock-frequency = <24000000>; 73*724ba675SRob Herring }; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring ldb: ldb { 77*724ba675SRob Herring #address-cells = <1>; 78*724ba675SRob Herring #size-cells = <0>; 79*724ba675SRob Herring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 80*724ba675SRob Herring gpr = <&gpr>; 81*724ba675SRob Herring status = "disabled"; 82*724ba675SRob Herring 83*724ba675SRob Herring lvds-channel@0 { 84*724ba675SRob Herring #address-cells = <1>; 85*724ba675SRob Herring #size-cells = <0>; 86*724ba675SRob Herring reg = <0>; 87*724ba675SRob Herring status = "disabled"; 88*724ba675SRob Herring 89*724ba675SRob Herring port@0 { 90*724ba675SRob Herring reg = <0>; 91*724ba675SRob Herring 92*724ba675SRob Herring lvds0_mux_0: endpoint { 93*724ba675SRob Herring remote-endpoint = <&ipu1_di0_lvds0>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring port@1 { 98*724ba675SRob Herring reg = <1>; 99*724ba675SRob Herring 100*724ba675SRob Herring lvds0_mux_1: endpoint { 101*724ba675SRob Herring remote-endpoint = <&ipu1_di1_lvds0>; 102*724ba675SRob Herring }; 103*724ba675SRob Herring }; 104*724ba675SRob Herring }; 105*724ba675SRob Herring 106*724ba675SRob Herring lvds-channel@1 { 107*724ba675SRob Herring #address-cells = <1>; 108*724ba675SRob Herring #size-cells = <0>; 109*724ba675SRob Herring reg = <1>; 110*724ba675SRob Herring status = "disabled"; 111*724ba675SRob Herring 112*724ba675SRob Herring port@0 { 113*724ba675SRob Herring reg = <0>; 114*724ba675SRob Herring 115*724ba675SRob Herring lvds1_mux_0: endpoint { 116*724ba675SRob Herring remote-endpoint = <&ipu1_di0_lvds1>; 117*724ba675SRob Herring }; 118*724ba675SRob Herring }; 119*724ba675SRob Herring 120*724ba675SRob Herring port@1 { 121*724ba675SRob Herring reg = <1>; 122*724ba675SRob Herring 123*724ba675SRob Herring lvds1_mux_1: endpoint { 124*724ba675SRob Herring remote-endpoint = <&ipu1_di1_lvds1>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring }; 127*724ba675SRob Herring }; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring pmu: pmu { 131*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 132*724ba675SRob Herring interrupt-parent = <&gpc>; 133*724ba675SRob Herring interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring usbphynop1: usbphynop1 { 137*724ba675SRob Herring compatible = "usb-nop-xceiv"; 138*724ba675SRob Herring #phy-cells = <0>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring usbphynop2: usbphynop2 { 142*724ba675SRob Herring compatible = "usb-nop-xceiv"; 143*724ba675SRob Herring #phy-cells = <0>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring 146*724ba675SRob Herring soc: soc { 147*724ba675SRob Herring #address-cells = <1>; 148*724ba675SRob Herring #size-cells = <1>; 149*724ba675SRob Herring compatible = "simple-bus"; 150*724ba675SRob Herring interrupt-parent = <&gpc>; 151*724ba675SRob Herring ranges; 152*724ba675SRob Herring 153*724ba675SRob Herring dma_apbh: dma-controller@110000 { 154*724ba675SRob Herring compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 155*724ba675SRob Herring reg = <0x00110000 0x2000>; 156*724ba675SRob Herring interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 157*724ba675SRob Herring <0 13 IRQ_TYPE_LEVEL_HIGH>, 158*724ba675SRob Herring <0 13 IRQ_TYPE_LEVEL_HIGH>, 159*724ba675SRob Herring <0 13 IRQ_TYPE_LEVEL_HIGH>; 160*724ba675SRob Herring #dma-cells = <1>; 161*724ba675SRob Herring dma-channels = <4>; 162*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 163*724ba675SRob Herring }; 164*724ba675SRob Herring 165*724ba675SRob Herring gpmi: nand-controller@112000 { 166*724ba675SRob Herring compatible = "fsl,imx6q-gpmi-nand"; 167*724ba675SRob Herring reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 168*724ba675SRob Herring reg-names = "gpmi-nand", "bch"; 169*724ba675SRob Herring interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 170*724ba675SRob Herring interrupt-names = "bch"; 171*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 172*724ba675SRob Herring <&clks IMX6QDL_CLK_GPMI_APB>, 173*724ba675SRob Herring <&clks IMX6QDL_CLK_GPMI_BCH>, 174*724ba675SRob Herring <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 175*724ba675SRob Herring <&clks IMX6QDL_CLK_PER1_BCH>; 176*724ba675SRob Herring clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 177*724ba675SRob Herring "gpmi_bch_apb", "per1_bch"; 178*724ba675SRob Herring dmas = <&dma_apbh 0>; 179*724ba675SRob Herring dma-names = "rx-tx"; 180*724ba675SRob Herring status = "disabled"; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring hdmi: hdmi@120000 { 184*724ba675SRob Herring reg = <0x00120000 0x9000>; 185*724ba675SRob Herring interrupts = <0 115 0x04>; 186*724ba675SRob Herring gpr = <&gpr>; 187*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 188*724ba675SRob Herring <&clks IMX6QDL_CLK_HDMI_ISFR>; 189*724ba675SRob Herring clock-names = "iahb", "isfr"; 190*724ba675SRob Herring status = "disabled"; 191*724ba675SRob Herring 192*724ba675SRob Herring ports { 193*724ba675SRob Herring #address-cells = <1>; 194*724ba675SRob Herring #size-cells = <0>; 195*724ba675SRob Herring 196*724ba675SRob Herring port@0 { 197*724ba675SRob Herring reg = <0>; 198*724ba675SRob Herring 199*724ba675SRob Herring hdmi_mux_0: endpoint { 200*724ba675SRob Herring remote-endpoint = <&ipu1_di0_hdmi>; 201*724ba675SRob Herring }; 202*724ba675SRob Herring }; 203*724ba675SRob Herring 204*724ba675SRob Herring port@1 { 205*724ba675SRob Herring reg = <1>; 206*724ba675SRob Herring 207*724ba675SRob Herring hdmi_mux_1: endpoint { 208*724ba675SRob Herring remote-endpoint = <&ipu1_di1_hdmi>; 209*724ba675SRob Herring }; 210*724ba675SRob Herring }; 211*724ba675SRob Herring }; 212*724ba675SRob Herring }; 213*724ba675SRob Herring 214*724ba675SRob Herring gpu_3d: gpu@130000 { 215*724ba675SRob Herring compatible = "vivante,gc"; 216*724ba675SRob Herring reg = <0x00130000 0x4000>; 217*724ba675SRob Herring interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 218*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, 219*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU3D_CORE>, 220*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU3D_SHADER>; 221*724ba675SRob Herring clock-names = "bus", "core", "shader"; 222*724ba675SRob Herring power-domains = <&pd_pu>; 223*724ba675SRob Herring #cooling-cells = <2>; 224*724ba675SRob Herring }; 225*724ba675SRob Herring 226*724ba675SRob Herring gpu_2d: gpu@134000 { 227*724ba675SRob Herring compatible = "vivante,gc"; 228*724ba675SRob Herring reg = <0x00134000 0x4000>; 229*724ba675SRob Herring interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 230*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, 231*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU2D_CORE>; 232*724ba675SRob Herring clock-names = "bus", "core"; 233*724ba675SRob Herring power-domains = <&pd_pu>; 234*724ba675SRob Herring #cooling-cells = <2>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring timer@a00600 { 238*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 239*724ba675SRob Herring reg = <0x00a00600 0x20>; 240*724ba675SRob Herring interrupts = <1 13 0xf01>; 241*724ba675SRob Herring interrupt-parent = <&intc>; 242*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_TWD>; 243*724ba675SRob Herring }; 244*724ba675SRob Herring 245*724ba675SRob Herring intc: interrupt-controller@a01000 { 246*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 247*724ba675SRob Herring #interrupt-cells = <3>; 248*724ba675SRob Herring interrupt-controller; 249*724ba675SRob Herring reg = <0x00a01000 0x1000>, 250*724ba675SRob Herring <0x00a00100 0x100>; 251*724ba675SRob Herring interrupt-parent = <&intc>; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring L2: cache-controller@a02000 { 255*724ba675SRob Herring compatible = "arm,pl310-cache"; 256*724ba675SRob Herring reg = <0x00a02000 0x1000>; 257*724ba675SRob Herring interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 258*724ba675SRob Herring cache-unified; 259*724ba675SRob Herring cache-level = <2>; 260*724ba675SRob Herring arm,tag-latency = <4 2 3>; 261*724ba675SRob Herring arm,data-latency = <4 2 3>; 262*724ba675SRob Herring arm,shared-override; 263*724ba675SRob Herring }; 264*724ba675SRob Herring 265*724ba675SRob Herring pcie: pcie@1ffc000 { 266*724ba675SRob Herring compatible = "fsl,imx6q-pcie"; 267*724ba675SRob Herring reg = <0x01ffc000 0x04000>, 268*724ba675SRob Herring <0x01f00000 0x80000>; 269*724ba675SRob Herring reg-names = "dbi", "config"; 270*724ba675SRob Herring #address-cells = <3>; 271*724ba675SRob Herring #size-cells = <2>; 272*724ba675SRob Herring device_type = "pci"; 273*724ba675SRob Herring bus-range = <0x00 0xff>; 274*724ba675SRob Herring ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ 275*724ba675SRob Herring <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 276*724ba675SRob Herring num-lanes = <1>; 277*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 278*724ba675SRob Herring interrupt-names = "msi"; 279*724ba675SRob Herring #interrupt-cells = <1>; 280*724ba675SRob Herring interrupt-map-mask = <0 0 0 0x7>; 281*724ba675SRob Herring interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 282*724ba675SRob Herring <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 283*724ba675SRob Herring <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 284*724ba675SRob Herring <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 285*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 286*724ba675SRob Herring <&clks IMX6QDL_CLK_LVDS1_GATE>, 287*724ba675SRob Herring <&clks IMX6QDL_CLK_PCIE_REF_125M>; 288*724ba675SRob Herring clock-names = "pcie", "pcie_bus", "pcie_phy"; 289*724ba675SRob Herring status = "disabled"; 290*724ba675SRob Herring }; 291*724ba675SRob Herring 292*724ba675SRob Herring aips1: bus@2000000 { /* AIPS1 */ 293*724ba675SRob Herring compatible = "fsl,aips-bus", "simple-bus"; 294*724ba675SRob Herring #address-cells = <1>; 295*724ba675SRob Herring #size-cells = <1>; 296*724ba675SRob Herring reg = <0x02000000 0x100000>; 297*724ba675SRob Herring ranges; 298*724ba675SRob Herring 299*724ba675SRob Herring spba-bus@2000000 { 300*724ba675SRob Herring compatible = "fsl,spba-bus", "simple-bus"; 301*724ba675SRob Herring #address-cells = <1>; 302*724ba675SRob Herring #size-cells = <1>; 303*724ba675SRob Herring reg = <0x02000000 0x40000>; 304*724ba675SRob Herring ranges; 305*724ba675SRob Herring 306*724ba675SRob Herring spdif: spdif@2004000 { 307*724ba675SRob Herring compatible = "fsl,imx35-spdif"; 308*724ba675SRob Herring reg = <0x02004000 0x4000>; 309*724ba675SRob Herring interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 310*724ba675SRob Herring dmas = <&sdma 14 18 0>, 311*724ba675SRob Herring <&sdma 15 18 0>; 312*724ba675SRob Herring dma-names = "rx", "tx"; 313*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 314*724ba675SRob Herring <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 315*724ba675SRob Herring <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 316*724ba675SRob Herring <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 317*724ba675SRob Herring <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 318*724ba675SRob Herring clock-names = "core", "rxtx0", 319*724ba675SRob Herring "rxtx1", "rxtx2", 320*724ba675SRob Herring "rxtx3", "rxtx4", 321*724ba675SRob Herring "rxtx5", "rxtx6", 322*724ba675SRob Herring "rxtx7", "spba"; 323*724ba675SRob Herring status = "disabled"; 324*724ba675SRob Herring }; 325*724ba675SRob Herring 326*724ba675SRob Herring ecspi1: spi@2008000 { 327*724ba675SRob Herring #address-cells = <1>; 328*724ba675SRob Herring #size-cells = <0>; 329*724ba675SRob Herring compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 330*724ba675SRob Herring reg = <0x02008000 0x4000>; 331*724ba675SRob Herring interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 332*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ECSPI1>, 333*724ba675SRob Herring <&clks IMX6QDL_CLK_ECSPI1>; 334*724ba675SRob Herring clock-names = "ipg", "per"; 335*724ba675SRob Herring dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 336*724ba675SRob Herring dma-names = "rx", "tx"; 337*724ba675SRob Herring status = "disabled"; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring ecspi2: spi@200c000 { 341*724ba675SRob Herring #address-cells = <1>; 342*724ba675SRob Herring #size-cells = <0>; 343*724ba675SRob Herring compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 344*724ba675SRob Herring reg = <0x0200c000 0x4000>; 345*724ba675SRob Herring interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 346*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ECSPI2>, 347*724ba675SRob Herring <&clks IMX6QDL_CLK_ECSPI2>; 348*724ba675SRob Herring clock-names = "ipg", "per"; 349*724ba675SRob Herring dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 350*724ba675SRob Herring dma-names = "rx", "tx"; 351*724ba675SRob Herring status = "disabled"; 352*724ba675SRob Herring }; 353*724ba675SRob Herring 354*724ba675SRob Herring ecspi3: spi@2010000 { 355*724ba675SRob Herring #address-cells = <1>; 356*724ba675SRob Herring #size-cells = <0>; 357*724ba675SRob Herring compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 358*724ba675SRob Herring reg = <0x02010000 0x4000>; 359*724ba675SRob Herring interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 360*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ECSPI3>, 361*724ba675SRob Herring <&clks IMX6QDL_CLK_ECSPI3>; 362*724ba675SRob Herring clock-names = "ipg", "per"; 363*724ba675SRob Herring dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 364*724ba675SRob Herring dma-names = "rx", "tx"; 365*724ba675SRob Herring status = "disabled"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring ecspi4: spi@2014000 { 369*724ba675SRob Herring #address-cells = <1>; 370*724ba675SRob Herring #size-cells = <0>; 371*724ba675SRob Herring compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 372*724ba675SRob Herring reg = <0x02014000 0x4000>; 373*724ba675SRob Herring interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 374*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ECSPI4>, 375*724ba675SRob Herring <&clks IMX6QDL_CLK_ECSPI4>; 376*724ba675SRob Herring clock-names = "ipg", "per"; 377*724ba675SRob Herring dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 378*724ba675SRob Herring dma-names = "rx", "tx"; 379*724ba675SRob Herring status = "disabled"; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring uart1: serial@2020000 { 383*724ba675SRob Herring compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 384*724ba675SRob Herring reg = <0x02020000 0x4000>; 385*724ba675SRob Herring interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 386*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_UART_IPG>, 387*724ba675SRob Herring <&clks IMX6QDL_CLK_UART_SERIAL>; 388*724ba675SRob Herring clock-names = "ipg", "per"; 389*724ba675SRob Herring dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 390*724ba675SRob Herring dma-names = "rx", "tx"; 391*724ba675SRob Herring status = "disabled"; 392*724ba675SRob Herring }; 393*724ba675SRob Herring 394*724ba675SRob Herring esai: esai@2024000 { 395*724ba675SRob Herring #sound-dai-cells = <0>; 396*724ba675SRob Herring compatible = "fsl,imx35-esai"; 397*724ba675SRob Herring reg = <0x02024000 0x4000>; 398*724ba675SRob Herring interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 399*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 400*724ba675SRob Herring <&clks IMX6QDL_CLK_ESAI_MEM>, 401*724ba675SRob Herring <&clks IMX6QDL_CLK_ESAI_EXTAL>, 402*724ba675SRob Herring <&clks IMX6QDL_CLK_ESAI_IPG>, 403*724ba675SRob Herring <&clks IMX6QDL_CLK_SPBA>; 404*724ba675SRob Herring clock-names = "core", "mem", "extal", "fsys", "spba"; 405*724ba675SRob Herring dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 406*724ba675SRob Herring dma-names = "rx", "tx"; 407*724ba675SRob Herring status = "disabled"; 408*724ba675SRob Herring }; 409*724ba675SRob Herring 410*724ba675SRob Herring ssi1: ssi@2028000 { 411*724ba675SRob Herring #sound-dai-cells = <0>; 412*724ba675SRob Herring compatible = "fsl,imx6q-ssi", 413*724ba675SRob Herring "fsl,imx51-ssi"; 414*724ba675SRob Herring reg = <0x02028000 0x4000>; 415*724ba675SRob Herring interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 416*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 417*724ba675SRob Herring <&clks IMX6QDL_CLK_SSI1>; 418*724ba675SRob Herring clock-names = "ipg", "baud"; 419*724ba675SRob Herring dmas = <&sdma 37 1 0>, 420*724ba675SRob Herring <&sdma 38 1 0>; 421*724ba675SRob Herring dma-names = "rx", "tx"; 422*724ba675SRob Herring fsl,fifo-depth = <15>; 423*724ba675SRob Herring status = "disabled"; 424*724ba675SRob Herring }; 425*724ba675SRob Herring 426*724ba675SRob Herring ssi2: ssi@202c000 { 427*724ba675SRob Herring #sound-dai-cells = <0>; 428*724ba675SRob Herring compatible = "fsl,imx6q-ssi", 429*724ba675SRob Herring "fsl,imx51-ssi"; 430*724ba675SRob Herring reg = <0x0202c000 0x4000>; 431*724ba675SRob Herring interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 432*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 433*724ba675SRob Herring <&clks IMX6QDL_CLK_SSI2>; 434*724ba675SRob Herring clock-names = "ipg", "baud"; 435*724ba675SRob Herring dmas = <&sdma 41 1 0>, 436*724ba675SRob Herring <&sdma 42 1 0>; 437*724ba675SRob Herring dma-names = "rx", "tx"; 438*724ba675SRob Herring fsl,fifo-depth = <15>; 439*724ba675SRob Herring status = "disabled"; 440*724ba675SRob Herring }; 441*724ba675SRob Herring 442*724ba675SRob Herring ssi3: ssi@2030000 { 443*724ba675SRob Herring #sound-dai-cells = <0>; 444*724ba675SRob Herring compatible = "fsl,imx6q-ssi", 445*724ba675SRob Herring "fsl,imx51-ssi"; 446*724ba675SRob Herring reg = <0x02030000 0x4000>; 447*724ba675SRob Herring interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 448*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 449*724ba675SRob Herring <&clks IMX6QDL_CLK_SSI3>; 450*724ba675SRob Herring clock-names = "ipg", "baud"; 451*724ba675SRob Herring dmas = <&sdma 45 1 0>, 452*724ba675SRob Herring <&sdma 46 1 0>; 453*724ba675SRob Herring dma-names = "rx", "tx"; 454*724ba675SRob Herring fsl,fifo-depth = <15>; 455*724ba675SRob Herring status = "disabled"; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring asrc: asrc@2034000 { 459*724ba675SRob Herring compatible = "fsl,imx53-asrc"; 460*724ba675SRob Herring reg = <0x02034000 0x4000>; 461*724ba675SRob Herring interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 462*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 463*724ba675SRob Herring <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 464*724ba675SRob Herring <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 465*724ba675SRob Herring <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 466*724ba675SRob Herring <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 467*724ba675SRob Herring <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 468*724ba675SRob Herring <&clks IMX6QDL_CLK_SPBA>; 469*724ba675SRob Herring clock-names = "mem", "ipg", "asrck_0", 470*724ba675SRob Herring "asrck_1", "asrck_2", "asrck_3", "asrck_4", 471*724ba675SRob Herring "asrck_5", "asrck_6", "asrck_7", "asrck_8", 472*724ba675SRob Herring "asrck_9", "asrck_a", "asrck_b", "asrck_c", 473*724ba675SRob Herring "asrck_d", "asrck_e", "asrck_f", "spba"; 474*724ba675SRob Herring dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 475*724ba675SRob Herring <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 476*724ba675SRob Herring dma-names = "rxa", "rxb", "rxc", 477*724ba675SRob Herring "txa", "txb", "txc"; 478*724ba675SRob Herring fsl,asrc-rate = <48000>; 479*724ba675SRob Herring fsl,asrc-width = <16>; 480*724ba675SRob Herring status = "okay"; 481*724ba675SRob Herring }; 482*724ba675SRob Herring 483*724ba675SRob Herring spba-bus@203c000 { 484*724ba675SRob Herring reg = <0x0203c000 0x4000>; 485*724ba675SRob Herring }; 486*724ba675SRob Herring }; 487*724ba675SRob Herring 488*724ba675SRob Herring vpu: vpu@2040000 { 489*724ba675SRob Herring compatible = "cnm,coda960"; 490*724ba675SRob Herring reg = <0x02040000 0x3c000>; 491*724ba675SRob Herring interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 492*724ba675SRob Herring <0 3 IRQ_TYPE_LEVEL_HIGH>; 493*724ba675SRob Herring interrupt-names = "bit", "jpeg"; 494*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 495*724ba675SRob Herring <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 496*724ba675SRob Herring clock-names = "per", "ahb"; 497*724ba675SRob Herring power-domains = <&pd_pu>; 498*724ba675SRob Herring resets = <&src 1>; 499*724ba675SRob Herring iram = <&ocram>; 500*724ba675SRob Herring }; 501*724ba675SRob Herring 502*724ba675SRob Herring aipstz@207c000 { /* AIPSTZ1 */ 503*724ba675SRob Herring reg = <0x0207c000 0x4000>; 504*724ba675SRob Herring }; 505*724ba675SRob Herring 506*724ba675SRob Herring pwm1: pwm@2080000 { 507*724ba675SRob Herring #pwm-cells = <3>; 508*724ba675SRob Herring compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 509*724ba675SRob Herring reg = <0x02080000 0x4000>; 510*724ba675SRob Herring interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 511*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>, 512*724ba675SRob Herring <&clks IMX6QDL_CLK_PWM1>; 513*724ba675SRob Herring clock-names = "ipg", "per"; 514*724ba675SRob Herring status = "disabled"; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring pwm2: pwm@2084000 { 518*724ba675SRob Herring #pwm-cells = <3>; 519*724ba675SRob Herring compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 520*724ba675SRob Herring reg = <0x02084000 0x4000>; 521*724ba675SRob Herring interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 522*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>, 523*724ba675SRob Herring <&clks IMX6QDL_CLK_PWM2>; 524*724ba675SRob Herring clock-names = "ipg", "per"; 525*724ba675SRob Herring status = "disabled"; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring pwm3: pwm@2088000 { 529*724ba675SRob Herring #pwm-cells = <3>; 530*724ba675SRob Herring compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 531*724ba675SRob Herring reg = <0x02088000 0x4000>; 532*724ba675SRob Herring interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 533*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>, 534*724ba675SRob Herring <&clks IMX6QDL_CLK_PWM3>; 535*724ba675SRob Herring clock-names = "ipg", "per"; 536*724ba675SRob Herring status = "disabled"; 537*724ba675SRob Herring }; 538*724ba675SRob Herring 539*724ba675SRob Herring pwm4: pwm@208c000 { 540*724ba675SRob Herring #pwm-cells = <3>; 541*724ba675SRob Herring compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 542*724ba675SRob Herring reg = <0x0208c000 0x4000>; 543*724ba675SRob Herring interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 544*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>, 545*724ba675SRob Herring <&clks IMX6QDL_CLK_PWM4>; 546*724ba675SRob Herring clock-names = "ipg", "per"; 547*724ba675SRob Herring status = "disabled"; 548*724ba675SRob Herring }; 549*724ba675SRob Herring 550*724ba675SRob Herring can1: can@2090000 { 551*724ba675SRob Herring compatible = "fsl,imx6q-flexcan"; 552*724ba675SRob Herring reg = <0x02090000 0x4000>; 553*724ba675SRob Herring interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 554*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 555*724ba675SRob Herring <&clks IMX6QDL_CLK_CAN1_SERIAL>; 556*724ba675SRob Herring clock-names = "ipg", "per"; 557*724ba675SRob Herring fsl,stop-mode = <&gpr 0x34 28>; 558*724ba675SRob Herring status = "disabled"; 559*724ba675SRob Herring }; 560*724ba675SRob Herring 561*724ba675SRob Herring can2: can@2094000 { 562*724ba675SRob Herring compatible = "fsl,imx6q-flexcan"; 563*724ba675SRob Herring reg = <0x02094000 0x4000>; 564*724ba675SRob Herring interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 565*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 566*724ba675SRob Herring <&clks IMX6QDL_CLK_CAN2_SERIAL>; 567*724ba675SRob Herring clock-names = "ipg", "per"; 568*724ba675SRob Herring fsl,stop-mode = <&gpr 0x34 29>; 569*724ba675SRob Herring status = "disabled"; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring gpt: timer@2098000 { 573*724ba675SRob Herring compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 574*724ba675SRob Herring reg = <0x02098000 0x4000>; 575*724ba675SRob Herring interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 576*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 577*724ba675SRob Herring <&clks IMX6QDL_CLK_GPT_IPG_PER>, 578*724ba675SRob Herring <&clks IMX6QDL_CLK_GPT_3M>; 579*724ba675SRob Herring clock-names = "ipg", "per", "osc_per"; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring gpio1: gpio@209c000 { 583*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 584*724ba675SRob Herring reg = <0x0209c000 0x4000>; 585*724ba675SRob Herring interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 586*724ba675SRob Herring <0 67 IRQ_TYPE_LEVEL_HIGH>; 587*724ba675SRob Herring gpio-controller; 588*724ba675SRob Herring #gpio-cells = <2>; 589*724ba675SRob Herring interrupt-controller; 590*724ba675SRob Herring #interrupt-cells = <2>; 591*724ba675SRob Herring }; 592*724ba675SRob Herring 593*724ba675SRob Herring gpio2: gpio@20a0000 { 594*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 595*724ba675SRob Herring reg = <0x020a0000 0x4000>; 596*724ba675SRob Herring interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 597*724ba675SRob Herring <0 69 IRQ_TYPE_LEVEL_HIGH>; 598*724ba675SRob Herring gpio-controller; 599*724ba675SRob Herring #gpio-cells = <2>; 600*724ba675SRob Herring interrupt-controller; 601*724ba675SRob Herring #interrupt-cells = <2>; 602*724ba675SRob Herring }; 603*724ba675SRob Herring 604*724ba675SRob Herring gpio3: gpio@20a4000 { 605*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 606*724ba675SRob Herring reg = <0x020a4000 0x4000>; 607*724ba675SRob Herring interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 608*724ba675SRob Herring <0 71 IRQ_TYPE_LEVEL_HIGH>; 609*724ba675SRob Herring gpio-controller; 610*724ba675SRob Herring #gpio-cells = <2>; 611*724ba675SRob Herring interrupt-controller; 612*724ba675SRob Herring #interrupt-cells = <2>; 613*724ba675SRob Herring }; 614*724ba675SRob Herring 615*724ba675SRob Herring gpio4: gpio@20a8000 { 616*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 617*724ba675SRob Herring reg = <0x020a8000 0x4000>; 618*724ba675SRob Herring interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 619*724ba675SRob Herring <0 73 IRQ_TYPE_LEVEL_HIGH>; 620*724ba675SRob Herring gpio-controller; 621*724ba675SRob Herring #gpio-cells = <2>; 622*724ba675SRob Herring interrupt-controller; 623*724ba675SRob Herring #interrupt-cells = <2>; 624*724ba675SRob Herring }; 625*724ba675SRob Herring 626*724ba675SRob Herring gpio5: gpio@20ac000 { 627*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 628*724ba675SRob Herring reg = <0x020ac000 0x4000>; 629*724ba675SRob Herring interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 630*724ba675SRob Herring <0 75 IRQ_TYPE_LEVEL_HIGH>; 631*724ba675SRob Herring gpio-controller; 632*724ba675SRob Herring #gpio-cells = <2>; 633*724ba675SRob Herring interrupt-controller; 634*724ba675SRob Herring #interrupt-cells = <2>; 635*724ba675SRob Herring }; 636*724ba675SRob Herring 637*724ba675SRob Herring gpio6: gpio@20b0000 { 638*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 639*724ba675SRob Herring reg = <0x020b0000 0x4000>; 640*724ba675SRob Herring interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 641*724ba675SRob Herring <0 77 IRQ_TYPE_LEVEL_HIGH>; 642*724ba675SRob Herring gpio-controller; 643*724ba675SRob Herring #gpio-cells = <2>; 644*724ba675SRob Herring interrupt-controller; 645*724ba675SRob Herring #interrupt-cells = <2>; 646*724ba675SRob Herring }; 647*724ba675SRob Herring 648*724ba675SRob Herring gpio7: gpio@20b4000 { 649*724ba675SRob Herring compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 650*724ba675SRob Herring reg = <0x020b4000 0x4000>; 651*724ba675SRob Herring interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 652*724ba675SRob Herring <0 79 IRQ_TYPE_LEVEL_HIGH>; 653*724ba675SRob Herring gpio-controller; 654*724ba675SRob Herring #gpio-cells = <2>; 655*724ba675SRob Herring interrupt-controller; 656*724ba675SRob Herring #interrupt-cells = <2>; 657*724ba675SRob Herring }; 658*724ba675SRob Herring 659*724ba675SRob Herring kpp: keypad@20b8000 { 660*724ba675SRob Herring compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 661*724ba675SRob Herring reg = <0x020b8000 0x4000>; 662*724ba675SRob Herring interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 663*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>; 664*724ba675SRob Herring status = "disabled"; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring wdog1: watchdog@20bc000 { 668*724ba675SRob Herring compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 669*724ba675SRob Herring reg = <0x020bc000 0x4000>; 670*724ba675SRob Herring interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 671*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>; 672*724ba675SRob Herring }; 673*724ba675SRob Herring 674*724ba675SRob Herring wdog2: watchdog@20c0000 { 675*724ba675SRob Herring compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 676*724ba675SRob Herring reg = <0x020c0000 0x4000>; 677*724ba675SRob Herring interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 678*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>; 679*724ba675SRob Herring status = "disabled"; 680*724ba675SRob Herring }; 681*724ba675SRob Herring 682*724ba675SRob Herring clks: clock-controller@20c4000 { 683*724ba675SRob Herring compatible = "fsl,imx6q-ccm"; 684*724ba675SRob Herring reg = <0x020c4000 0x4000>; 685*724ba675SRob Herring interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 686*724ba675SRob Herring <0 88 IRQ_TYPE_LEVEL_HIGH>; 687*724ba675SRob Herring #clock-cells = <1>; 688*724ba675SRob Herring }; 689*724ba675SRob Herring 690*724ba675SRob Herring anatop: anatop@20c8000 { 691*724ba675SRob Herring compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; 692*724ba675SRob Herring reg = <0x020c8000 0x1000>; 693*724ba675SRob Herring interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 694*724ba675SRob Herring <0 54 IRQ_TYPE_LEVEL_HIGH>, 695*724ba675SRob Herring <0 127 IRQ_TYPE_LEVEL_HIGH>; 696*724ba675SRob Herring 697*724ba675SRob Herring reg_vdd1p1: regulator-1p1 { 698*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 699*724ba675SRob Herring regulator-name = "vdd1p1"; 700*724ba675SRob Herring regulator-min-microvolt = <1000000>; 701*724ba675SRob Herring regulator-max-microvolt = <1200000>; 702*724ba675SRob Herring regulator-always-on; 703*724ba675SRob Herring anatop-reg-offset = <0x110>; 704*724ba675SRob Herring anatop-vol-bit-shift = <8>; 705*724ba675SRob Herring anatop-vol-bit-width = <5>; 706*724ba675SRob Herring anatop-min-bit-val = <4>; 707*724ba675SRob Herring anatop-min-voltage = <800000>; 708*724ba675SRob Herring anatop-max-voltage = <1375000>; 709*724ba675SRob Herring anatop-enable-bit = <0>; 710*724ba675SRob Herring }; 711*724ba675SRob Herring 712*724ba675SRob Herring reg_vdd3p0: regulator-3p0 { 713*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 714*724ba675SRob Herring regulator-name = "vdd3p0"; 715*724ba675SRob Herring regulator-min-microvolt = <2800000>; 716*724ba675SRob Herring regulator-max-microvolt = <3150000>; 717*724ba675SRob Herring regulator-always-on; 718*724ba675SRob Herring anatop-reg-offset = <0x120>; 719*724ba675SRob Herring anatop-vol-bit-shift = <8>; 720*724ba675SRob Herring anatop-vol-bit-width = <5>; 721*724ba675SRob Herring anatop-min-bit-val = <0>; 722*724ba675SRob Herring anatop-min-voltage = <2625000>; 723*724ba675SRob Herring anatop-max-voltage = <3400000>; 724*724ba675SRob Herring anatop-enable-bit = <0>; 725*724ba675SRob Herring }; 726*724ba675SRob Herring 727*724ba675SRob Herring reg_vdd2p5: regulator-2p5 { 728*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 729*724ba675SRob Herring regulator-name = "vdd2p5"; 730*724ba675SRob Herring regulator-min-microvolt = <2250000>; 731*724ba675SRob Herring regulator-max-microvolt = <2750000>; 732*724ba675SRob Herring regulator-always-on; 733*724ba675SRob Herring anatop-reg-offset = <0x130>; 734*724ba675SRob Herring anatop-vol-bit-shift = <8>; 735*724ba675SRob Herring anatop-vol-bit-width = <5>; 736*724ba675SRob Herring anatop-min-bit-val = <0>; 737*724ba675SRob Herring anatop-min-voltage = <2100000>; 738*724ba675SRob Herring anatop-max-voltage = <2875000>; 739*724ba675SRob Herring anatop-enable-bit = <0>; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring reg_arm: regulator-vddcore { 743*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 744*724ba675SRob Herring regulator-name = "vddarm"; 745*724ba675SRob Herring regulator-min-microvolt = <725000>; 746*724ba675SRob Herring regulator-max-microvolt = <1450000>; 747*724ba675SRob Herring regulator-always-on; 748*724ba675SRob Herring anatop-reg-offset = <0x140>; 749*724ba675SRob Herring anatop-vol-bit-shift = <0>; 750*724ba675SRob Herring anatop-vol-bit-width = <5>; 751*724ba675SRob Herring anatop-delay-reg-offset = <0x170>; 752*724ba675SRob Herring anatop-delay-bit-shift = <24>; 753*724ba675SRob Herring anatop-delay-bit-width = <2>; 754*724ba675SRob Herring anatop-min-bit-val = <1>; 755*724ba675SRob Herring anatop-min-voltage = <725000>; 756*724ba675SRob Herring anatop-max-voltage = <1450000>; 757*724ba675SRob Herring }; 758*724ba675SRob Herring 759*724ba675SRob Herring reg_pu: regulator-vddpu { 760*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 761*724ba675SRob Herring regulator-name = "vddpu"; 762*724ba675SRob Herring regulator-min-microvolt = <725000>; 763*724ba675SRob Herring regulator-max-microvolt = <1450000>; 764*724ba675SRob Herring regulator-enable-ramp-delay = <380>; 765*724ba675SRob Herring anatop-reg-offset = <0x140>; 766*724ba675SRob Herring anatop-vol-bit-shift = <9>; 767*724ba675SRob Herring anatop-vol-bit-width = <5>; 768*724ba675SRob Herring anatop-delay-reg-offset = <0x170>; 769*724ba675SRob Herring anatop-delay-bit-shift = <26>; 770*724ba675SRob Herring anatop-delay-bit-width = <2>; 771*724ba675SRob Herring anatop-min-bit-val = <1>; 772*724ba675SRob Herring anatop-min-voltage = <725000>; 773*724ba675SRob Herring anatop-max-voltage = <1450000>; 774*724ba675SRob Herring }; 775*724ba675SRob Herring 776*724ba675SRob Herring reg_soc: regulator-vddsoc { 777*724ba675SRob Herring compatible = "fsl,anatop-regulator"; 778*724ba675SRob Herring regulator-name = "vddsoc"; 779*724ba675SRob Herring regulator-min-microvolt = <725000>; 780*724ba675SRob Herring regulator-max-microvolt = <1450000>; 781*724ba675SRob Herring regulator-always-on; 782*724ba675SRob Herring anatop-reg-offset = <0x140>; 783*724ba675SRob Herring anatop-vol-bit-shift = <18>; 784*724ba675SRob Herring anatop-vol-bit-width = <5>; 785*724ba675SRob Herring anatop-delay-reg-offset = <0x170>; 786*724ba675SRob Herring anatop-delay-bit-shift = <28>; 787*724ba675SRob Herring anatop-delay-bit-width = <2>; 788*724ba675SRob Herring anatop-min-bit-val = <1>; 789*724ba675SRob Herring anatop-min-voltage = <725000>; 790*724ba675SRob Herring anatop-max-voltage = <1450000>; 791*724ba675SRob Herring }; 792*724ba675SRob Herring 793*724ba675SRob Herring tempmon: tempmon { 794*724ba675SRob Herring compatible = "fsl,imx6q-tempmon"; 795*724ba675SRob Herring interrupt-parent = <&gpc>; 796*724ba675SRob Herring interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 797*724ba675SRob Herring fsl,tempmon = <&anatop>; 798*724ba675SRob Herring nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 799*724ba675SRob Herring nvmem-cell-names = "calib", "temp_grade"; 800*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 801*724ba675SRob Herring #thermal-sensor-cells = <0>; 802*724ba675SRob Herring }; 803*724ba675SRob Herring }; 804*724ba675SRob Herring 805*724ba675SRob Herring usbphy1: usbphy@20c9000 { 806*724ba675SRob Herring compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 807*724ba675SRob Herring reg = <0x020c9000 0x1000>; 808*724ba675SRob Herring interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 809*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBPHY1>; 810*724ba675SRob Herring fsl,anatop = <&anatop>; 811*724ba675SRob Herring }; 812*724ba675SRob Herring 813*724ba675SRob Herring usbphy2: usbphy@20ca000 { 814*724ba675SRob Herring compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 815*724ba675SRob Herring reg = <0x020ca000 0x1000>; 816*724ba675SRob Herring interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 817*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBPHY2>; 818*724ba675SRob Herring fsl,anatop = <&anatop>; 819*724ba675SRob Herring }; 820*724ba675SRob Herring 821*724ba675SRob Herring snvs: snvs@20cc000 { 822*724ba675SRob Herring compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 823*724ba675SRob Herring reg = <0x020cc000 0x4000>; 824*724ba675SRob Herring 825*724ba675SRob Herring snvs_rtc: snvs-rtc-lp { 826*724ba675SRob Herring compatible = "fsl,sec-v4.0-mon-rtc-lp"; 827*724ba675SRob Herring regmap = <&snvs>; 828*724ba675SRob Herring offset = <0x34>; 829*724ba675SRob Herring interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 830*724ba675SRob Herring <0 20 IRQ_TYPE_LEVEL_HIGH>; 831*724ba675SRob Herring }; 832*724ba675SRob Herring 833*724ba675SRob Herring snvs_poweroff: snvs-poweroff { 834*724ba675SRob Herring compatible = "syscon-poweroff"; 835*724ba675SRob Herring regmap = <&snvs>; 836*724ba675SRob Herring offset = <0x38>; 837*724ba675SRob Herring value = <0x60>; 838*724ba675SRob Herring mask = <0x60>; 839*724ba675SRob Herring status = "disabled"; 840*724ba675SRob Herring }; 841*724ba675SRob Herring 842*724ba675SRob Herring snvs_pwrkey: snvs-powerkey { 843*724ba675SRob Herring compatible = "fsl,sec-v4.0-pwrkey"; 844*724ba675SRob Herring regmap = <&snvs>; 845*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 846*724ba675SRob Herring linux,keycode = <KEY_POWER>; 847*724ba675SRob Herring wakeup-source; 848*724ba675SRob Herring status = "disabled"; 849*724ba675SRob Herring }; 850*724ba675SRob Herring 851*724ba675SRob Herring snvs_lpgpr: snvs-lpgpr { 852*724ba675SRob Herring compatible = "fsl,imx6q-snvs-lpgpr"; 853*724ba675SRob Herring }; 854*724ba675SRob Herring }; 855*724ba675SRob Herring 856*724ba675SRob Herring epit1: epit@20d0000 { /* EPIT1 */ 857*724ba675SRob Herring reg = <0x020d0000 0x4000>; 858*724ba675SRob Herring interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 859*724ba675SRob Herring }; 860*724ba675SRob Herring 861*724ba675SRob Herring epit2: epit@20d4000 { /* EPIT2 */ 862*724ba675SRob Herring reg = <0x020d4000 0x4000>; 863*724ba675SRob Herring interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 864*724ba675SRob Herring }; 865*724ba675SRob Herring 866*724ba675SRob Herring src: reset-controller@20d8000 { 867*724ba675SRob Herring compatible = "fsl,imx6q-src", "fsl,imx51-src"; 868*724ba675SRob Herring reg = <0x020d8000 0x4000>; 869*724ba675SRob Herring interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 870*724ba675SRob Herring <0 96 IRQ_TYPE_LEVEL_HIGH>; 871*724ba675SRob Herring #reset-cells = <1>; 872*724ba675SRob Herring }; 873*724ba675SRob Herring 874*724ba675SRob Herring gpc: gpc@20dc000 { 875*724ba675SRob Herring compatible = "fsl,imx6q-gpc"; 876*724ba675SRob Herring reg = <0x020dc000 0x4000>; 877*724ba675SRob Herring interrupt-controller; 878*724ba675SRob Herring #interrupt-cells = <3>; 879*724ba675SRob Herring interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 880*724ba675SRob Herring interrupt-parent = <&intc>; 881*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>; 882*724ba675SRob Herring clock-names = "ipg"; 883*724ba675SRob Herring 884*724ba675SRob Herring pgc { 885*724ba675SRob Herring #address-cells = <1>; 886*724ba675SRob Herring #size-cells = <0>; 887*724ba675SRob Herring 888*724ba675SRob Herring power-domain@0 { 889*724ba675SRob Herring reg = <0>; 890*724ba675SRob Herring #power-domain-cells = <0>; 891*724ba675SRob Herring }; 892*724ba675SRob Herring pd_pu: power-domain@1 { 893*724ba675SRob Herring reg = <1>; 894*724ba675SRob Herring #power-domain-cells = <0>; 895*724ba675SRob Herring power-supply = <®_pu>; 896*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 897*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU3D_SHADER>, 898*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU2D_CORE>, 899*724ba675SRob Herring <&clks IMX6QDL_CLK_GPU2D_AXI>, 900*724ba675SRob Herring <&clks IMX6QDL_CLK_OPENVG_AXI>, 901*724ba675SRob Herring <&clks IMX6QDL_CLK_VPU_AXI>; 902*724ba675SRob Herring }; 903*724ba675SRob Herring }; 904*724ba675SRob Herring }; 905*724ba675SRob Herring 906*724ba675SRob Herring gpr: iomuxc-gpr@20e0000 { 907*724ba675SRob Herring compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 908*724ba675SRob Herring reg = <0x20e0000 0x38>; 909*724ba675SRob Herring 910*724ba675SRob Herring mux: mux-controller { 911*724ba675SRob Herring compatible = "mmio-mux"; 912*724ba675SRob Herring #mux-control-cells = <1>; 913*724ba675SRob Herring }; 914*724ba675SRob Herring }; 915*724ba675SRob Herring 916*724ba675SRob Herring iomuxc: pinctrl@20e0000 { 917*724ba675SRob Herring compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 918*724ba675SRob Herring reg = <0x20e0000 0x4000>; 919*724ba675SRob Herring }; 920*724ba675SRob Herring 921*724ba675SRob Herring dcic1: dcic@20e4000 { 922*724ba675SRob Herring reg = <0x020e4000 0x4000>; 923*724ba675SRob Herring interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 924*724ba675SRob Herring }; 925*724ba675SRob Herring 926*724ba675SRob Herring dcic2: dcic@20e8000 { 927*724ba675SRob Herring reg = <0x020e8000 0x4000>; 928*724ba675SRob Herring interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 929*724ba675SRob Herring }; 930*724ba675SRob Herring 931*724ba675SRob Herring sdma: dma-controller@20ec000 { 932*724ba675SRob Herring compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 933*724ba675SRob Herring reg = <0x020ec000 0x4000>; 934*724ba675SRob Herring interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 935*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPG>, 936*724ba675SRob Herring <&clks IMX6QDL_CLK_SDMA>; 937*724ba675SRob Herring clock-names = "ipg", "ahb"; 938*724ba675SRob Herring #dma-cells = <3>; 939*724ba675SRob Herring fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 940*724ba675SRob Herring }; 941*724ba675SRob Herring }; 942*724ba675SRob Herring 943*724ba675SRob Herring aips2: bus@2100000 { /* AIPS2 */ 944*724ba675SRob Herring compatible = "fsl,aips-bus", "simple-bus"; 945*724ba675SRob Herring #address-cells = <1>; 946*724ba675SRob Herring #size-cells = <1>; 947*724ba675SRob Herring reg = <0x02100000 0x100000>; 948*724ba675SRob Herring ranges; 949*724ba675SRob Herring 950*724ba675SRob Herring crypto: crypto@2100000 { 951*724ba675SRob Herring compatible = "fsl,sec-v4.0"; 952*724ba675SRob Herring #address-cells = <1>; 953*724ba675SRob Herring #size-cells = <1>; 954*724ba675SRob Herring reg = <0x2100000 0x10000>; 955*724ba675SRob Herring ranges = <0 0x2100000 0x10000>; 956*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 957*724ba675SRob Herring <&clks IMX6QDL_CLK_CAAM_ACLK>, 958*724ba675SRob Herring <&clks IMX6QDL_CLK_CAAM_IPG>, 959*724ba675SRob Herring <&clks IMX6QDL_CLK_EIM_SLOW>; 960*724ba675SRob Herring clock-names = "mem", "aclk", "ipg", "emi_slow"; 961*724ba675SRob Herring 962*724ba675SRob Herring sec_jr0: jr@1000 { 963*724ba675SRob Herring compatible = "fsl,sec-v4.0-job-ring"; 964*724ba675SRob Herring reg = <0x1000 0x1000>; 965*724ba675SRob Herring interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 966*724ba675SRob Herring }; 967*724ba675SRob Herring 968*724ba675SRob Herring sec_jr1: jr@2000 { 969*724ba675SRob Herring compatible = "fsl,sec-v4.0-job-ring"; 970*724ba675SRob Herring reg = <0x2000 0x1000>; 971*724ba675SRob Herring interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 972*724ba675SRob Herring }; 973*724ba675SRob Herring }; 974*724ba675SRob Herring 975*724ba675SRob Herring aipstz@217c000 { /* AIPSTZ2 */ 976*724ba675SRob Herring reg = <0x0217c000 0x4000>; 977*724ba675SRob Herring }; 978*724ba675SRob Herring 979*724ba675SRob Herring usbotg: usb@2184000 { 980*724ba675SRob Herring compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 981*724ba675SRob Herring reg = <0x02184000 0x200>; 982*724ba675SRob Herring interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 983*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBOH3>; 984*724ba675SRob Herring fsl,usbphy = <&usbphy1>; 985*724ba675SRob Herring fsl,usbmisc = <&usbmisc 0>; 986*724ba675SRob Herring ahb-burst-config = <0x0>; 987*724ba675SRob Herring tx-burst-size-dword = <0x10>; 988*724ba675SRob Herring rx-burst-size-dword = <0x10>; 989*724ba675SRob Herring status = "disabled"; 990*724ba675SRob Herring }; 991*724ba675SRob Herring 992*724ba675SRob Herring usbh1: usb@2184200 { 993*724ba675SRob Herring compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 994*724ba675SRob Herring reg = <0x02184200 0x200>; 995*724ba675SRob Herring interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 996*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBOH3>; 997*724ba675SRob Herring fsl,usbphy = <&usbphy2>; 998*724ba675SRob Herring fsl,usbmisc = <&usbmisc 1>; 999*724ba675SRob Herring dr_mode = "host"; 1000*724ba675SRob Herring ahb-burst-config = <0x0>; 1001*724ba675SRob Herring tx-burst-size-dword = <0x10>; 1002*724ba675SRob Herring rx-burst-size-dword = <0x10>; 1003*724ba675SRob Herring status = "disabled"; 1004*724ba675SRob Herring }; 1005*724ba675SRob Herring 1006*724ba675SRob Herring usbh2: usb@2184400 { 1007*724ba675SRob Herring compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1008*724ba675SRob Herring reg = <0x02184400 0x200>; 1009*724ba675SRob Herring interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 1010*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBOH3>; 1011*724ba675SRob Herring fsl,usbphy = <&usbphynop1>; 1012*724ba675SRob Herring phy_type = "hsic"; 1013*724ba675SRob Herring fsl,usbmisc = <&usbmisc 2>; 1014*724ba675SRob Herring dr_mode = "host"; 1015*724ba675SRob Herring ahb-burst-config = <0x0>; 1016*724ba675SRob Herring tx-burst-size-dword = <0x10>; 1017*724ba675SRob Herring rx-burst-size-dword = <0x10>; 1018*724ba675SRob Herring status = "disabled"; 1019*724ba675SRob Herring }; 1020*724ba675SRob Herring 1021*724ba675SRob Herring usbh3: usb@2184600 { 1022*724ba675SRob Herring compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1023*724ba675SRob Herring reg = <0x02184600 0x200>; 1024*724ba675SRob Herring interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 1025*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBOH3>; 1026*724ba675SRob Herring fsl,usbphy = <&usbphynop2>; 1027*724ba675SRob Herring phy_type = "hsic"; 1028*724ba675SRob Herring fsl,usbmisc = <&usbmisc 3>; 1029*724ba675SRob Herring dr_mode = "host"; 1030*724ba675SRob Herring ahb-burst-config = <0x0>; 1031*724ba675SRob Herring tx-burst-size-dword = <0x10>; 1032*724ba675SRob Herring rx-burst-size-dword = <0x10>; 1033*724ba675SRob Herring status = "disabled"; 1034*724ba675SRob Herring }; 1035*724ba675SRob Herring 1036*724ba675SRob Herring usbmisc: usbmisc@2184800 { 1037*724ba675SRob Herring #index-cells = <1>; 1038*724ba675SRob Herring compatible = "fsl,imx6q-usbmisc"; 1039*724ba675SRob Herring reg = <0x02184800 0x200>; 1040*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USBOH3>; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring 1043*724ba675SRob Herring fec: ethernet@2188000 { 1044*724ba675SRob Herring compatible = "fsl,imx6q-fec"; 1045*724ba675SRob Herring reg = <0x02188000 0x4000>; 1046*724ba675SRob Herring interrupt-names = "int0", "pps"; 1047*724ba675SRob Herring interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, 1048*724ba675SRob Herring <0 119 IRQ_TYPE_LEVEL_HIGH>; 1049*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_ENET>, 1050*724ba675SRob Herring <&clks IMX6QDL_CLK_ENET>, 1051*724ba675SRob Herring <&clks IMX6QDL_CLK_ENET_REF>, 1052*724ba675SRob Herring <&clks IMX6QDL_CLK_ENET_REF_SEL>; 1053*724ba675SRob Herring clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 1054*724ba675SRob Herring fsl,stop-mode = <&gpr 0x34 27>; 1055*724ba675SRob Herring nvmem-cells = <&fec_mac_addr>; 1056*724ba675SRob Herring nvmem-cell-names = "mac-address"; 1057*724ba675SRob Herring status = "disabled"; 1058*724ba675SRob Herring }; 1059*724ba675SRob Herring 1060*724ba675SRob Herring mlb@218c000 { 1061*724ba675SRob Herring reg = <0x0218c000 0x4000>; 1062*724ba675SRob Herring interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 1063*724ba675SRob Herring <0 117 IRQ_TYPE_LEVEL_HIGH>, 1064*724ba675SRob Herring <0 126 IRQ_TYPE_LEVEL_HIGH>; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring 1067*724ba675SRob Herring usdhc1: mmc@2190000 { 1068*724ba675SRob Herring compatible = "fsl,imx6q-usdhc"; 1069*724ba675SRob Herring reg = <0x02190000 0x4000>; 1070*724ba675SRob Herring interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 1071*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USDHC1>, 1072*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC1>, 1073*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC1>; 1074*724ba675SRob Herring clock-names = "ipg", "ahb", "per"; 1075*724ba675SRob Herring bus-width = <4>; 1076*724ba675SRob Herring status = "disabled"; 1077*724ba675SRob Herring }; 1078*724ba675SRob Herring 1079*724ba675SRob Herring usdhc2: mmc@2194000 { 1080*724ba675SRob Herring compatible = "fsl,imx6q-usdhc"; 1081*724ba675SRob Herring reg = <0x02194000 0x4000>; 1082*724ba675SRob Herring interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 1083*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USDHC2>, 1084*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC2>, 1085*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC2>; 1086*724ba675SRob Herring clock-names = "ipg", "ahb", "per"; 1087*724ba675SRob Herring bus-width = <4>; 1088*724ba675SRob Herring status = "disabled"; 1089*724ba675SRob Herring }; 1090*724ba675SRob Herring 1091*724ba675SRob Herring usdhc3: mmc@2198000 { 1092*724ba675SRob Herring compatible = "fsl,imx6q-usdhc"; 1093*724ba675SRob Herring reg = <0x02198000 0x4000>; 1094*724ba675SRob Herring interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 1095*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USDHC3>, 1096*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC3>, 1097*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC3>; 1098*724ba675SRob Herring clock-names = "ipg", "ahb", "per"; 1099*724ba675SRob Herring bus-width = <4>; 1100*724ba675SRob Herring status = "disabled"; 1101*724ba675SRob Herring }; 1102*724ba675SRob Herring 1103*724ba675SRob Herring usdhc4: mmc@219c000 { 1104*724ba675SRob Herring compatible = "fsl,imx6q-usdhc"; 1105*724ba675SRob Herring reg = <0x0219c000 0x4000>; 1106*724ba675SRob Herring interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1107*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_USDHC4>, 1108*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC4>, 1109*724ba675SRob Herring <&clks IMX6QDL_CLK_USDHC4>; 1110*724ba675SRob Herring clock-names = "ipg", "ahb", "per"; 1111*724ba675SRob Herring bus-width = <4>; 1112*724ba675SRob Herring status = "disabled"; 1113*724ba675SRob Herring }; 1114*724ba675SRob Herring 1115*724ba675SRob Herring i2c1: i2c@21a0000 { 1116*724ba675SRob Herring #address-cells = <1>; 1117*724ba675SRob Herring #size-cells = <0>; 1118*724ba675SRob Herring compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1119*724ba675SRob Herring reg = <0x021a0000 0x4000>; 1120*724ba675SRob Herring interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1121*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_I2C1>; 1122*724ba675SRob Herring status = "disabled"; 1123*724ba675SRob Herring }; 1124*724ba675SRob Herring 1125*724ba675SRob Herring i2c2: i2c@21a4000 { 1126*724ba675SRob Herring #address-cells = <1>; 1127*724ba675SRob Herring #size-cells = <0>; 1128*724ba675SRob Herring compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1129*724ba675SRob Herring reg = <0x021a4000 0x4000>; 1130*724ba675SRob Herring interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1131*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_I2C2>; 1132*724ba675SRob Herring status = "disabled"; 1133*724ba675SRob Herring }; 1134*724ba675SRob Herring 1135*724ba675SRob Herring i2c3: i2c@21a8000 { 1136*724ba675SRob Herring #address-cells = <1>; 1137*724ba675SRob Herring #size-cells = <0>; 1138*724ba675SRob Herring compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1139*724ba675SRob Herring reg = <0x021a8000 0x4000>; 1140*724ba675SRob Herring interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1141*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_I2C3>; 1142*724ba675SRob Herring status = "disabled"; 1143*724ba675SRob Herring }; 1144*724ba675SRob Herring 1145*724ba675SRob Herring romcp@21ac000 { 1146*724ba675SRob Herring reg = <0x021ac000 0x4000>; 1147*724ba675SRob Herring }; 1148*724ba675SRob Herring 1149*724ba675SRob Herring mmdc0: memory-controller@21b0000 { /* MMDC0 */ 1150*724ba675SRob Herring compatible = "fsl,imx6q-mmdc"; 1151*724ba675SRob Herring reg = <0x021b0000 0x4000>; 1152*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 1153*724ba675SRob Herring }; 1154*724ba675SRob Herring 1155*724ba675SRob Herring mmdc1: memory-controller@21b4000 { /* MMDC1 */ 1156*724ba675SRob Herring compatible = "fsl,imx6q-mmdc"; 1157*724ba675SRob Herring reg = <0x021b4000 0x4000>; 1158*724ba675SRob Herring status = "disabled"; 1159*724ba675SRob Herring }; 1160*724ba675SRob Herring 1161*724ba675SRob Herring weim: weim@21b8000 { 1162*724ba675SRob Herring #address-cells = <2>; 1163*724ba675SRob Herring #size-cells = <1>; 1164*724ba675SRob Herring compatible = "fsl,imx6q-weim"; 1165*724ba675SRob Herring reg = <0x021b8000 0x4000>; 1166*724ba675SRob Herring interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1167*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1168*724ba675SRob Herring fsl,weim-cs-gpr = <&gpr>; 1169*724ba675SRob Herring status = "disabled"; 1170*724ba675SRob Herring }; 1171*724ba675SRob Herring 1172*724ba675SRob Herring ocotp: efuse@21bc000 { 1173*724ba675SRob Herring compatible = "fsl,imx6q-ocotp", "syscon"; 1174*724ba675SRob Herring reg = <0x021bc000 0x4000>; 1175*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IIM>; 1176*724ba675SRob Herring #address-cells = <1>; 1177*724ba675SRob Herring #size-cells = <1>; 1178*724ba675SRob Herring 1179*724ba675SRob Herring cpu_speed_grade: speed-grade@10 { 1180*724ba675SRob Herring reg = <0x10 4>; 1181*724ba675SRob Herring }; 1182*724ba675SRob Herring 1183*724ba675SRob Herring tempmon_calib: calib@38 { 1184*724ba675SRob Herring reg = <0x38 4>; 1185*724ba675SRob Herring }; 1186*724ba675SRob Herring 1187*724ba675SRob Herring tempmon_temp_grade: temp-grade@20 { 1188*724ba675SRob Herring reg = <0x20 4>; 1189*724ba675SRob Herring }; 1190*724ba675SRob Herring 1191*724ba675SRob Herring fec_mac_addr: mac-addr@88 { 1192*724ba675SRob Herring reg = <0x88 6>; 1193*724ba675SRob Herring }; 1194*724ba675SRob Herring }; 1195*724ba675SRob Herring 1196*724ba675SRob Herring tzasc@21d0000 { /* TZASC1 */ 1197*724ba675SRob Herring reg = <0x021d0000 0x4000>; 1198*724ba675SRob Herring interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1199*724ba675SRob Herring }; 1200*724ba675SRob Herring 1201*724ba675SRob Herring tzasc@21d4000 { /* TZASC2 */ 1202*724ba675SRob Herring reg = <0x021d4000 0x4000>; 1203*724ba675SRob Herring interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1204*724ba675SRob Herring }; 1205*724ba675SRob Herring 1206*724ba675SRob Herring audmux: audmux@21d8000 { 1207*724ba675SRob Herring compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1208*724ba675SRob Herring reg = <0x021d8000 0x4000>; 1209*724ba675SRob Herring status = "disabled"; 1210*724ba675SRob Herring }; 1211*724ba675SRob Herring 1212*724ba675SRob Herring mipi_csi: mipi@21dc000 { 1213*724ba675SRob Herring compatible = "fsl,imx6-mipi-csi2"; 1214*724ba675SRob Herring reg = <0x021dc000 0x4000>; 1215*724ba675SRob Herring #address-cells = <1>; 1216*724ba675SRob Herring #size-cells = <0>; 1217*724ba675SRob Herring interrupts = <0 100 0x04>, <0 101 0x04>; 1218*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_HSI_TX>, 1219*724ba675SRob Herring <&clks IMX6QDL_CLK_VIDEO_27M>, 1220*724ba675SRob Herring <&clks IMX6QDL_CLK_EIM_PODF>; 1221*724ba675SRob Herring clock-names = "dphy", "ref", "pix"; 1222*724ba675SRob Herring status = "disabled"; 1223*724ba675SRob Herring }; 1224*724ba675SRob Herring 1225*724ba675SRob Herring mipi_dsi: mipi@21e0000 { 1226*724ba675SRob Herring reg = <0x021e0000 0x4000>; 1227*724ba675SRob Herring status = "disabled"; 1228*724ba675SRob Herring 1229*724ba675SRob Herring ports { 1230*724ba675SRob Herring #address-cells = <1>; 1231*724ba675SRob Herring #size-cells = <0>; 1232*724ba675SRob Herring 1233*724ba675SRob Herring port@0 { 1234*724ba675SRob Herring reg = <0>; 1235*724ba675SRob Herring 1236*724ba675SRob Herring mipi_mux_0: endpoint { 1237*724ba675SRob Herring remote-endpoint = <&ipu1_di0_mipi>; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring }; 1240*724ba675SRob Herring 1241*724ba675SRob Herring port@1 { 1242*724ba675SRob Herring reg = <1>; 1243*724ba675SRob Herring 1244*724ba675SRob Herring mipi_mux_1: endpoint { 1245*724ba675SRob Herring remote-endpoint = <&ipu1_di1_mipi>; 1246*724ba675SRob Herring }; 1247*724ba675SRob Herring }; 1248*724ba675SRob Herring }; 1249*724ba675SRob Herring }; 1250*724ba675SRob Herring 1251*724ba675SRob Herring vdoa@21e4000 { 1252*724ba675SRob Herring compatible = "fsl,imx6q-vdoa"; 1253*724ba675SRob Herring reg = <0x021e4000 0x4000>; 1254*724ba675SRob Herring interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1255*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_VDOA>; 1256*724ba675SRob Herring }; 1257*724ba675SRob Herring 1258*724ba675SRob Herring uart2: serial@21e8000 { 1259*724ba675SRob Herring compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1260*724ba675SRob Herring reg = <0x021e8000 0x4000>; 1261*724ba675SRob Herring interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1262*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1263*724ba675SRob Herring <&clks IMX6QDL_CLK_UART_SERIAL>; 1264*724ba675SRob Herring clock-names = "ipg", "per"; 1265*724ba675SRob Herring dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1266*724ba675SRob Herring dma-names = "rx", "tx"; 1267*724ba675SRob Herring status = "disabled"; 1268*724ba675SRob Herring }; 1269*724ba675SRob Herring 1270*724ba675SRob Herring uart3: serial@21ec000 { 1271*724ba675SRob Herring compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1272*724ba675SRob Herring reg = <0x021ec000 0x4000>; 1273*724ba675SRob Herring interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1274*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1275*724ba675SRob Herring <&clks IMX6QDL_CLK_UART_SERIAL>; 1276*724ba675SRob Herring clock-names = "ipg", "per"; 1277*724ba675SRob Herring dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1278*724ba675SRob Herring dma-names = "rx", "tx"; 1279*724ba675SRob Herring status = "disabled"; 1280*724ba675SRob Herring }; 1281*724ba675SRob Herring 1282*724ba675SRob Herring uart4: serial@21f0000 { 1283*724ba675SRob Herring compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1284*724ba675SRob Herring reg = <0x021f0000 0x4000>; 1285*724ba675SRob Herring interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1286*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1287*724ba675SRob Herring <&clks IMX6QDL_CLK_UART_SERIAL>; 1288*724ba675SRob Herring clock-names = "ipg", "per"; 1289*724ba675SRob Herring dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1290*724ba675SRob Herring dma-names = "rx", "tx"; 1291*724ba675SRob Herring status = "disabled"; 1292*724ba675SRob Herring }; 1293*724ba675SRob Herring 1294*724ba675SRob Herring uart5: serial@21f4000 { 1295*724ba675SRob Herring compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1296*724ba675SRob Herring reg = <0x021f4000 0x4000>; 1297*724ba675SRob Herring interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1298*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1299*724ba675SRob Herring <&clks IMX6QDL_CLK_UART_SERIAL>; 1300*724ba675SRob Herring clock-names = "ipg", "per"; 1301*724ba675SRob Herring dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1302*724ba675SRob Herring dma-names = "rx", "tx"; 1303*724ba675SRob Herring status = "disabled"; 1304*724ba675SRob Herring }; 1305*724ba675SRob Herring }; 1306*724ba675SRob Herring 1307*724ba675SRob Herring ipu1: ipu@2400000 { 1308*724ba675SRob Herring #address-cells = <1>; 1309*724ba675SRob Herring #size-cells = <0>; 1310*724ba675SRob Herring compatible = "fsl,imx6q-ipu"; 1311*724ba675SRob Herring reg = <0x02400000 0x400000>; 1312*724ba675SRob Herring interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1313*724ba675SRob Herring <0 5 IRQ_TYPE_LEVEL_HIGH>; 1314*724ba675SRob Herring clocks = <&clks IMX6QDL_CLK_IPU1>, 1315*724ba675SRob Herring <&clks IMX6QDL_CLK_IPU1_DI0>, 1316*724ba675SRob Herring <&clks IMX6QDL_CLK_IPU1_DI1>; 1317*724ba675SRob Herring clock-names = "bus", "di0", "di1"; 1318*724ba675SRob Herring resets = <&src 2>; 1319*724ba675SRob Herring 1320*724ba675SRob Herring ipu1_csi0: port@0 { 1321*724ba675SRob Herring reg = <0>; 1322*724ba675SRob Herring 1323*724ba675SRob Herring ipu1_csi0_from_ipu1_csi0_mux: endpoint { 1324*724ba675SRob Herring remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; 1325*724ba675SRob Herring }; 1326*724ba675SRob Herring }; 1327*724ba675SRob Herring 1328*724ba675SRob Herring ipu1_csi1: port@1 { 1329*724ba675SRob Herring reg = <1>; 1330*724ba675SRob Herring }; 1331*724ba675SRob Herring 1332*724ba675SRob Herring ipu1_di0: port@2 { 1333*724ba675SRob Herring #address-cells = <1>; 1334*724ba675SRob Herring #size-cells = <0>; 1335*724ba675SRob Herring reg = <2>; 1336*724ba675SRob Herring 1337*724ba675SRob Herring ipu1_di0_disp0: endpoint@0 { 1338*724ba675SRob Herring reg = <0>; 1339*724ba675SRob Herring }; 1340*724ba675SRob Herring 1341*724ba675SRob Herring ipu1_di0_hdmi: endpoint@1 { 1342*724ba675SRob Herring reg = <1>; 1343*724ba675SRob Herring remote-endpoint = <&hdmi_mux_0>; 1344*724ba675SRob Herring }; 1345*724ba675SRob Herring 1346*724ba675SRob Herring ipu1_di0_mipi: endpoint@2 { 1347*724ba675SRob Herring reg = <2>; 1348*724ba675SRob Herring remote-endpoint = <&mipi_mux_0>; 1349*724ba675SRob Herring }; 1350*724ba675SRob Herring 1351*724ba675SRob Herring ipu1_di0_lvds0: endpoint@3 { 1352*724ba675SRob Herring reg = <3>; 1353*724ba675SRob Herring remote-endpoint = <&lvds0_mux_0>; 1354*724ba675SRob Herring }; 1355*724ba675SRob Herring 1356*724ba675SRob Herring ipu1_di0_lvds1: endpoint@4 { 1357*724ba675SRob Herring reg = <4>; 1358*724ba675SRob Herring remote-endpoint = <&lvds1_mux_0>; 1359*724ba675SRob Herring }; 1360*724ba675SRob Herring }; 1361*724ba675SRob Herring 1362*724ba675SRob Herring ipu1_di1: port@3 { 1363*724ba675SRob Herring #address-cells = <1>; 1364*724ba675SRob Herring #size-cells = <0>; 1365*724ba675SRob Herring reg = <3>; 1366*724ba675SRob Herring 1367*724ba675SRob Herring ipu1_di1_disp1: endpoint@0 { 1368*724ba675SRob Herring reg = <0>; 1369*724ba675SRob Herring }; 1370*724ba675SRob Herring 1371*724ba675SRob Herring ipu1_di1_hdmi: endpoint@1 { 1372*724ba675SRob Herring reg = <1>; 1373*724ba675SRob Herring remote-endpoint = <&hdmi_mux_1>; 1374*724ba675SRob Herring }; 1375*724ba675SRob Herring 1376*724ba675SRob Herring ipu1_di1_mipi: endpoint@2 { 1377*724ba675SRob Herring reg = <2>; 1378*724ba675SRob Herring remote-endpoint = <&mipi_mux_1>; 1379*724ba675SRob Herring }; 1380*724ba675SRob Herring 1381*724ba675SRob Herring ipu1_di1_lvds0: endpoint@3 { 1382*724ba675SRob Herring reg = <3>; 1383*724ba675SRob Herring remote-endpoint = <&lvds0_mux_1>; 1384*724ba675SRob Herring }; 1385*724ba675SRob Herring 1386*724ba675SRob Herring ipu1_di1_lvds1: endpoint@4 { 1387*724ba675SRob Herring reg = <4>; 1388*724ba675SRob Herring remote-endpoint = <&lvds1_mux_1>; 1389*724ba675SRob Herring }; 1390*724ba675SRob Herring }; 1391*724ba675SRob Herring }; 1392*724ba675SRob Herring }; 1393*724ba675SRob Herring}; 1394