xref: /linux/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	sound {
16		compatible = "fsl,imx6-wandboard-sgtl5000",
17			     "fsl,imx-audio-sgtl5000";
18		model = "imx6-wandboard-sgtl5000";
19		ssi-controller = <&ssi1>;
20		audio-codec = <&codec>;
21		audio-routing =
22			"MIC_IN", "Mic Jack",
23			"Mic Jack", "Mic Bias",
24			"Headphone Jack", "HP_OUT";
25		mux-int-port = <1>;
26		mux-ext-port = <3>;
27	};
28
29	spdif_out: spdif-out {
30		compatible = "linux,spdif-dit";
31		#sound-dai-cells = <0>;
32	};
33
34	sound-spdif {
35		compatible = "fsl,imx-audio-spdif";
36		model = "imx-spdif";
37		audio-cpu = <&spdif>;
38		audio-codec = <&spdif_out>;
39	};
40
41	reg_1p5v: regulator-1p5v {
42		compatible = "regulator-fixed";
43		regulator-name = "1P5V";
44		regulator-min-microvolt = <1500000>;
45		regulator-max-microvolt = <1500000>;
46		regulator-always-on;
47	};
48
49	reg_1p8v: regulator-1p8v {
50		compatible = "regulator-fixed";
51		regulator-name = "1P8V";
52		regulator-min-microvolt = <1800000>;
53		regulator-max-microvolt = <1800000>;
54		regulator-always-on;
55	};
56
57	reg_2p8v: regulator-2p8v {
58		compatible = "regulator-fixed";
59		regulator-name = "2P8V";
60		regulator-min-microvolt = <2800000>;
61		regulator-max-microvolt = <2800000>;
62		regulator-always-on;
63	};
64
65	reg_2p5v: regulator-2p5v {
66		compatible = "regulator-fixed";
67		regulator-name = "2P5V";
68		regulator-min-microvolt = <2500000>;
69		regulator-max-microvolt = <2500000>;
70		regulator-always-on;
71	};
72
73	reg_3p3v: regulator-3p3v {
74		compatible = "regulator-fixed";
75		regulator-name = "3P3V";
76		regulator-min-microvolt = <3300000>;
77		regulator-max-microvolt = <3300000>;
78		regulator-always-on;
79	};
80
81	reg_usb_otg_vbus: regulator-usbotgvbus {
82		compatible = "regulator-fixed";
83		regulator-name = "usb_otg_vbus";
84		regulator-min-microvolt = <5000000>;
85		regulator-max-microvolt = <5000000>;
86		pinctrl-names = "default";
87		pinctrl-0 = <&pinctrl_usbotgvbus>;
88		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
89	};
90};
91
92&audmux {
93	pinctrl-names = "default";
94	pinctrl-0 = <&pinctrl_audmux>;
95	status = "okay";
96};
97
98&hdmi {
99	ddc-i2c-bus = <&i2c1>;
100	status = "okay";
101};
102
103&i2c1 {
104	clock-frequency = <100000>;
105	pinctrl-names = "default", "gpio";
106	pinctrl-0 = <&pinctrl_i2c1>;
107	pinctrl-1 = <&pinctrl_i2c1_gpio>;
108	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
109	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
110	status = "okay";
111};
112
113&i2c2 {
114	clock-frequency = <100000>;
115	pinctrl-names = "default", "gpio";
116	pinctrl-0 = <&pinctrl_i2c2>;
117	pinctrl-1 = <&pinctrl_i2c2_gpio>;
118	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
119	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
120	status = "okay";
121
122	codec: sgtl5000@a {
123		pinctrl-names = "default";
124		pinctrl-0 = <&pinctrl_mclk>;
125		compatible = "fsl,sgtl5000";
126		reg = <0x0a>;
127		#sound-dai-cells = <0>;
128		clocks = <&clks IMX6QDL_CLK_CKO>;
129		VDDA-supply = <&reg_2p5v>;
130		VDDIO-supply = <&reg_3p3v>;
131		lrclk-strength = <3>;
132	};
133
134	camera@3c {
135		compatible = "ovti,ov5645";
136		pinctrl-names = "default";
137		pinctrl-0 = <&pinctrl_ov5645>;
138		reg = <0x3c>;
139		clocks = <&clks IMX6QDL_CLK_CKO2>;
140		clock-frequency = <24000000>;
141		vdddo-supply = <&reg_1p8v>;
142		vdda-supply = <&reg_2p8v>;
143		vddd-supply = <&reg_1p5v>;
144		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
145		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
146
147		port {
148			ov5645_to_mipi_csi2: endpoint {
149				remote-endpoint = <&mipi_csi2_in>;
150				clock-lanes = <0>;
151				data-lanes = <1 2>;
152			};
153		};
154	};
155};
156
157&iomuxc {
158	pinctrl-names = "default";
159
160	pinctrl_audmux: audmuxgrp {
161		fsl,pins = <
162			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
163			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
164			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
165			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
166		>;
167	};
168
169	pinctrl_enet: enetgrp {
170		fsl,pins = <
171			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
172			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
173			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
174			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
175			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
176			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
177			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
178			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
179			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
180			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
181			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
182			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
183			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
184			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
185			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
186			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
187		>;
188	};
189
190	pinctrl_i2c1: i2c1grp {
191		fsl,pins = <
192			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
193			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
194		>;
195	};
196
197	pinctrl_i2c1_gpio: i2c1gpiogrp {
198		fsl,pins = <
199			MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b0
200			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b0
201		>;
202	};
203
204	pinctrl_i2c2: i2c2grp {
205		fsl,pins = <
206			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
207			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
208		>;
209	};
210
211	pinctrl_i2c2_gpio: i2c2gpiogrp {
212		fsl,pins = <
213			MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x4001b8b0
214			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x4001b8b0
215		>;
216	};
217
218	pinctrl_mclk: mclkgrp {
219		fsl,pins = <
220			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
221		>;
222	};
223
224	pinctrl_ov5645: ov5645grp {
225		fsl,pins = <
226			MX6QDL_PAD_GPIO_3__CCM_CLKO2		0x000b0
227			MX6QDL_PAD_GPIO_6__GPIO1_IO06		0x1b0b0
228			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0
229		>;
230	};
231
232	pinctrl_spdif: spdifgrp {
233		fsl,pins = <
234			MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
235		>;
236	};
237
238	pinctrl_uart1: uart1grp {
239		fsl,pins = <
240			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
241			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
242		>;
243	};
244
245	pinctrl_uart3: uart3grp {
246		fsl,pins = <
247			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
248			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
249			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
250			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
251		>;
252	};
253
254	pinctrl_usbotg: usbotggrp {
255		fsl,pins = <
256			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
257		>;
258	};
259
260	pinctrl_usbotgvbus: usbotgvbusgrp {
261		fsl,pins = <
262			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
263		>;
264	};
265
266	pinctrl_usdhc1: usdhc1grp {
267		fsl,pins = <
268			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
269			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
270			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
271			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
272			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
273			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
274		>;
275	};
276
277	pinctrl_usdhc2: usdhc2grp {
278		fsl,pins = <
279			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
280			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
281			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
282			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
283			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
284			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
285		>;
286	};
287
288	pinctrl_usdhc3: usdhc3grp {
289		fsl,pins = <
290			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
291			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
292			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
293			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
294			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
295			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
296		>;
297	};
298};
299
300&fec {
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_enet>;
303	phy-mode = "rgmii-id";
304	phy-handle = <&ethphy>;
305	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
306	status = "okay";
307
308	mdio {
309		#address-cells = <1>;
310		#size-cells = <0>;
311
312		ethphy: ethernet-phy@1 {
313			reg = <1>;
314			qca,clk-out-frequency = <125000000>;
315		};
316	};
317};
318
319&mipi_csi {
320	status = "okay";
321
322	port@0 {
323		reg = <0>;
324
325		mipi_csi2_in: endpoint {
326			remote-endpoint = <&ov5645_to_mipi_csi2>;
327			clock-lanes = <0>;
328			data-lanes = <1 2>;
329		};
330	};
331};
332
333&spdif {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_spdif>;
336	status = "okay";
337};
338
339&ssi1 {
340	status = "okay";
341};
342
343&uart1 {
344	pinctrl-names = "default";
345	pinctrl-0 = <&pinctrl_uart1>;
346	status = "okay";
347};
348
349&uart3 {
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_uart3>;
352	uart-has-rtscts;
353	status = "okay";
354};
355
356&usbh1 {
357	status = "okay";
358};
359
360&usbotg {
361	vbus-supply = <&reg_usb_otg_vbus>;
362	pinctrl-names = "default";
363	pinctrl-0 = <&pinctrl_usbotg>;
364	disable-over-current;
365	dr_mode = "otg";
366	status = "okay";
367};
368
369&usdhc1 {
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_usdhc1>;
372	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
373	status = "okay";
374};
375
376&usdhc3 {
377	pinctrl-names = "default";
378	pinctrl-0 = <&pinctrl_usdhc3>;
379	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
380	status = "okay";
381};
382