1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2014 FEDEVEL, Inc. 4 * 5 * Author: Robert Nelson <robertcnelson@gmail.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 reg_3p3v: regulator-3p3v { 17 compatible = "regulator-fixed"; 18 regulator-name = "3P3V"; 19 regulator-min-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>; 21 regulator-always-on; 22 }; 23 24 reg_usbh1_vbus: regulator-usbh1-vbus { 25 compatible = "regulator-fixed"; 26 regulator-name = "usbh1_vbus"; 27 regulator-min-microvolt = <5000000>; 28 regulator-max-microvolt = <5000000>; 29 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 reg_usb_otg_vbus: regulator-otg-vbus { 34 compatible = "regulator-fixed"; 35 regulator-name = "usb_otg_vbus"; 36 regulator-min-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>; 38 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 39 enable-active-high; 40 }; 41 42 leds { 43 compatible = "gpio-leds"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_led>; 46 47 led0: led-usr { 48 label = "usr"; 49 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 50 default-state = "off"; 51 linux,default-trigger = "heartbeat"; 52 }; 53 }; 54 55 sound { 56 compatible = "fsl,imx6-rex-sgtl5000", 57 "fsl,imx-audio-sgtl5000"; 58 model = "imx6-rex-sgtl5000"; 59 ssi-controller = <&ssi1>; 60 audio-codec = <&codec>; 61 audio-routing = 62 "MIC_IN", "Mic Jack", 63 "Mic Jack", "Mic Bias", 64 "Headphone Jack", "HP_OUT"; 65 mux-int-port = <1>; 66 mux-ext-port = <3>; 67 }; 68}; 69 70&audmux { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_audmux>; 73 status = "okay"; 74}; 75 76&ecspi2 { 77 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_ecspi2>; 80 status = "okay"; 81}; 82 83&ecspi3 { 84 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_ecspi3>; 87 status = "okay"; 88}; 89 90&fec { 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_enet>; 93 phy-mode = "rgmii"; 94 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 95 status = "okay"; 96}; 97 98&hdmi { 99 ddc-i2c-bus = <&i2c2>; 100 status = "okay"; 101}; 102 103&i2c1 { 104 clock-frequency = <100000>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_i2c1>; 107 status = "okay"; 108 109 codec: sgtl5000@a { 110 compatible = "fsl,sgtl5000"; 111 reg = <0x0a>; 112 #sound-dai-cells = <0>; 113 clocks = <&clks IMX6QDL_CLK_CKO>; 114 VDDA-supply = <®_3p3v>; 115 VDDIO-supply = <®_3p3v>; 116 }; 117}; 118 119&i2c2 { 120 clock-frequency = <100000>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_i2c2>; 123 status = "okay"; 124 125 pca9535: gpio-expander@27 { 126 compatible = "nxp,pca9535"; 127 reg = <0x27>; 128 gpio-controller; 129 #gpio-cells = <2>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pca9535>; 132 interrupt-parent = <&gpio6>; 133 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 134 interrupt-controller; 135 #interrupt-cells = <2>; 136 }; 137 138 eeprom@57 { 139 compatible = "atmel,24c02"; 140 reg = <0x57>; 141 }; 142}; 143 144&i2c3 { 145 clock-frequency = <100000>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_i2c3>; 148 status = "okay"; 149}; 150 151&iomuxc { 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_hog>; 154 155 pinctrl_hog: hoggrp { 156 fsl,pins = < 157 /* SGTL5000 sys_mclk */ 158 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 159 >; 160 }; 161 162 pinctrl_audmux: audmuxgrp { 163 fsl,pins = < 164 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 165 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 166 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 167 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 168 >; 169 }; 170 171 pinctrl_ecspi2: ecspi2grp { 172 fsl,pins = < 173 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 174 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 175 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 176 /* CS */ 177 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 178 >; 179 }; 180 181 pinctrl_ecspi3: ecspi3grp { 182 fsl,pins = < 183 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 184 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 185 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 186 /* CS */ 187 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 188 >; 189 }; 190 191 pinctrl_enet: enetgrp { 192 fsl,pins = < 193 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 194 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 195 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 196 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 197 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 198 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 199 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 200 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 201 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 202 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 203 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 204 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 205 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 206 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 207 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 208 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 209 /* Phy reset */ 210 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 211 >; 212 }; 213 214 pinctrl_i2c1: i2c1grp { 215 fsl,pins = < 216 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 217 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 218 >; 219 }; 220 221 pinctrl_i2c2: i2c2grp { 222 fsl,pins = < 223 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 224 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 225 >; 226 }; 227 228 pinctrl_i2c3: i2c3grp { 229 fsl,pins = < 230 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 231 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 232 >; 233 }; 234 235 pinctrl_led: ledgrp { 236 fsl,pins = < 237 /* user led */ 238 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 239 >; 240 }; 241 242 pinctrl_pca9535: pca9535grp { 243 fsl,pins = < 244 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 245 >; 246 }; 247 248 pinctrl_uart1: uart1grp { 249 fsl,pins = < 250 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 251 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 252 >; 253 }; 254 255 pinctrl_uart2: uart2grp { 256 fsl,pins = < 257 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 258 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 259 >; 260 }; 261 262 pinctrl_usbh1: usbh1grp { 263 fsl,pins = < 264 /* power enable, high active */ 265 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 266 >; 267 }; 268 269 pinctrl_usbotg: usbotggrp { 270 fsl,pins = < 271 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 272 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 273 /* power enable, high active */ 274 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 275 >; 276 }; 277 278 pinctrl_usdhc2: usdhc2grp { 279 fsl,pins = < 280 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 281 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 282 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 283 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 284 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 285 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 286 /* CD */ 287 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 288 /* WP */ 289 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 290 >; 291 }; 292 293 pinctrl_usdhc3: usdhc3grp { 294 fsl,pins = < 295 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 296 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 297 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 298 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 299 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 300 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 301 /* CD */ 302 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 303 /* WP */ 304 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 305 >; 306 }; 307}; 308 309&ssi1 { 310 status = "okay"; 311}; 312 313&uart1 { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_uart1>; 316 status = "okay"; 317}; 318 319&uart2 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_uart2>; 322 status = "okay"; 323}; 324 325&usbh1 { 326 vbus-supply = <®_usbh1_vbus>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_usbh1>; 329 status = "okay"; 330}; 331 332&usbotg { 333 vbus-supply = <®_usb_otg_vbus>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_usbotg>; 336 status = "okay"; 337}; 338 339&usdhc2 { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_usdhc2>; 342 bus-width = <4>; 343 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 344 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 345 status = "okay"; 346}; 347 348&usdhc3 { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_usdhc3>; 351 bus-width = <4>; 352 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 353 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 354 status = "okay"; 355}; 356