1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 nand = &gpmi; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 stdout-path = &uart2; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 27 key-user-pb { 28 label = "user_pb"; 29 gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; 30 linux,code = <BTN_0>; 31 }; 32 33 key-user-pb1x { 34 label = "user_pb1x"; 35 linux,code = <BTN_1>; 36 interrupt-parent = <&gsc>; 37 interrupts = <0>; 38 }; 39 40 key-erased { 41 label = "key-erased"; 42 linux,code = <BTN_2>; 43 interrupt-parent = <&gsc>; 44 interrupts = <1>; 45 }; 46 47 key-eeprom-wp { 48 label = "eeprom_wp"; 49 linux,code = <BTN_3>; 50 interrupt-parent = <&gsc>; 51 interrupts = <2>; 52 }; 53 54 key-tamper { 55 label = "tamper"; 56 linux,code = <BTN_4>; 57 interrupt-parent = <&gsc>; 58 interrupts = <5>; 59 }; 60 61 key-switch-hold { 62 label = "switch_hold"; 63 linux,code = <BTN_5>; 64 interrupt-parent = <&gsc>; 65 interrupts = <7>; 66 }; 67 }; 68 69 leds { 70 compatible = "gpio-leds"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_leds>; 73 74 led0: led-user1 { 75 label = "user1"; 76 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 77 default-state = "on"; 78 linux,default-trigger = "heartbeat"; 79 }; 80 81 led1: led-user2 { 82 label = "user2"; 83 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 84 default-state = "off"; 85 }; 86 }; 87 88 memory@10000000 { 89 device_type = "memory"; 90 reg = <0x10000000 0x20000000>; 91 }; 92 93 pps { 94 compatible = "pps-gpio"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pps>; 97 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 98 status = "okay"; 99 }; 100 101 reg_3p3v: regulator-3p3v { 102 compatible = "regulator-fixed"; 103 regulator-name = "3P3V"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 regulator-always-on; 107 }; 108 109 reg_5p0v: regulator-5p0v { 110 compatible = "regulator-fixed"; 111 regulator-name = "5P0V"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 regulator-always-on; 115 }; 116}; 117 118&fec { 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_enet>; 121 phy-mode = "rgmii-id"; 122 status = "okay"; 123}; 124 125&gpmi { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_gpmi_nand>; 128 status = "okay"; 129}; 130 131&i2c1 { 132 clock-frequency = <100000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_i2c1>; 135 status = "okay"; 136 137 gsc: gsc@20 { 138 compatible = "gw,gsc"; 139 reg = <0x20>; 140 interrupt-parent = <&gpio1>; 141 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 142 interrupt-controller; 143 #interrupt-cells = <1>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 adc { 148 compatible = "gw,gsc-adc"; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 channel@6 { 153 gw,mode = <0>; 154 reg = <0x06>; 155 label = "temp"; 156 }; 157 158 channel@8 { 159 gw,mode = <3>; 160 reg = <0x08>; 161 label = "vdd_bat"; 162 }; 163 164 channel@82 { 165 gw,mode = <2>; 166 reg = <0x82>; 167 label = "vdd_vin"; 168 gw,voltage-divider-ohms = <22100 1000>; 169 gw,voltage-offset-microvolt = <800000>; 170 }; 171 172 channel@84 { 173 gw,mode = <2>; 174 reg = <0x84>; 175 label = "vdd_5p0"; 176 gw,voltage-divider-ohms = <22100 10000>; 177 }; 178 179 channel@86 { 180 gw,mode = <2>; 181 reg = <0x86>; 182 label = "vdd_3p3"; 183 gw,voltage-divider-ohms = <10000 10000>; 184 }; 185 186 channel@88 { 187 gw,mode = <2>; 188 reg = <0x88>; 189 label = "vdd_2p5"; 190 gw,voltage-divider-ohms = <10000 10000>; 191 }; 192 193 channel@8c { 194 gw,mode = <2>; 195 reg = <0x8c>; 196 label = "vdd_arm"; 197 }; 198 199 channel@8e { 200 gw,mode = <2>; 201 reg = <0x8e>; 202 label = "vdd_soc"; 203 }; 204 205 channel@90 { 206 gw,mode = <2>; 207 reg = <0x90>; 208 label = "vdd_1p5"; 209 }; 210 211 channel@92 { 212 gw,mode = <2>; 213 reg = <0x92>; 214 label = "vdd_1p0"; 215 }; 216 217 channel@98 { 218 gw,mode = <2>; 219 reg = <0x98>; 220 label = "vdd_3p0"; 221 }; 222 223 channel@9a { 224 gw,mode = <2>; 225 reg = <0x9a>; 226 label = "vdd_an1"; 227 gw,voltage-divider-ohms = <10000 10000>; 228 }; 229 230 channel@a2 { 231 gw,mode = <2>; 232 reg = <0xa2>; 233 label = "vdd_gsc"; 234 gw,voltage-divider-ohms = <10000 10000>; 235 }; 236 }; 237 }; 238 239 gsc_gpio: gpio@23 { 240 compatible = "nxp,pca9555"; 241 reg = <0x23>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 interrupt-parent = <&gsc>; 245 interrupts = <4>; 246 }; 247 248 eeprom@50 { 249 compatible = "atmel,24c02"; 250 reg = <0x50>; 251 pagesize = <16>; 252 }; 253 254 eeprom@51 { 255 compatible = "atmel,24c02"; 256 reg = <0x51>; 257 pagesize = <16>; 258 }; 259 260 eeprom@52 { 261 compatible = "atmel,24c02"; 262 reg = <0x52>; 263 pagesize = <16>; 264 }; 265 266 eeprom@53 { 267 compatible = "atmel,24c02"; 268 reg = <0x53>; 269 pagesize = <16>; 270 }; 271 272 rtc@68 { 273 compatible = "dallas,ds1672"; 274 reg = <0x68>; 275 }; 276}; 277 278&i2c2 { 279 clock-frequency = <100000>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_i2c2>; 282 status = "okay"; 283}; 284 285&i2c3 { 286 clock-frequency = <100000>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_i2c3>; 289 status = "okay"; 290}; 291 292&pcie { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_pcie>; 295 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 296 status = "okay"; 297}; 298 299&pwm2 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 302 status = "disabled"; 303}; 304 305&pwm3 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 308 status = "disabled"; 309}; 310 311&pwm4 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 314 status = "disabled"; 315}; 316 317&uart1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_uart1>; 320 status = "okay"; 321}; 322 323&uart2 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart2>; 326 status = "okay"; 327}; 328 329&uart3 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_uart3>; 332 status = "okay"; 333}; 334 335&uart5 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart5>; 338 status = "okay"; 339}; 340 341&usbotg { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_usbotg>; 344 disable-over-current; 345 status = "okay"; 346}; 347 348&usbh1 { 349 status = "okay"; 350}; 351 352&wdog1 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_wdog>; 355 fsl,ext-reset-output; 356}; 357 358&iomuxc { 359 pinctrl_enet: enetgrp { 360 fsl,pins = < 361 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 362 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 363 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 364 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 365 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 366 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 367 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 368 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 369 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 370 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 371 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 372 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 373 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 374 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 375 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 376 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 377 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 378 >; 379 }; 380 381 pinctrl_gpio_leds: gpioledsgrp { 382 fsl,pins = < 383 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 384 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 385 >; 386 }; 387 388 pinctrl_gpmi_nand: gpminandgrp { 389 fsl,pins = < 390 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 391 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 392 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 393 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 394 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 395 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 396 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 397 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 398 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 399 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 400 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 401 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 402 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 403 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 404 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 405 >; 406 }; 407 408 pinctrl_i2c1: i2c1grp { 409 fsl,pins = < 410 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 411 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 412 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 413 >; 414 }; 415 416 pinctrl_i2c2: i2c2grp { 417 fsl,pins = < 418 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 419 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 420 >; 421 }; 422 423 pinctrl_i2c3: i2c3grp { 424 fsl,pins = < 425 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 426 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 427 >; 428 }; 429 430 pinctrl_pcie: pciegrp { 431 fsl,pins = < 432 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 433 >; 434 }; 435 436 pinctrl_pps: ppsgrp { 437 fsl,pins = < 438 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 439 >; 440 }; 441 442 pinctrl_pwm2: pwm2grp { 443 fsl,pins = < 444 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 445 >; 446 }; 447 448 pinctrl_pwm3: pwm3grp { 449 fsl,pins = < 450 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 451 >; 452 }; 453 454 pinctrl_pwm4: pwm4grp { 455 fsl,pins = < 456 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 457 >; 458 }; 459 460 pinctrl_uart1: uart1grp { 461 fsl,pins = < 462 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 463 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 464 >; 465 }; 466 467 pinctrl_uart2: uart2grp { 468 fsl,pins = < 469 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 470 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 471 >; 472 }; 473 474 pinctrl_uart3: uart3grp { 475 fsl,pins = < 476 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 477 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 478 >; 479 }; 480 481 pinctrl_uart5: uart5grp { 482 fsl,pins = < 483 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 484 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 485 >; 486 }; 487 488 pinctrl_usbotg: usbotggrp { 489 fsl,pins = < 490 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 491 >; 492 }; 493 494 pinctrl_wdog: wdoggrp { 495 fsl,pins = < 496 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 497 >; 498 }; 499}; 500