1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 ethernet0 = &fec; 14 ethernet1 = &lan1; 15 ethernet2 = &lan2; 16 ethernet3 = &lan3; 17 ethernet4 = &lan4; 18 led0 = &led0; 19 led1 = &led1; 20 led2 = &led2; 21 usb0 = &usbh1; 22 usb1 = &usbotg; 23 }; 24 25 chosen { 26 stdout-path = &uart2; 27 }; 28 29 backlight { 30 compatible = "pwm-backlight"; 31 pwms = <&pwm4 0 5000000 0>; 32 brightness-levels = <0 4 8 16 32 64 128 255>; 33 default-brightness-level = <7>; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys"; 38 39 key-user-pb { 40 label = "user_pb"; 41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 42 linux,code = <BTN_0>; 43 }; 44 45 key-user-pb1x { 46 label = "user_pb1x"; 47 linux,code = <BTN_1>; 48 interrupt-parent = <&gsc>; 49 interrupts = <0>; 50 }; 51 52 key-erased { 53 label = "key-erased"; 54 linux,code = <BTN_2>; 55 interrupt-parent = <&gsc>; 56 interrupts = <1>; 57 }; 58 59 key-eeprom-wp { 60 label = "eeprom_wp"; 61 linux,code = <BTN_3>; 62 interrupt-parent = <&gsc>; 63 interrupts = <2>; 64 }; 65 66 key-tamper { 67 label = "tamper"; 68 linux,code = <BTN_4>; 69 interrupt-parent = <&gsc>; 70 interrupts = <5>; 71 }; 72 73 key-switch-hold { 74 label = "switch_hold"; 75 linux,code = <BTN_5>; 76 interrupt-parent = <&gsc>; 77 interrupts = <7>; 78 }; 79 }; 80 81 leds { 82 compatible = "gpio-leds"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_gpio_leds>; 85 86 led0: led-user1 { 87 label = "user1"; 88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 89 default-state = "on"; 90 linux,default-trigger = "heartbeat"; 91 }; 92 93 led1: led-user2 { 94 label = "user2"; 95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 96 default-state = "off"; 97 }; 98 99 led2: led-user3 { 100 label = "user3"; 101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 102 default-state = "off"; 103 }; 104 }; 105 106 memory@10000000 { 107 device_type = "memory"; 108 reg = <0x10000000 0x40000000>; 109 }; 110 111 pps { 112 compatible = "pps-gpio"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_pps>; 115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 116 }; 117 118 reg_1p0v: regulator-1p0v { 119 compatible = "regulator-fixed"; 120 regulator-name = "1P0V"; 121 regulator-min-microvolt = <1000000>; 122 regulator-max-microvolt = <1000000>; 123 regulator-always-on; 124 }; 125 126 reg_3p3v: regulator-3p3v { 127 compatible = "regulator-fixed"; 128 regulator-name = "3P3V"; 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 regulator-always-on; 132 }; 133 134 reg_usb_h1_vbus: regulator-usb-h1-vbus { 135 compatible = "regulator-fixed"; 136 regulator-name = "usb_h1_vbus"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 regulator-always-on; 140 }; 141 142 reg_usb_otg_vbus: regulator-usb-otg-vbus { 143 compatible = "regulator-fixed"; 144 regulator-name = "usb_otg_vbus"; 145 regulator-min-microvolt = <5000000>; 146 regulator-max-microvolt = <5000000>; 147 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 148 enable-active-high; 149 }; 150}; 151 152&clks { 153 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 154 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 155 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 156 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 157}; 158 159&fec { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_enet>; 162 phy-mode = "rgmii-id"; 163 status = "okay"; 164 165 fixed-link { 166 speed = <1000>; 167 full-duplex; 168 }; 169 170 mdio { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 switch@0 { 175 compatible = "marvell,mv88e6085"; 176 reg = <0>; 177 178 mdio { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 sw_phy0: ethernet-phy@0 { 183 reg = <0x0>; 184 }; 185 186 sw_phy1: ethernet-phy@1 { 187 reg = <0x1>; 188 }; 189 190 sw_phy2: ethernet-phy@2 { 191 reg = <0x2>; 192 }; 193 194 sw_phy3: ethernet-phy@3 { 195 reg = <0x3>; 196 }; 197 }; 198 199 ports { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 lan4: port@0 { 204 reg = <0>; 205 label = "lan4"; 206 phy-handle = <&sw_phy0>; 207 phy-mode = "internal"; 208 local-mac-address = [00 00 00 00 00 00]; 209 }; 210 211 lan3: port@1 { 212 reg = <1>; 213 label = "lan3"; 214 phy-handle = <&sw_phy1>; 215 phy-mode = "internal"; 216 local-mac-address = [00 00 00 00 00 00]; 217 }; 218 219 lan2: port@2 { 220 reg = <2>; 221 label = "lan2"; 222 phy-handle = <&sw_phy2>; 223 phy-mode = "internal"; 224 local-mac-address = [00 00 00 00 00 00]; 225 }; 226 227 lan1: port@3 { 228 reg = <3>; 229 label = "lan1"; 230 phy-handle = <&sw_phy3>; 231 phy-mode = "internal"; 232 local-mac-address = [00 00 00 00 00 00]; 233 }; 234 235 port@5 { 236 reg = <5>; 237 ethernet = <&fec>; 238 phy-mode = "rgmii-id"; 239 240 fixed-link { 241 speed = <1000>; 242 full-duplex; 243 }; 244 }; 245 }; 246 }; 247 }; 248}; 249 250&i2c1 { 251 clock-frequency = <100000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c1>; 254 status = "okay"; 255 256 gsc: gsc@20 { 257 compatible = "gw,gsc"; 258 reg = <0x20>; 259 interrupt-parent = <&gpio1>; 260 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 261 interrupt-controller; 262 #interrupt-cells = <1>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 266 adc { 267 compatible = "gw,gsc-adc"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 channel@0 { 272 gw,mode = <0>; 273 reg = <0x00>; 274 label = "temp"; 275 }; 276 277 channel@2 { 278 gw,mode = <1>; 279 reg = <0x02>; 280 label = "vdd_vin"; 281 }; 282 283 channel@5 { 284 gw,mode = <1>; 285 reg = <0x05>; 286 label = "vdd_3p3"; 287 }; 288 289 channel@8 { 290 gw,mode = <1>; 291 reg = <0x08>; 292 label = "vdd_bat"; 293 }; 294 295 channel@b { 296 gw,mode = <1>; 297 reg = <0x0b>; 298 label = "vdd_5p0"; 299 }; 300 301 channel@e { 302 gw,mode = <1>; 303 reg = <0xe>; 304 label = "vdd_arm"; 305 }; 306 307 channel@11 { 308 gw,mode = <1>; 309 reg = <0x11>; 310 label = "vdd_soc"; 311 }; 312 313 channel@14 { 314 gw,mode = <1>; 315 reg = <0x14>; 316 label = "vdd_3p0"; 317 }; 318 319 channel@17 { 320 gw,mode = <1>; 321 reg = <0x17>; 322 label = "vdd_1p5"; 323 }; 324 325 channel@1d { 326 gw,mode = <1>; 327 reg = <0x1d>; 328 label = "vdd_1p8"; 329 }; 330 331 channel@20 { 332 gw,mode = <1>; 333 reg = <0x20>; 334 label = "vdd_an1"; 335 }; 336 337 channel@23 { 338 gw,mode = <1>; 339 reg = <0x23>; 340 label = "vdd_2p5"; 341 }; 342 }; 343 }; 344 345 gsc_gpio: gpio@23 { 346 compatible = "nxp,pca9555"; 347 reg = <0x23>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-parent = <&gsc>; 351 interrupts = <4>; 352 }; 353 354 eeprom1: eeprom@50 { 355 compatible = "atmel,24c02"; 356 reg = <0x50>; 357 pagesize = <16>; 358 }; 359 360 eeprom2: eeprom@51 { 361 compatible = "atmel,24c02"; 362 reg = <0x51>; 363 pagesize = <16>; 364 }; 365 366 eeprom3: eeprom@52 { 367 compatible = "atmel,24c02"; 368 reg = <0x52>; 369 pagesize = <16>; 370 }; 371 372 eeprom4: eeprom@53 { 373 compatible = "atmel,24c02"; 374 reg = <0x53>; 375 pagesize = <16>; 376 }; 377 378 dts1672: rtc@68 { 379 compatible = "dallas,ds1672"; 380 reg = <0x68>; 381 }; 382}; 383 384&i2c2 { 385 clock-frequency = <100000>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_i2c2>; 388 status = "okay"; 389 390 magn@1c { 391 compatible = "st,lsm9ds1-magn"; 392 reg = <0x1c>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_mag>; 395 interrupt-parent = <&gpio5>; 396 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 397 }; 398 399 ltc3676: pmic@3c { 400 compatible = "lltc,ltc3676"; 401 reg = <0x3c>; 402 interrupt-parent = <&gpio1>; 403 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 404 405 regulators { 406 /* VDD_SOC (1+R1/R2 = 1.635) */ 407 reg_vdd_soc: sw1 { 408 regulator-name = "vddsoc"; 409 regulator-min-microvolt = <674400>; 410 regulator-max-microvolt = <1308000>; 411 lltc,fb-voltage-divider = <127000 200000>; 412 regulator-ramp-delay = <7000>; 413 regulator-boot-on; 414 regulator-always-on; 415 }; 416 417 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 418 reg_1p8v: sw2 { 419 regulator-name = "vdd1p8"; 420 regulator-min-microvolt = <1033310>; 421 regulator-max-microvolt = <2004000>; 422 lltc,fb-voltage-divider = <301000 200000>; 423 regulator-ramp-delay = <7000>; 424 regulator-boot-on; 425 regulator-always-on; 426 }; 427 428 /* VDD_ARM (1+R1/R2 = 1.635) */ 429 reg_vdd_arm: sw3 { 430 regulator-name = "vddarm"; 431 regulator-min-microvolt = <674400>; 432 regulator-max-microvolt = <1308000>; 433 lltc,fb-voltage-divider = <127000 200000>; 434 regulator-ramp-delay = <7000>; 435 regulator-boot-on; 436 regulator-always-on; 437 }; 438 439 /* VDD_DDR (1+R1/R2 = 2.105) */ 440 reg_vdd_ddr: sw4 { 441 regulator-name = "vddddr"; 442 regulator-min-microvolt = <868310>; 443 regulator-max-microvolt = <1684000>; 444 lltc,fb-voltage-divider = <221000 200000>; 445 regulator-ramp-delay = <7000>; 446 regulator-boot-on; 447 regulator-always-on; 448 }; 449 450 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 451 reg_2p5v: ldo2 { 452 regulator-name = "vdd2p5"; 453 regulator-min-microvolt = <2490375>; 454 regulator-max-microvolt = <2490375>; 455 lltc,fb-voltage-divider = <487000 200000>; 456 regulator-boot-on; 457 regulator-always-on; 458 }; 459 460 /* VDD_HIGH (1+R1/R2 = 4.17) */ 461 reg_3p0v: ldo4 { 462 regulator-name = "vdd3p0"; 463 regulator-min-microvolt = <3023250>; 464 regulator-max-microvolt = <3023250>; 465 lltc,fb-voltage-divider = <634000 200000>; 466 regulator-boot-on; 467 regulator-always-on; 468 }; 469 }; 470 }; 471 472 crypto@60 { 473 compatible = "atmel,atecc508a"; 474 reg = <0x60>; 475 }; 476 477 imu@6a { 478 compatible = "st,lsm9ds1-imu"; 479 reg = <0x6a>; 480 st,drdy-int-pin = <1>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_imu>; 483 interrupt-parent = <&gpio4>; 484 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 485 }; 486}; 487 488&i2c3 { 489 clock-frequency = <100000>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pinctrl_i2c3>; 492 status = "okay"; 493 494 egalax_ts: touchscreen@4 { 495 compatible = "eeti,egalax_ts"; 496 reg = <0x04>; 497 interrupt-parent = <&gpio1>; 498 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 499 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 500 }; 501}; 502 503&ldb { 504 status = "okay"; 505 506 lvds-channel@0 { 507 fsl,data-mapping = "spwg"; 508 fsl,data-width = <18>; 509 status = "okay"; 510 511 display-timings { 512 native-mode = <&timing0>; 513 timing0: timing-hsd100pxn1 { 514 clock-frequency = <65000000>; 515 hactive = <1024>; 516 vactive = <768>; 517 hback-porch = <220>; 518 hfront-porch = <40>; 519 vback-porch = <21>; 520 vfront-porch = <7>; 521 hsync-len = <60>; 522 vsync-len = <10>; 523 }; 524 }; 525 }; 526}; 527 528&pcie { 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_pcie>; 531 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 532 status = "okay"; 533}; 534 535&pwm2 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 538 status = "disabled"; 539}; 540 541&pwm3 { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 544 status = "disabled"; 545}; 546 547&pwm4 { 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pinctrl_pwm4>; 550 status = "okay"; 551}; 552 553&uart1 { 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_uart1>; 556 status = "okay"; 557}; 558 559&uart2 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart2>; 562 status = "okay"; 563}; 564 565&uart3 { 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_uart3>; 568 uart-has-rtscts; 569 status = "okay"; 570}; 571 572&uart4 { 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pinctrl_uart4>; 575 uart-has-rtscts; 576 status = "okay"; 577}; 578 579&uart5 { 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pinctrl_uart5>; 582 status = "okay"; 583}; 584 585&usbotg { 586 vbus-supply = <®_usb_otg_vbus>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&pinctrl_usbotg>; 589 disable-over-current; 590 status = "okay"; 591}; 592 593&usbh1 { 594 vbus-supply = <®_usb_h1_vbus>; 595 status = "okay"; 596}; 597 598&usdhc3 { 599 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 600 pinctrl-0 = <&pinctrl_usdhc3>; 601 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 602 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 603 non-removable; 604 vmmc-supply = <®_3p3v>; 605 keep-power-in-suspend; 606 status = "okay"; 607}; 608 609&wdog1 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_wdog>; 612 fsl,ext-reset-output; 613}; 614 615&iomuxc { 616 pinctrl_enet: enetgrp { 617 fsl,pins = < 618 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 619 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 620 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 621 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 622 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 623 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 624 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 625 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 626 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 627 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 628 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 629 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 630 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 631 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 632 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 633 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 634 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 635 >; 636 }; 637 638 pinctrl_gpio_leds: gpioledsgrp { 639 fsl,pins = < 640 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 641 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 642 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 643 >; 644 }; 645 646 pinctrl_i2c1: i2c1grp { 647 fsl,pins = < 648 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 649 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 650 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 651 >; 652 }; 653 654 pinctrl_i2c2: i2c2grp { 655 fsl,pins = < 656 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 657 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 658 >; 659 }; 660 661 pinctrl_i2c3: i2c3grp { 662 fsl,pins = < 663 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 664 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 665 >; 666 }; 667 668 pinctrl_imu: imugrp { 669 fsl,pins = < 670 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 671 >; 672 }; 673 674 pinctrl_mag: maggrp { 675 fsl,pins = < 676 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 677 >; 678 }; 679 680 pinctrl_pcie: pciegrp { 681 fsl,pins = < 682 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 683 >; 684 }; 685 686 pinctrl_pmic: pmicgrp { 687 fsl,pins = < 688 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 689 >; 690 }; 691 692 pinctrl_pps: ppsgrp { 693 fsl,pins = < 694 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 695 >; 696 }; 697 698 pinctrl_pwm2: pwm2grp { 699 fsl,pins = < 700 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 701 >; 702 }; 703 704 pinctrl_pwm3: pwm3grp { 705 fsl,pins = < 706 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 707 >; 708 }; 709 710 pinctrl_pwm4: pwm4grp { 711 fsl,pins = < 712 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 713 >; 714 }; 715 716 pinctrl_uart1: uart1grp { 717 fsl,pins = < 718 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 719 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 720 >; 721 }; 722 723 pinctrl_uart2: uart2grp { 724 fsl,pins = < 725 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 726 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 727 >; 728 }; 729 730 pinctrl_uart3: uart3grp { 731 fsl,pins = < 732 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 733 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 734 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 735 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 736 >; 737 }; 738 739 pinctrl_uart4: uart4grp { 740 fsl,pins = < 741 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 742 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 743 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 744 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 745 >; 746 }; 747 748 pinctrl_uart5: uart5grp { 749 fsl,pins = < 750 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 751 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 752 >; 753 }; 754 755 pinctrl_usbotg: usbotggrp { 756 fsl,pins = < 757 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 758 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 759 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 760 >; 761 }; 762 763 pinctrl_usdhc3: usdhc3grp { 764 fsl,pins = < 765 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 766 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 767 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 768 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 769 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 770 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 771 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 772 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 773 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 774 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 775 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 776 >; 777 }; 778 779 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 780 fsl,pins = < 781 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 782 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 783 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 784 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 785 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 786 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 787 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 788 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 789 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 790 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 791 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 792 >; 793 }; 794 795 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 796 fsl,pins = < 797 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 798 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 799 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 800 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 801 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 802 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 803 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 804 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 805 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 806 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 807 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 808 >; 809 }; 810 811 pinctrl_wdog: wdoggrp { 812 fsl,pins = < 813 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 814 >; 815 }; 816}; 817