1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 chosen { 12 stdout-path = &uart2; 13 }; 14 15 backlight { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000 0>; 18 brightness-levels = < 19 0 1 2 3 4 5 6 7 8 9 20 10 11 12 13 14 15 16 17 18 19 21 20 21 22 23 24 25 26 27 28 29 22 30 31 32 33 34 35 36 37 38 39 23 40 41 42 43 44 45 46 47 48 49 24 50 51 52 53 54 55 56 57 58 59 25 60 61 62 63 64 65 66 67 68 69 26 70 71 72 73 74 75 76 77 78 79 27 80 81 82 83 84 85 86 87 88 89 28 90 91 92 93 94 95 96 97 98 99 29 100 30 >; 31 default-brightness-level = <100>; 32 }; 33 34 gpio-keys { 35 compatible = "gpio-keys"; 36 37 key-user-pb { 38 label = "user_pb"; 39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 40 linux,code = <BTN_0>; 41 }; 42 43 key-user-pb1x { 44 label = "user_pb1x"; 45 linux,code = <BTN_1>; 46 interrupt-parent = <&gsc>; 47 interrupts = <0>; 48 }; 49 50 key-erased { 51 label = "key-erased"; 52 linux,code = <BTN_2>; 53 interrupt-parent = <&gsc>; 54 interrupts = <1>; 55 }; 56 57 key-eeprom-wp { 58 label = "eeprom_wp"; 59 linux,code = <BTN_3>; 60 interrupt-parent = <&gsc>; 61 interrupts = <2>; 62 }; 63 64 key-tamper { 65 label = "tamper"; 66 linux,code = <BTN_4>; 67 interrupt-parent = <&gsc>; 68 interrupts = <5>; 69 }; 70 71 key-switch-hold { 72 label = "switch_hold"; 73 linux,code = <BTN_5>; 74 interrupt-parent = <&gsc>; 75 interrupts = <7>; 76 }; 77 }; 78 79 leds { 80 compatible = "gpio-leds"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_gpio_leds>; 83 84 led0: led-user1 { 85 label = "user1"; 86 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 87 default-state = "off"; 88 }; 89 }; 90 91 memory@10000000 { 92 device_type = "memory"; 93 reg = <0x10000000 0x40000000>; 94 }; 95 96 reg_5p0v: regulator-5p0v { 97 compatible = "regulator-fixed"; 98 regulator-name = "5P0V"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 regulator-always-on; 102 }; 103 104 reg_3p3v: regulator-3p3v { 105 compatible = "regulator-fixed"; 106 regulator-name = "3P3V"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-always-on; 110 }; 111 112 reg_2p5v: regulator-2p5v { 113 compatible = "regulator-fixed"; 114 regulator-name = "2P5V"; 115 regulator-min-microvolt = <2500000>; 116 regulator-max-microvolt = <2500000>; 117 regulator-always-on; 118 }; 119 120 reg_usb_h1_vbus: regulator-usb-h1-vbus { 121 compatible = "regulator-fixed"; 122 regulator-name = "usb_h1_vbus"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 gpio = <&gpio3 30 0>; 126 enable-active-high; 127 }; 128 129 reg_usb_otg_vbus: regulator-usb-otg-vbus { 130 compatible = "regulator-fixed"; 131 regulator-name = "usb_otg_vbus"; 132 regulator-min-microvolt = <5000000>; 133 regulator-max-microvolt = <5000000>; 134 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 135 enable-active-high; 136 }; 137 138 reg_12p0: regulator-12p0v { 139 compatible = "regulator-fixed"; 140 regulator-name = "12P0V"; 141 regulator-min-microvolt = <12000000>; 142 regulator-max-microvolt = <12000000>; 143 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 144 enable-active-high; 145 }; 146 147 sound { 148 compatible = "fsl,imx-audio-tlv320"; 149 model = "imx-tlv320"; 150 ssi-controller = <&ssi1>; 151 audio-codec = <&tlv320aic3105>; 152 /* routing of sink, source */ 153 audio-routing = 154 /* TLV320 LINE1L pin <-> Mic Jack connector */ 155 "LINE1L", "Mic Jack", 156 /* board Headphone Jack <-> HPOUT */ 157 "Headphone Jack", "HPLOUT", 158 "Headphone Jack", "HPROUT", 159 "Mic Jack", "Mic Bias"; 160 mux-int-port = <1>; 161 mux-ext-port = <6>; 162 }; 163}; 164 165&audmux { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_audmux>; 168 status = "okay"; 169}; 170 171&clks { 172 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 173 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 174 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 175 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 176}; 177 178&fec { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_enet>; 181 phy-mode = "rgmii-id"; 182 status = "okay"; 183}; 184 185&i2c1 { 186 clock-frequency = <100000>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_i2c1>; 189 status = "okay"; 190 191 gsc: gsc@20 { 192 compatible = "gw,gsc"; 193 reg = <0x20>; 194 interrupt-parent = <&gpio1>; 195 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 196 interrupt-controller; 197 #interrupt-cells = <1>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 adc { 202 compatible = "gw,gsc-adc"; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 206 channel@0 { 207 gw,mode = <0>; 208 reg = <0x00>; 209 label = "temp"; 210 }; 211 212 channel@2 { 213 gw,mode = <1>; 214 reg = <0x02>; 215 label = "vdd_vin"; 216 }; 217 218 channel@5 { 219 gw,mode = <1>; 220 reg = <0x05>; 221 label = "vdd_3p3"; 222 }; 223 224 channel@8 { 225 gw,mode = <1>; 226 reg = <0x08>; 227 label = "vdd_bat"; 228 }; 229 230 channel@b { 231 gw,mode = <1>; 232 reg = <0x0b>; 233 label = "vdd_5p0"; 234 }; 235 236 channel@e { 237 gw,mode = <1>; 238 reg = <0xe>; 239 label = "vdd_arm"; 240 }; 241 242 channel@11 { 243 gw,mode = <1>; 244 reg = <0x11>; 245 label = "vdd_soc"; 246 }; 247 248 channel@14 { 249 gw,mode = <1>; 250 reg = <0x14>; 251 label = "vdd_3p0"; 252 }; 253 254 channel@17 { 255 gw,mode = <1>; 256 reg = <0x17>; 257 label = "vdd_1p5"; 258 }; 259 260 channel@1d { 261 gw,mode = <1>; 262 reg = <0x1d>; 263 label = "vdd_1p8"; 264 }; 265 266 channel@20 { 267 gw,mode = <1>; 268 reg = <0x20>; 269 label = "vdd_an1"; 270 }; 271 272 channel@23 { 273 gw,mode = <1>; 274 reg = <0x23>; 275 label = "vdd_2p5"; 276 }; 277 }; 278 }; 279 280 gsc_gpio: gpio@23 { 281 compatible = "nxp,pca9555"; 282 reg = <0x23>; 283 gpio-controller; 284 #gpio-cells = <2>; 285 interrupt-parent = <&gsc>; 286 interrupts = <4>; 287 }; 288 289 eeprom1: eeprom@50 { 290 compatible = "atmel,24c02"; 291 reg = <0x50>; 292 pagesize = <16>; 293 }; 294 295 eeprom2: eeprom@51 { 296 compatible = "atmel,24c02"; 297 reg = <0x51>; 298 pagesize = <16>; 299 }; 300 301 eeprom3: eeprom@52 { 302 compatible = "atmel,24c02"; 303 reg = <0x52>; 304 pagesize = <16>; 305 }; 306 307 eeprom4: eeprom@53 { 308 compatible = "atmel,24c02"; 309 reg = <0x53>; 310 pagesize = <16>; 311 }; 312 313 dts1672: rtc@68 { 314 compatible = "dallas,ds1672"; 315 reg = <0x68>; 316 }; 317}; 318 319&i2c2 { 320 clock-frequency = <400000>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_i2c2>; 323 status = "okay"; 324 325 ltc3676: pmic@3c { 326 compatible = "lltc,ltc3676"; 327 reg = <0x3c>; 328 interrupt-parent = <&gpio1>; 329 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 330 331 regulators { 332 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 333 reg_1p8v: sw1 { 334 regulator-name = "vdd1p8"; 335 regulator-min-microvolt = <1033310>; 336 regulator-max-microvolt = <2004000>; 337 lltc,fb-voltage-divider = <301000 200000>; 338 regulator-ramp-delay = <7000>; 339 regulator-boot-on; 340 regulator-always-on; 341 }; 342 343 /* VDD_DDR (1+R1/R2 = 2.105) */ 344 reg_vdd_ddr: sw2 { 345 regulator-name = "vddddr"; 346 regulator-min-microvolt = <868310>; 347 regulator-max-microvolt = <1684000>; 348 lltc,fb-voltage-divider = <221000 200000>; 349 regulator-ramp-delay = <7000>; 350 regulator-boot-on; 351 regulator-always-on; 352 }; 353 354 /* VDD_ARM (1+R1/R2 = 1.635) */ 355 reg_vdd_arm: sw3 { 356 regulator-name = "vddarm"; 357 regulator-min-microvolt = <674400>; 358 regulator-max-microvolt = <1308000>; 359 lltc,fb-voltage-divider = <127000 200000>; 360 regulator-ramp-delay = <7000>; 361 regulator-boot-on; 362 regulator-always-on; 363 linux,phandle = <®_vdd_arm>; 364 }; 365 366 /* VDD_SOC (1+R1/R2 = 1.635) */ 367 reg_vdd_soc: sw4 { 368 regulator-name = "vddsoc"; 369 regulator-min-microvolt = <674400>; 370 regulator-max-microvolt = <1308000>; 371 lltc,fb-voltage-divider = <127000 200000>; 372 regulator-ramp-delay = <7000>; 373 regulator-boot-on; 374 regulator-always-on; 375 linux,phandle = <®_vdd_soc>; 376 }; 377 378 /* VDD_1P0 (1+R1/R2 = 1.38): */ 379 reg_1p0v: ldo2 { 380 regulator-name = "vdd1p0"; 381 regulator-min-microvolt = <1002777>; 382 regulator-max-microvolt = <1002777>; 383 lltc,fb-voltage-divider = <100000 261000>; 384 regulator-boot-on; 385 regulator-always-on; 386 }; 387 388 /* VDD_HIGH (1+R1/R2 = 4.17) */ 389 reg_3p0v: ldo4 { 390 regulator-name = "vdd3p0"; 391 regulator-min-microvolt = <3023250>; 392 regulator-max-microvolt = <3023250>; 393 lltc,fb-voltage-divider = <634000 200000>; 394 regulator-boot-on; 395 regulator-always-on; 396 }; 397 }; 398 }; 399}; 400 401&i2c3 { 402 clock-frequency = <400000>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_i2c3>; 405 status = "okay"; 406 407 tlv320aic3105: codec@18 { 408 compatible = "ti,tlv320aic3x"; 409 reg = <0x18>; 410 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 411 clocks = <&clks IMX6QDL_CLK_CKO>; 412 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 413 /* Regulators */ 414 DRVDD-supply = <®_3p3v>; 415 AVDD-supply = <®_3p3v>; 416 IOVDD-supply = <®_3p3v>; 417 DVDD-supply = <®_1p8v>; 418 }; 419 420 accelerometer@1d { 421 compatible = "fsl,mma8451"; 422 reg = <0x1d>; 423 interrupt-parent = <&gpio7>; 424 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 425 interrupt-names = "INT2"; 426 }; 427 428 /* headphone detect */ 429 ts3a227e@3b { 430 compatible = "ti,ts3a227e"; 431 reg = <0x3b>; 432 interrupt-parent = <&gpio5>; 433 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 434 ti,micbias = <4>; /* 2.5V micbias */ 435 }; 436}; 437 438&ldb { 439 status = "okay"; 440 441 lvds-channel@0 { 442 fsl,data-mapping = "spwg"; 443 fsl,data-width = <18>; 444 status = "okay"; 445 446 display-timings { 447 native-mode = <&timing0>; 448 timing0: timing-g101evn010 { 449 clock-frequency = <68930000>; 450 hactive = <1280>; 451 vactive = <800>; 452 hback-porch = <220>; 453 hfront-porch = <40>; 454 vback-porch = <21>; 455 vfront-porch = <7>; 456 hsync-len = <60>; 457 vsync-len = <10>; 458 }; 459 }; 460 }; 461}; 462 463&pwm1 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_pwm1>; 466 status = "okay"; 467}; 468 469&ssi1 { 470 status = "okay"; 471}; 472 473&uart1 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_uart1>; 476 status = "okay"; 477}; 478 479&uart2 { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_uart2>; 482 status = "okay"; 483}; 484 485&usbotg { 486 vbus-supply = <®_usb_otg_vbus>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_usbotg>; 489 disable-over-current; 490 status = "okay"; 491}; 492 493&usbh1 { 494 vbus-supply = <®_usb_h1_vbus>; 495 status = "okay"; 496}; 497 498&usdhc1 { 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 501 vmmc-supply = <®_3p3v>; 502 non-removable; 503 bus-width = <4>; 504 status = "okay"; 505}; 506 507&usdhc2 { 508 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 509 pinctrl-0 = <&pinctrl_usdhc2>; 510 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 511 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 512 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 513 vmmc-supply = <®_3p3v>; 514 max-frequency = <100000000>; 515 status = "okay"; 516}; 517 518&usdhc3 { 519 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 520 pinctrl-0 = <&pinctrl_usdhc3>; 521 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 522 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 523 non-removable; 524 vmmc-supply = <®_3p3v>; 525 keep-power-in-suspend; 526 status = "okay"; 527}; 528 529&wdog1 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_wdog>; 532 fsl,ext-reset-output; 533}; 534 535&iomuxc { 536 pinctrl_audmux: audmuxgrp { 537 fsl,pins = < 538 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 539 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 540 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 541 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 542 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 543 >; 544 }; 545 546 pinctrl_enet: enetgrp { 547 fsl,pins = < 548 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 549 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 550 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 551 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 552 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 553 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 554 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 555 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 556 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 557 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 558 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 559 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 560 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 561 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 562 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 563 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 564 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 565 >; 566 }; 567 568 pinctrl_gpio_leds: gpioledsgrp { 569 fsl,pins = < 570 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 571 >; 572 }; 573 574 pinctrl_i2c1: i2c1grp { 575 fsl,pins = < 576 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 577 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 578 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 579 >; 580 }; 581 582 pinctrl_i2c2: i2c2grp { 583 fsl,pins = < 584 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 585 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 586 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 587 >; 588 }; 589 590 pinctrl_i2c3: i2c3grp { 591 fsl,pins = < 592 /* I2C3 */ 593 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 594 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 595 596 /* Headphone Detect */ 597 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 598 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 599 600 /* Codec */ 601 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 602 603 /* Touch Controller */ 604 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 605 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 606 607 /* Stow Sensor */ 608 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 609 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 610 >; 611 }; 612 613 pinctrl_pwm1: pwm1grp { 614 fsl,pins = < 615 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 616 >; 617 }; 618 619 pinctrl_uart1: uart1grp { 620 fsl,pins = < 621 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 622 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 623 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 624 >; 625 }; 626 627 pinctrl_uart2: uart2grp { 628 fsl,pins = < 629 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 630 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 631 >; 632 }; 633 634 pinctrl_usbotg: usbotggrp { 635 fsl,pins = < 636 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 637 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 638 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 639 >; 640 }; 641 642 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 643 fsl,pins = < 644 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 645 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 646 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 647 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 648 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 649 650 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 651 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 652 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 653 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 654 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 655 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 656 >; 657 }; 658 659 pinctrl_usdhc2: usdhc2grp { 660 fsl,pins = < 661 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 662 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 663 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 664 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 665 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 666 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 667 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 668 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 669 >; 670 }; 671 672 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 673 fsl,pins = < 674 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 675 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 676 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 677 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 678 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 679 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 680 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 681 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 682 >; 683 }; 684 685 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 686 fsl,pins = < 687 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 688 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 689 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 690 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 691 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 692 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 693 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 694 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 695 >; 696 }; 697 698 pinctrl_usdhc3: usdhc3grp { 699 fsl,pins = < 700 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 701 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 702 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 703 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 704 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 705 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 706 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 707 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 708 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 709 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 710 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 711 >; 712 }; 713 714 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 715 fsl,pins = < 716 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 717 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 718 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 719 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 720 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 721 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 722 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 723 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 724 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 725 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 726 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 727 >; 728 }; 729 730 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 731 fsl,pins = < 732 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 733 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 734 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 735 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 736 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 737 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 738 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 739 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 740 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 741 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 742 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 743 >; 744 }; 745 746 pinctrl_wdog: wdoggrp { 747 fsl,pins = < 748 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 749 >; 750 }; 751}; 752