1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 ssi0 = &ssi1; 17 usb0 = &usbh1; 18 usb1 = &usbotg; 19 }; 20 21 chosen { 22 stdout-path = &uart2; 23 }; 24 25 backlight-display { 26 compatible = "pwm-backlight"; 27 pwms = <&pwm4 0 5000000 0>; 28 brightness-levels = < 29 0 1 2 3 4 5 6 7 8 9 30 10 11 12 13 14 15 16 17 18 19 31 20 21 22 23 24 25 26 27 28 29 32 30 31 32 33 34 35 36 37 38 39 33 40 41 42 43 44 45 46 47 48 49 34 50 51 52 53 54 55 56 57 58 59 35 60 61 62 63 64 65 66 67 68 69 36 70 71 72 73 74 75 76 77 78 79 37 80 81 82 83 84 85 86 87 88 89 38 90 91 92 93 94 95 96 97 98 99 39 100 40 >; 41 default-brightness-level = <100>; 42 }; 43 44 backlight-keypad { 45 compatible = "gpio-backlight"; 46 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 47 default-on; 48 }; 49 50 gpio-keys { 51 compatible = "gpio-keys"; 52 53 key-user-pb { 54 label = "user_pb"; 55 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 56 linux,code = <BTN_0>; 57 }; 58 59 key-user-pb1x { 60 label = "user_pb1x"; 61 linux,code = <BTN_1>; 62 interrupt-parent = <&gsc>; 63 interrupts = <0>; 64 }; 65 66 key-erased { 67 label = "key-erased"; 68 linux,code = <BTN_2>; 69 interrupt-parent = <&gsc>; 70 interrupts = <1>; 71 }; 72 73 key-eeprom-wp { 74 label = "eeprom_wp"; 75 linux,code = <BTN_3>; 76 interrupt-parent = <&gsc>; 77 interrupts = <2>; 78 }; 79 80 key-tamper { 81 label = "tamper"; 82 linux,code = <BTN_4>; 83 interrupt-parent = <&gsc>; 84 interrupts = <5>; 85 }; 86 87 key-switch-hold { 88 label = "switch_hold"; 89 linux,code = <BTN_5>; 90 interrupt-parent = <&gsc>; 91 interrupts = <7>; 92 }; 93 }; 94 95 leds { 96 compatible = "gpio-leds"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_gpio_leds>; 99 100 led0: led-user1 { 101 label = "user1"; 102 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 103 default-state = "on"; 104 linux,default-trigger = "heartbeat"; 105 }; 106 107 led1: led-user2 { 108 label = "user2"; 109 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 110 default-state = "off"; 111 }; 112 113 led2: led-user3 { 114 label = "user3"; 115 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 116 default-state = "off"; 117 }; 118 }; 119 120 memory@10000000 { 121 device_type = "memory"; 122 reg = <0x10000000 0x40000000>; 123 }; 124 125 pps { 126 compatible = "pps-gpio"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_pps>; 129 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 130 }; 131 132 reg_2p5v: regulator-2p5v { 133 compatible = "regulator-fixed"; 134 regulator-name = "2P5V"; 135 regulator-min-microvolt = <2500000>; 136 regulator-max-microvolt = <2500000>; 137 regulator-always-on; 138 }; 139 140 reg_3p3v: regulator-3p3v { 141 compatible = "regulator-fixed"; 142 regulator-name = "3P3V"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 regulator-always-on; 146 }; 147 148 reg_5p0v: regulator-5p0v { 149 compatible = "regulator-fixed"; 150 regulator-name = "5P0V"; 151 regulator-min-microvolt = <5000000>; 152 regulator-max-microvolt = <5000000>; 153 regulator-always-on; 154 }; 155 156 reg_12p0v: regulator-12p0v { 157 compatible = "regulator-fixed"; 158 regulator-name = "12P0V"; 159 regulator-min-microvolt = <12000000>; 160 regulator-max-microvolt = <12000000>; 161 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 162 enable-active-high; 163 }; 164 165 reg_1p4v: regulator-vddsoc { 166 compatible = "regulator-fixed"; 167 regulator-name = "vdd_soc"; 168 regulator-min-microvolt = <1400000>; 169 regulator-max-microvolt = <1400000>; 170 regulator-always-on; 171 }; 172 173 reg_usb_h1_vbus: regulator-usb-h1-vbus { 174 compatible = "regulator-fixed"; 175 regulator-name = "usb_h1_vbus"; 176 regulator-min-microvolt = <5000000>; 177 regulator-max-microvolt = <5000000>; 178 regulator-always-on; 179 }; 180 181 reg_usb_otg_vbus: regulator-usb-otg-vbus { 182 compatible = "regulator-fixed"; 183 regulator-name = "usb_otg_vbus"; 184 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>; 186 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 187 enable-active-high; 188 }; 189 190 sound { 191 compatible = "fsl,imx6q-ventana-sgtl5000", 192 "fsl,imx-audio-sgtl5000"; 193 model = "sgtl5000-audio"; 194 ssi-controller = <&ssi1>; 195 audio-codec = <&sgtl5000>; 196 audio-routing = 197 "MIC_IN", "Mic Jack", 198 "Mic Jack", "Mic Bias", 199 "Headphone Jack", "HP_OUT"; 200 mux-int-port = <1>; 201 mux-ext-port = <4>; 202 }; 203}; 204 205&audmux { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_audmux>; 208 status = "okay"; 209}; 210 211&ecspi3 { 212 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_ecspi3>; 215 status = "okay"; 216}; 217 218&can1 { 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_flexcan>; 221 status = "okay"; 222}; 223 224&clks { 225 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 226 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 227 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 228 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 229}; 230 231&fec { 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_enet>; 234 phy-mode = "rgmii-id"; 235 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 236 status = "okay"; 237}; 238 239&hdmi { 240 ddc-i2c-bus = <&i2c3>; 241 status = "okay"; 242}; 243 244&i2c1 { 245 clock-frequency = <100000>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_i2c1>; 248 status = "okay"; 249 250 gsc: gsc@20 { 251 compatible = "gw,gsc"; 252 reg = <0x20>; 253 interrupt-parent = <&gpio1>; 254 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 255 interrupt-controller; 256 #interrupt-cells = <1>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 adc { 261 compatible = "gw,gsc-adc"; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 channel@0 { 266 gw,mode = <0>; 267 reg = <0x00>; 268 label = "temp"; 269 }; 270 271 channel@2 { 272 gw,mode = <1>; 273 reg = <0x02>; 274 label = "vdd_vin"; 275 }; 276 277 channel@5 { 278 gw,mode = <1>; 279 reg = <0x05>; 280 label = "vdd_3p3"; 281 }; 282 283 channel@8 { 284 gw,mode = <1>; 285 reg = <0x08>; 286 label = "vdd_bat"; 287 }; 288 289 channel@b { 290 gw,mode = <1>; 291 reg = <0x0b>; 292 label = "vdd_5p0"; 293 }; 294 295 channel@e { 296 gw,mode = <1>; 297 reg = <0xe>; 298 label = "vdd_arm"; 299 }; 300 301 channel@11 { 302 gw,mode = <1>; 303 reg = <0x11>; 304 label = "vdd_soc"; 305 }; 306 307 channel@14 { 308 gw,mode = <1>; 309 reg = <0x14>; 310 label = "vdd_3p0"; 311 }; 312 313 channel@17 { 314 gw,mode = <1>; 315 reg = <0x17>; 316 label = "vdd_1p5"; 317 }; 318 319 channel@1d { 320 gw,mode = <1>; 321 reg = <0x1d>; 322 label = "vdd_1p8"; 323 }; 324 325 channel@20 { 326 gw,mode = <1>; 327 reg = <0x20>; 328 label = "vdd_an1"; 329 }; 330 331 channel@23 { 332 gw,mode = <1>; 333 reg = <0x23>; 334 label = "vdd_2p5"; 335 }; 336 337 channel@26 { 338 gw,mode = <1>; 339 reg = <0x26>; 340 label = "vdd_gps"; 341 }; 342 343 channel@29 { 344 gw,mode = <1>; 345 reg = <0x29>; 346 label = "vdd_an2"; 347 }; 348 }; 349 }; 350 351 gsc_gpio: gpio@23 { 352 compatible = "nxp,pca9555"; 353 reg = <0x23>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-parent = <&gsc>; 357 interrupts = <4>; 358 }; 359 360 eeprom1: eeprom@50 { 361 compatible = "atmel,24c02"; 362 reg = <0x50>; 363 pagesize = <16>; 364 }; 365 366 eeprom2: eeprom@51 { 367 compatible = "atmel,24c02"; 368 reg = <0x51>; 369 pagesize = <16>; 370 }; 371 372 eeprom3: eeprom@52 { 373 compatible = "atmel,24c02"; 374 reg = <0x52>; 375 pagesize = <16>; 376 }; 377 378 eeprom4: eeprom@53 { 379 compatible = "atmel,24c02"; 380 reg = <0x53>; 381 pagesize = <16>; 382 }; 383 384 ds1672: rtc@68 { 385 compatible = "dallas,ds1672"; 386 reg = <0x68>; 387 }; 388}; 389 390&i2c2 { 391 clock-frequency = <100000>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_i2c2>; 394 status = "okay"; 395 396 sgtl5000: codec@a { 397 compatible = "fsl,sgtl5000"; 398 reg = <0x0a>; 399 #sound-dai-cells = <0>; 400 clocks = <&clks IMX6QDL_CLK_CKO>; 401 VDDA-supply = <®_1p8v>; 402 VDDIO-supply = <®_3p3v>; 403 }; 404 405 magn@1c { 406 compatible = "st,lsm9ds1-magn"; 407 reg = <0x1c>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_mag>; 410 interrupt-parent = <&gpio5>; 411 interrupts = <9 IRQ_TYPE_EDGE_RISING>; 412 }; 413 414 tca8418: keypad@34 { 415 compatible = "ti,tca8418"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_keypad>; 418 reg = <0x34>; 419 interrupt-parent = <&gpio5>; 420 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 421 linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) 422 MATRIX_KEY(0x00, 0x00, BTN_1) 423 MATRIX_KEY(0x01, 0x01, BTN_2) 424 MATRIX_KEY(0x01, 0x00, BTN_3) 425 MATRIX_KEY(0x02, 0x00, BTN_4) 426 MATRIX_KEY(0x00, 0x03, BTN_5) 427 MATRIX_KEY(0x00, 0x02, BTN_6) 428 MATRIX_KEY(0x01, 0x03, BTN_7) 429 MATRIX_KEY(0x01, 0x02, BTN_8) 430 MATRIX_KEY(0x02, 0x02, BTN_9) 431 >; 432 keypad,num-rows = <4>; 433 keypad,num-columns = <4>; 434 }; 435 436 ltc3676: pmic@3c { 437 compatible = "lltc,ltc3676"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_pmic>; 440 reg = <0x3c>; 441 interrupt-parent = <&gpio1>; 442 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 443 444 regulators { 445 /* VDD_DDR (1+R1/R2 = 2.105) */ 446 reg_vdd_ddr: sw2 { 447 regulator-name = "vddddr"; 448 regulator-min-microvolt = <868310>; 449 regulator-max-microvolt = <1684000>; 450 lltc,fb-voltage-divider = <221000 200000>; 451 regulator-ramp-delay = <7000>; 452 regulator-boot-on; 453 regulator-always-on; 454 }; 455 456 /* VDD_ARM (1+R1/R2 = 1.931) */ 457 reg_vdd_arm: sw3 { 458 regulator-name = "vddarm"; 459 regulator-min-microvolt = <796551>; 460 regulator-max-microvolt = <1544827>; 461 lltc,fb-voltage-divider = <243000 261000>; 462 regulator-ramp-delay = <7000>; 463 regulator-boot-on; 464 regulator-always-on; 465 linux,phandle = <®_vdd_arm>; 466 }; 467 468 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 469 reg_1p8v: sw4 { 470 regulator-name = "vdd1p8"; 471 regulator-min-microvolt = <1033310>; 472 regulator-max-microvolt = <2004000>; 473 lltc,fb-voltage-divider = <301000 200000>; 474 regulator-ramp-delay = <7000>; 475 regulator-boot-on; 476 regulator-always-on; 477 }; 478 479 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ 480 reg_1p0v: ldo2 { 481 regulator-name = "vdd1p0"; 482 regulator-min-microvolt = <950000>; 483 regulator-max-microvolt = <1050000>; 484 lltc,fb-voltage-divider = <78700 200000>; 485 regulator-boot-on; 486 regulator-always-on; 487 }; 488 489 /* VDD_AUD_1P8: Audio codec */ 490 reg_aud_1p8v: ldo3 { 491 regulator-name = "vdd1p8a"; 492 regulator-min-microvolt = <1800000>; 493 regulator-max-microvolt = <1800000>; 494 regulator-boot-on; 495 }; 496 497 /* VDD_HIGH (1+R1/R2 = 4.17) */ 498 reg_3p0v: ldo4 { 499 regulator-name = "vdd3p0"; 500 regulator-min-microvolt = <3023250>; 501 regulator-max-microvolt = <3023250>; 502 lltc,fb-voltage-divider = <634000 200000>; 503 regulator-boot-on; 504 regulator-always-on; 505 }; 506 }; 507 }; 508 509 imu@6a { 510 compatible = "st,lsm9ds1-imu"; 511 reg = <0x6a>; 512 st,drdy-int-pin = <1>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pinctrl_imu>; 515 interrupt-parent = <&gpio5>; 516 interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; 517 }; 518}; 519 520&i2c3 { 521 clock-frequency = <100000>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pinctrl_i2c3>; 524 status = "okay"; 525 526 egalax_ts: touchscreen@4 { 527 compatible = "eeti,egalax_ts"; 528 reg = <0x04>; 529 interrupt-parent = <&gpio5>; 530 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 531 wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 532 }; 533}; 534 535&ldb { 536 fsl,dual-channel; 537 status = "okay"; 538 539 lvds-channel@0 { 540 fsl,data-mapping = "spwg"; 541 fsl,data-width = <18>; 542 status = "okay"; 543 544 display-timings { 545 native-mode = <&timing0>; 546 timing0: timing-hsd100pxn1 { 547 clock-frequency = <65000000>; 548 hactive = <1024>; 549 vactive = <768>; 550 hback-porch = <220>; 551 hfront-porch = <40>; 552 vback-porch = <21>; 553 vfront-porch = <7>; 554 hsync-len = <60>; 555 vsync-len = <10>; 556 }; 557 }; 558 }; 559}; 560 561&pcie { 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_pcie>; 564 reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; 565 status = "okay"; 566}; 567 568&pwm2 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 571 status = "disabled"; 572}; 573 574&pwm3 { 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 577 status = "disabled"; 578}; 579 580&pwm4 { 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pinctrl_pwm4>; 583 status = "okay"; 584}; 585 586&ssi1 { 587 status = "okay"; 588}; 589 590&uart1 { 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pinctrl_uart1>; 593 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 594 status = "okay"; 595}; 596 597&uart2 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_uart2>; 600 status = "okay"; 601}; 602 603&uart5 { 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_uart5>; 606 status = "okay"; 607}; 608 609&usbotg { 610 vbus-supply = <®_usb_otg_vbus>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pinctrl_usbotg>; 613 disable-over-current; 614 status = "okay"; 615}; 616 617&usbh1 { 618 vbus-supply = <®_usb_h1_vbus>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_usbh1>; 621 status = "okay"; 622}; 623 624&usdhc2 { 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pinctrl_usdhc2>; 627 bus-width = <8>; 628 vmmc-supply = <®_3p3v>; 629 non-removable; 630 status = "okay"; 631}; 632 633&usdhc3 { 634 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 635 pinctrl-0 = <&pinctrl_usdhc3>; 636 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 637 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 638 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 639 vmmc-supply = <®_3p3v>; 640 status = "okay"; 641}; 642 643&wdog1 { 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_wdog>; 646 fsl,ext-reset-output; 647}; 648 649&iomuxc { 650 pinctrl_audmux: audmuxgrp { 651 fsl,pins = < 652 /* AUD4 */ 653 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 654 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 655 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 656 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 657 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 658 /* AUD6 */ 659 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 660 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 661 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 662 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 663 >; 664 }; 665 666 pinctrl_ecspi3: escpi3grp { 667 fsl,pins = < 668 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 669 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 670 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 671 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 672 >; 673 }; 674 675 pinctrl_enet: enetgrp { 676 fsl,pins = < 677 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 678 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 679 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 680 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 681 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 682 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 683 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 684 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 685 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 686 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 687 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 688 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 689 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 690 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 691 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 692 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 693 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 694 >; 695 }; 696 697 pinctrl_flexcan: flexcangrp { 698 fsl,pins = < 699 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 700 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 701 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 702 >; 703 }; 704 705 pinctrl_gpio_leds: gpioledsgrp { 706 fsl,pins = < 707 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 708 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 709 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 710 >; 711 }; 712 713 pinctrl_i2c1: i2c1grp { 714 fsl,pins = < 715 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 716 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 717 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 718 >; 719 }; 720 721 pinctrl_i2c2: i2c2grp { 722 fsl,pins = < 723 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 724 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 725 >; 726 }; 727 728 pinctrl_i2c3: i2c3grp { 729 fsl,pins = < 730 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 731 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 732 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ 733 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ 734 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ 735 >; 736 }; 737 738 pinctrl_imu: imugrp { 739 fsl,pins = < 740 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 741 >; 742 }; 743 744 pinctrl_keypad: keypadgrp { 745 fsl,pins = < 746 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ 747 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ 748 >; 749 }; 750 751 pinctrl_mag: maggrp { 752 fsl,pins = < 753 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 754 >; 755 }; 756 757 pinctrl_pcie: pciegrp { 758 fsl,pins = < 759 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ 760 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 761 >; 762 }; 763 764 pinctrl_pmic: pmicgrp { 765 fsl,pins = < 766 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 767 >; 768 }; 769 770 pinctrl_pps: ppsgrp { 771 fsl,pins = < 772 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 773 >; 774 }; 775 776 pinctrl_pwm2: pwm2grp { 777 fsl,pins = < 778 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 779 >; 780 }; 781 782 pinctrl_pwm3: pwm3grp { 783 fsl,pins = < 784 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 785 >; 786 }; 787 788 pinctrl_pwm4: pwm4grp { 789 fsl,pins = < 790 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 791 >; 792 }; 793 794 pinctrl_uart1: uart1grp { 795 fsl,pins = < 796 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 797 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 798 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 799 >; 800 }; 801 802 pinctrl_uart2: uart2grp { 803 fsl,pins = < 804 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 805 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 806 >; 807 }; 808 809 pinctrl_uart5: uart5grp { 810 fsl,pins = < 811 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 812 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 813 >; 814 }; 815 816 pinctrl_usbh1: usbh1grp { 817 fsl,pins = < 818 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ 819 >; 820 }; 821 822 pinctrl_usbotg: usbotggrp { 823 fsl,pins = < 824 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 825 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 826 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 827 >; 828 }; 829 830 pinctrl_usdhc2: usdhc2grp { 831 fsl,pins = < 832 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 833 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 834 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 835 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 836 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 837 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 838 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 839 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 840 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 841 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 842 >; 843 }; 844 845 pinctrl_usdhc3: usdhc3grp { 846 fsl,pins = < 847 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 848 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 849 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 850 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 851 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 852 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 853 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 854 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 855 >; 856 }; 857 858 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 859 fsl,pins = < 860 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 861 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 862 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 863 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 864 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 865 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 866 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 867 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 868 >; 869 }; 870 871 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 872 fsl,pins = < 873 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 874 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 875 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 876 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 877 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 878 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 879 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 880 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 881 >; 882 }; 883 884 pinctrl_wdog: wdoggrp { 885 fsl,pins = < 886 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 887 >; 888 }; 889}; 890