1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2016 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 nand = &gpmi; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 stdout-path = &uart2; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 27 key-user-pb { 28 label = "user_pb"; 29 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 30 linux,code = <BTN_0>; 31 }; 32 33 key-user-pb1x { 34 label = "user_pb1x"; 35 linux,code = <BTN_1>; 36 interrupt-parent = <&gsc>; 37 interrupts = <0>; 38 }; 39 40 key-erased { 41 label = "key-erased"; 42 linux,code = <BTN_2>; 43 interrupt-parent = <&gsc>; 44 interrupts = <1>; 45 }; 46 47 key-eeprom-wp { 48 label = "eeprom_wp"; 49 linux,code = <BTN_3>; 50 interrupt-parent = <&gsc>; 51 interrupts = <2>; 52 }; 53 54 key-tamper { 55 label = "tamper"; 56 linux,code = <BTN_4>; 57 interrupt-parent = <&gsc>; 58 interrupts = <5>; 59 }; 60 61 key-switch-hold { 62 label = "switch_hold"; 63 linux,code = <BTN_5>; 64 interrupt-parent = <&gsc>; 65 interrupts = <7>; 66 }; 67 }; 68 69 leds { 70 compatible = "gpio-leds"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_leds>; 73 74 led0: led-user1 { 75 label = "user1"; 76 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 77 default-state = "on"; 78 linux,default-trigger = "heartbeat"; 79 }; 80 81 led1: led-user2 { 82 label = "user2"; 83 gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 84 default-state = "off"; 85 }; 86 }; 87 88 memory@10000000 { 89 device_type = "memory"; 90 reg = <0x10000000 0x20000000>; 91 }; 92 93 pps { 94 compatible = "pps-gpio"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pps>; 97 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 98 status = "okay"; 99 }; 100 101 reg_5p0v: regulator-5p0v { 102 compatible = "regulator-fixed"; 103 regulator-name = "5P0V"; 104 regulator-min-microvolt = <5000000>; 105 regulator-max-microvolt = <5000000>; 106 regulator-always-on; 107 }; 108 109 reg_usb_otg_vbus: regulator-usb-otg-vbus { 110 compatible = "regulator-fixed"; 111 regulator-name = "usb_otg_vbus"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117}; 118 119&gpmi { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_gpmi_nand>; 122 status = "okay"; 123}; 124 125&hdmi { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_hdmi>; 128 ddc-i2c-bus = <&i2c3>; 129 status = "okay"; 130}; 131 132&i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_i2c1>; 136 status = "okay"; 137 138 gsc: gsc@20 { 139 compatible = "gw,gsc"; 140 reg = <0x20>; 141 interrupt-parent = <&gpio1>; 142 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 143 interrupt-controller; 144 #interrupt-cells = <1>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 148 adc { 149 compatible = "gw,gsc-adc"; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 channel@0 { 154 gw,mode = <0>; 155 reg = <0x00>; 156 label = "temp"; 157 }; 158 159 channel@2 { 160 gw,mode = <1>; 161 reg = <0x02>; 162 label = "vdd_vin"; 163 }; 164 165 channel@5 { 166 gw,mode = <1>; 167 reg = <0x05>; 168 label = "vdd_3p3"; 169 }; 170 171 channel@8 { 172 gw,mode = <1>; 173 reg = <0x08>; 174 label = "vdd_bat"; 175 }; 176 177 channel@b { 178 gw,mode = <1>; 179 reg = <0x0b>; 180 label = "vdd_5p0"; 181 }; 182 183 channel@e { 184 gw,mode = <1>; 185 reg = <0xe>; 186 label = "vdd_arm"; 187 }; 188 189 channel@11 { 190 gw,mode = <1>; 191 reg = <0x11>; 192 label = "vdd_soc"; 193 }; 194 195 channel@14 { 196 gw,mode = <1>; 197 reg = <0x14>; 198 label = "vdd_3p0"; 199 }; 200 201 channel@17 { 202 gw,mode = <1>; 203 reg = <0x17>; 204 label = "vdd_1p5"; 205 }; 206 207 channel@1d { 208 gw,mode = <1>; 209 reg = <0x1d>; 210 label = "vdd_1p8a"; 211 }; 212 213 channel@20 { 214 gw,mode = <1>; 215 reg = <0x20>; 216 label = "vdd_1p0b"; 217 }; 218 219 channel@26 { 220 gw,mode = <1>; 221 reg = <0x26>; 222 label = "vdd_an1"; 223 }; 224 }; 225 }; 226 227 gsc_gpio: gpio@23 { 228 compatible = "nxp,pca9555"; 229 reg = <0x23>; 230 gpio-controller; 231 #gpio-cells = <2>; 232 interrupt-parent = <&gsc>; 233 interrupts = <4>; 234 }; 235 236 eeprom1: eeprom@50 { 237 compatible = "atmel,24c02"; 238 reg = <0x50>; 239 pagesize = <16>; 240 }; 241 242 eeprom2: eeprom@51 { 243 compatible = "atmel,24c02"; 244 reg = <0x51>; 245 pagesize = <16>; 246 }; 247 248 eeprom3: eeprom@52 { 249 compatible = "atmel,24c02"; 250 reg = <0x52>; 251 pagesize = <16>; 252 }; 253 254 eeprom4: eeprom@53 { 255 compatible = "atmel,24c02"; 256 reg = <0x53>; 257 pagesize = <16>; 258 }; 259 260 rtc: rtc@68 { 261 compatible = "dallas,ds1672"; 262 reg = <0x68>; 263 }; 264}; 265 266&i2c2 { 267 clock-frequency = <100000>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_i2c2>; 270 status = "okay"; 271 272 magn@1c { 273 compatible = "st,lsm9ds1-magn"; 274 reg = <0x1c>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_mag>; 277 interrupt-parent = <&gpio1>; 278 interrupts = <2 IRQ_TYPE_EDGE_RISING>; 279 }; 280 281 imu@6a { 282 compatible = "st,lsm9ds1-imu"; 283 reg = <0x6a>; 284 st,drdy-int-pin = <1>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_imu>; 287 interrupt-parent = <&gpio7>; 288 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 ltc3676: pmic@3c { 292 compatible = "lltc,ltc3676"; 293 reg = <0x3c>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_pmic>; 296 interrupt-parent = <&gpio1>; 297 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 298 299 regulators { 300 /* VDD_SOC (1+R1/R2 = 1.635) */ 301 reg_vdd_soc: sw1 { 302 regulator-name = "vddsoc"; 303 regulator-min-microvolt = <674400>; 304 regulator-max-microvolt = <1308000>; 305 lltc,fb-voltage-divider = <127000 200000>; 306 regulator-ramp-delay = <7000>; 307 regulator-boot-on; 308 regulator-always-on; 309 }; 310 311 /* VDD_DDR (1+R1/R2 = 2.105) */ 312 reg_vdd_ddr: sw2 { 313 regulator-name = "vddddr"; 314 regulator-min-microvolt = <868310>; 315 regulator-max-microvolt = <1684000>; 316 lltc,fb-voltage-divider = <221000 200000>; 317 regulator-ramp-delay = <7000>; 318 regulator-boot-on; 319 regulator-always-on; 320 }; 321 322 /* VDD_ARM (1+R1/R2 = 1.635) */ 323 reg_vdd_arm: sw3 { 324 regulator-name = "vddarm"; 325 regulator-min-microvolt = <674400>; 326 regulator-max-microvolt = <1308000>; 327 lltc,fb-voltage-divider = <127000 200000>; 328 regulator-ramp-delay = <7000>; 329 regulator-boot-on; 330 regulator-always-on; 331 }; 332 333 /* VDD_3P3 (1+R1/R2 = 1.281) */ 334 reg_3p3v: sw4 { 335 regulator-name = "vdd3p3"; 336 regulator-min-microvolt = <1880000>; 337 regulator-max-microvolt = <3647000>; 338 lltc,fb-voltage-divider = <200000 56200>; 339 regulator-ramp-delay = <7000>; 340 regulator-boot-on; 341 regulator-always-on; 342 }; 343 344 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ 345 reg_1p8a: ldo2 { 346 regulator-name = "vdd1p8a"; 347 regulator-min-microvolt = <1816125>; 348 regulator-max-microvolt = <1816125>; 349 lltc,fb-voltage-divider = <301000 200000>; 350 regulator-boot-on; 351 regulator-always-on; 352 }; 353 354 /* VDD_1P8b: microSD VDD_1P8 */ 355 reg_1p8b: ldo3 { 356 regulator-name = "vdd1p8b"; 357 regulator-min-microvolt = <1800000>; 358 regulator-max-microvolt = <1800000>; 359 regulator-boot-on; 360 }; 361 362 /* VDD_HIGH (1+R1/R2 = 4.17) */ 363 reg_3p0v: ldo4 { 364 regulator-name = "vdd3p0"; 365 regulator-min-microvolt = <3023250>; 366 regulator-max-microvolt = <3023250>; 367 lltc,fb-voltage-divider = <634000 200000>; 368 regulator-boot-on; 369 regulator-always-on; 370 }; 371 }; 372 }; 373}; 374 375&i2c3 { 376 clock-frequency = <100000>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_i2c3>; 379 status = "okay"; 380 381 adv7180: camera@20 { 382 compatible = "adi,adv7180"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_adv7180>; 385 reg = <0x20>; 386 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 387 interrupt-parent = <&gpio5>; 388 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 389 390 port { 391 adv7180_to_ipu1_csi0_mux: endpoint { 392 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 393 bus-width = <8>; 394 }; 395 }; 396 }; 397}; 398 399&ipu1_csi0_from_ipu1_csi0_mux { 400 bus-width = <8>; 401}; 402 403&ipu1_csi0_mux_from_parallel_sensor { 404 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 405 bus-width = <8>; 406}; 407 408&ipu1_csi0 { 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_ipu1_csi0>; 411}; 412 413&pcie { 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_pcie>; 416 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 417 status = "okay"; 418}; 419 420&pwm2 { 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 423 status = "disabled"; 424}; 425 426&pwm3 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 429 status = "disabled"; 430}; 431 432&pwm4 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 435 status = "disabled"; 436}; 437 438&uart2 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_uart2>; 441 status = "okay"; 442}; 443 444&uart3 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_uart3>; 447 status = "okay"; 448}; 449 450&uart4 { 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_uart4>; 453 status = "okay"; 454}; 455 456&uart5 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_uart5>; 459 status = "okay"; 460}; 461 462&usbh1 { 463 status = "okay"; 464}; 465 466&usbotg { 467 vbus-supply = <®_usb_otg_vbus>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_usbotg>; 470 disable-over-current; 471 status = "okay"; 472}; 473 474&usdhc3 { 475 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 476 pinctrl-0 = <&pinctrl_usdhc3>; 477 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 478 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 479 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 480 status = "okay"; 481}; 482 483&wdog1 { 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pinctrl_wdog>; 486 fsl,ext-reset-output; 487}; 488 489&iomuxc { 490 pinctrl_adv7180: adv7180grp { 491 fsl,pins = < 492 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 493 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 494 >; 495 }; 496 497 pinctrl_gpmi_nand: gpminandgrp { 498 fsl,pins = < 499 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 500 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 501 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 502 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 503 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 504 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 505 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 506 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 507 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 508 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 509 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 510 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 511 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 512 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 513 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 514 >; 515 }; 516 517 pinctrl_hdmi: hdmigrp { 518 fsl,pins = < 519 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 520 >; 521 }; 522 523 pinctrl_i2c1: i2c1grp { 524 fsl,pins = < 525 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 526 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 527 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 528 >; 529 }; 530 531 pinctrl_i2c2: i2c2grp { 532 fsl,pins = < 533 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 534 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 535 >; 536 }; 537 538 pinctrl_i2c3: i2c3grp { 539 fsl,pins = < 540 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 541 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 542 >; 543 }; 544 545 pinctrl_imu: imugrp { 546 fsl,pins = < 547 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 548 >; 549 }; 550 551 pinctrl_ipu1_csi0: ipu1csi0grp { 552 fsl,pins = < 553 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 554 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 555 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 556 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 557 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 558 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 559 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 560 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 561 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 562 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 563 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 564 >; 565 }; 566 567 pinctrl_gpio_leds: gpioledsgrp { 568 fsl,pins = < 569 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 570 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 571 >; 572 }; 573 574 pinctrl_mag: maggrp { 575 fsl,pins = < 576 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 577 >; 578 }; 579 580 pinctrl_pcie: pciegrp { 581 fsl,pins = < 582 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 583 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 584 >; 585 }; 586 587 pinctrl_pmic: pmicgrp { 588 fsl,pins = < 589 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 590 >; 591 }; 592 593 pinctrl_pps: ppsgrp { 594 fsl,pins = < 595 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 596 >; 597 }; 598 599 pinctrl_pwm2: pwm2grp { 600 fsl,pins = < 601 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 602 >; 603 }; 604 605 pinctrl_pwm3: pwm3grp { 606 fsl,pins = < 607 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 608 >; 609 }; 610 611 pinctrl_pwm4: pwm4grp { 612 fsl,pins = < 613 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 614 >; 615 }; 616 617 pinctrl_uart2: uart2grp { 618 fsl,pins = < 619 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 620 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 621 >; 622 }; 623 624 pinctrl_uart3: uart3grp { 625 fsl,pins = < 626 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 627 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 628 >; 629 }; 630 631 pinctrl_uart4: uart4grp { 632 fsl,pins = < 633 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 634 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 635 >; 636 }; 637 638 pinctrl_uart5: uart5grp { 639 fsl,pins = < 640 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 641 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 642 >; 643 }; 644 645 pinctrl_usbotg: usbotggrp { 646 fsl,pins = < 647 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 648 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 649 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 650 >; 651 }; 652 653 pinctrl_usdhc3: usdhc3grp { 654 fsl,pins = < 655 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 656 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 657 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 658 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 659 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 660 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 661 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 662 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 663 >; 664 }; 665 666 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 667 fsl,pins = < 668 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 669 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 670 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 671 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 672 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 673 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 674 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 675 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 676 >; 677 }; 678 679 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 680 fsl,pins = < 681 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 682 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 683 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 684 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 685 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 686 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 687 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 688 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 689 >; 690 }; 691 692 pinctrl_wdog: wdoggrp { 693 fsl,pins = < 694 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 695 >; 696 }; 697}; 698