1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2014 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/media/tda1997x.h> 8#include <dt-bindings/input/linux-event-codes.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/sound/fsl-imx-audmux.h> 11 12/ { 13 /* these are used by bootloader for disabling nodes */ 14 aliases { 15 led0 = &led0; 16 nand = &gpmi; 17 ssi0 = &ssi1; 18 usb0 = &usbh1; 19 usb1 = &usbotg; 20 }; 21 22 chosen { 23 bootargs = "console=ttymxc1,115200"; 24 }; 25 26 gpio-keys { 27 compatible = "gpio-keys"; 28 29 key-user-pb { 30 label = "user_pb"; 31 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 32 linux,code = <BTN_0>; 33 }; 34 35 key-user-pb1x { 36 label = "user_pb1x"; 37 linux,code = <BTN_1>; 38 interrupt-parent = <&gsc>; 39 interrupts = <0>; 40 }; 41 42 key-erased { 43 label = "key-erased"; 44 linux,code = <BTN_2>; 45 interrupt-parent = <&gsc>; 46 interrupts = <1>; 47 }; 48 49 key-eeprom-wp { 50 label = "eeprom_wp"; 51 linux,code = <BTN_3>; 52 interrupt-parent = <&gsc>; 53 interrupts = <2>; 54 }; 55 56 key-tamper { 57 label = "tamper"; 58 linux,code = <BTN_4>; 59 interrupt-parent = <&gsc>; 60 interrupts = <5>; 61 }; 62 63 key-switch-hold { 64 label = "switch_hold"; 65 linux,code = <BTN_5>; 66 interrupt-parent = <&gsc>; 67 interrupts = <7>; 68 }; 69 }; 70 71 leds { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led0: led-user1 { 77 label = "user1"; 78 gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 79 default-state = "on"; 80 linux,default-trigger = "heartbeat"; 81 }; 82 }; 83 84 memory@10000000 { 85 device_type = "memory"; 86 reg = <0x10000000 0x20000000>; 87 }; 88 89 reg_5p0v: regulator-5p0v { 90 compatible = "regulator-fixed"; 91 regulator-name = "5P0V"; 92 regulator-min-microvolt = <5000000>; 93 regulator-max-microvolt = <5000000>; 94 }; 95 96 reg_usb_h1_vbus: regulator-usb-h1-vbus { 97 compatible = "regulator-fixed"; 98 regulator-name = "usb_h1_vbus"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 }; 102 103 reg_usb_otg_vbus: regulator-usb-otg-vbus { 104 compatible = "regulator-fixed"; 105 regulator-name = "usb_otg_vbus"; 106 regulator-min-microvolt = <5000000>; 107 regulator-max-microvolt = <5000000>; 108 }; 109 110 sound-digital { 111 compatible = "simple-audio-card"; 112 simple-audio-card,name = "tda1997x-audio"; 113 simple-audio-card,format = "i2s"; 114 simple-audio-card,bitclock-master = <&sound_codec>; 115 simple-audio-card,frame-master = <&sound_codec>; 116 117 sound_cpu: simple-audio-card,cpu { 118 sound-dai = <&ssi1>; 119 }; 120 121 sound_codec: simple-audio-card,codec { 122 sound-dai = <&hdmi_receiver>; 123 }; 124 }; 125}; 126 127&audmux { 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ 130 status = "okay"; 131 132 mux-ssi1 { 133 fsl,audmux-port = <0>; 134 fsl,port-config = < 135 (IMX_AUDMUX_V2_PTCR_TFSDIR | 136 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ 137 IMX_AUDMUX_V2_PTCR_TCLKDIR | 138 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ 139 IMX_AUDMUX_V2_PTCR_SYN) 140 IMX_AUDMUX_V2_PDCR_RXDSEL(4) 141 >; 142 }; 143 144 mux-aud5 { 145 fsl,audmux-port = <4>; 146 fsl,port-config = < 147 IMX_AUDMUX_V2_PTCR_SYN 148 IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; 149 }; 150}; 151 152&can1 { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_flexcan1>; 155 status = "okay"; 156}; 157 158&gpmi { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_gpmi_nand>; 161 status = "okay"; 162}; 163 164&hdmi { 165 ddc-i2c-bus = <&i2c3>; 166 status = "okay"; 167}; 168 169&i2c1 { 170 clock-frequency = <100000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_i2c1>; 173 status = "okay"; 174 175 gsc: gsc@20 { 176 compatible = "gw,gsc"; 177 reg = <0x20>; 178 interrupt-parent = <&gpio1>; 179 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 180 interrupt-controller; 181 #interrupt-cells = <1>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 adc { 186 compatible = "gw,gsc-adc"; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 channel@0 { 191 gw,mode = <0>; 192 reg = <0x00>; 193 label = "temp"; 194 }; 195 196 channel@2 { 197 gw,mode = <1>; 198 reg = <0x02>; 199 label = "vdd_vin"; 200 }; 201 202 channel@5 { 203 gw,mode = <1>; 204 reg = <0x05>; 205 label = "vdd_3p3"; 206 }; 207 208 channel@8 { 209 gw,mode = <1>; 210 reg = <0x08>; 211 label = "vdd_bat"; 212 }; 213 214 channel@b { 215 gw,mode = <1>; 216 reg = <0x0b>; 217 label = "vdd_5p0"; 218 }; 219 220 channel@e { 221 gw,mode = <1>; 222 reg = <0xe>; 223 label = "vdd_arm"; 224 }; 225 226 channel@11 { 227 gw,mode = <1>; 228 reg = <0x11>; 229 label = "vdd_soc"; 230 }; 231 232 channel@14 { 233 gw,mode = <1>; 234 reg = <0x14>; 235 label = "vdd_3p0"; 236 }; 237 238 channel@17 { 239 gw,mode = <1>; 240 reg = <0x17>; 241 label = "vdd_1p5"; 242 }; 243 244 channel@1d { 245 gw,mode = <1>; 246 reg = <0x1d>; 247 label = "vdd_1p8a"; 248 }; 249 250 channel@20 { 251 gw,mode = <1>; 252 reg = <0x20>; 253 label = "vdd_1p0b"; 254 }; 255 }; 256 }; 257 258 gsc_gpio: gpio@23 { 259 compatible = "nxp,pca9555"; 260 reg = <0x23>; 261 gpio-controller; 262 #gpio-cells = <2>; 263 interrupt-parent = <&gsc>; 264 interrupts = <4>; 265 }; 266 267 eeprom1: eeprom@50 { 268 compatible = "atmel,24c02"; 269 reg = <0x50>; 270 pagesize = <16>; 271 }; 272 273 eeprom2: eeprom@51 { 274 compatible = "atmel,24c02"; 275 reg = <0x51>; 276 pagesize = <16>; 277 }; 278 279 eeprom3: eeprom@52 { 280 compatible = "atmel,24c02"; 281 reg = <0x52>; 282 pagesize = <16>; 283 }; 284 285 eeprom4: eeprom@53 { 286 compatible = "atmel,24c02"; 287 reg = <0x53>; 288 pagesize = <16>; 289 }; 290 291 rtc: rtc@68 { 292 compatible = "dallas,ds1672"; 293 reg = <0x68>; 294 }; 295}; 296 297&i2c2 { 298 clock-frequency = <100000>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_i2c2>; 301 status = "okay"; 302 303 ltc3676: pmic@3c { 304 compatible = "lltc,ltc3676"; 305 reg = <0x3c>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_pmic>; 308 interrupt-parent = <&gpio1>; 309 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 310 311 regulators { 312 /* VDD_SOC (1+R1/R2 = 1.635) */ 313 reg_vdd_soc: sw1 { 314 regulator-name = "vddsoc"; 315 regulator-min-microvolt = <674400>; 316 regulator-max-microvolt = <1308000>; 317 lltc,fb-voltage-divider = <127000 200000>; 318 regulator-ramp-delay = <7000>; 319 regulator-boot-on; 320 regulator-always-on; 321 }; 322 323 /* VDD_DDR (1+R1/R2 = 2.105) */ 324 reg_vdd_ddr: sw2 { 325 regulator-name = "vddddr"; 326 regulator-min-microvolt = <868310>; 327 regulator-max-microvolt = <1684000>; 328 lltc,fb-voltage-divider = <221000 200000>; 329 regulator-ramp-delay = <7000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 /* VDD_ARM (1+R1/R2 = 1.635) */ 335 reg_vdd_arm: sw3 { 336 regulator-name = "vddarm"; 337 regulator-min-microvolt = <674400>; 338 regulator-max-microvolt = <1308000>; 339 lltc,fb-voltage-divider = <127000 200000>; 340 regulator-ramp-delay = <7000>; 341 regulator-boot-on; 342 regulator-always-on; 343 }; 344 345 /* VDD_3P3 (1+R1/R2 = 1.281) */ 346 reg_3p3: sw4 { 347 regulator-name = "vdd3p3"; 348 regulator-min-microvolt = <1880000>; 349 regulator-max-microvolt = <3647000>; 350 lltc,fb-voltage-divider = <200000 56200>; 351 regulator-ramp-delay = <7000>; 352 regulator-boot-on; 353 regulator-always-on; 354 }; 355 356 /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ 357 reg_1p8a: ldo2 { 358 regulator-name = "vdd1p8a"; 359 regulator-min-microvolt = <1816125>; 360 regulator-max-microvolt = <1816125>; 361 lltc,fb-voltage-divider = <301000 200000>; 362 regulator-boot-on; 363 regulator-always-on; 364 }; 365 366 /* VDD_1P8b: HDMI In analog */ 367 reg_1p8b: ldo3 { 368 regulator-name = "vdd1p8b"; 369 regulator-min-microvolt = <1800000>; 370 regulator-max-microvolt = <1800000>; 371 regulator-boot-on; 372 }; 373 374 /* VDD_HIGH (1+R1/R2 = 4.17) */ 375 reg_3p0: ldo4 { 376 regulator-name = "vdd3p0"; 377 regulator-min-microvolt = <3023250>; 378 regulator-max-microvolt = <3023250>; 379 lltc,fb-voltage-divider = <634000 200000>; 380 regulator-boot-on; 381 regulator-always-on; 382 }; 383 }; 384 }; 385}; 386 387&i2c3 { 388 clock-frequency = <100000>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_i2c3>; 391 status = "okay"; 392 393 gpio_exp: pca9555@24 { 394 compatible = "nxp,pca9555"; 395 reg = <0x24>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 }; 399 400 hdmi_receiver: hdmi-receiver@48 { 401 compatible = "nxp,tda19971"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_tda1997x>; 404 reg = <0x48>; 405 interrupt-parent = <&gpio1>; 406 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 407 DOVDD-supply = <®_3p3>; 408 AVDD-supply = <®_1p8b>; 409 DVDD-supply = <®_1p8a>; 410 #sound-dai-cells = <0>; 411 nxp,audout-format = "i2s"; 412 nxp,audout-layout = <0>; 413 nxp,audout-width = <16>; 414 nxp,audout-mclk-fs = <128>; 415 /* 416 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] 417 * and Y[11:4] across 16bits in the same cycle 418 * which we map to VP[15:08]<->CSI_DATA[19:12] 419 */ 420 nxp,vidout-portcfg = 421 /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ 422 < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, 423 /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ 424 < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, 425 /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ 426 < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, 427 /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ 428 < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; 429 430 port { 431 tda1997x_to_ipu1_csi0_mux: endpoint { 432 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 433 bus-width = <16>; 434 hsync-active = <1>; 435 vsync-active = <1>; 436 data-active = <1>; 437 }; 438 }; 439 }; 440}; 441 442&ipu1_csi0_from_ipu1_csi0_mux { 443 bus-width = <16>; 444}; 445 446&ipu1_csi0_mux_from_parallel_sensor { 447 remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; 448 bus-width = <16>; 449}; 450 451&ipu1_csi0 { 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_ipu1_csi0>; 454}; 455 456&pcie { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_pcie>; 459 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 460 status = "okay"; 461}; 462 463&pwm2 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 466 status = "disabled"; 467}; 468 469&pwm3 { 470 pinctrl-names = "default"; 471 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 472 status = "disabled"; 473}; 474 475&ssi1 { 476 status = "okay"; 477}; 478 479&uart2 { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_uart2>; 482 status = "okay"; 483}; 484 485&uart3 { 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_uart3>; 488 status = "okay"; 489}; 490 491&usbotg { 492 vbus-supply = <®_usb_otg_vbus>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_usbotg>; 495 disable-over-current; 496 status = "okay"; 497}; 498 499&usbh1 { 500 vbus-supply = <®_usb_h1_vbus>; 501 status = "okay"; 502}; 503 504&wdog1 { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pinctrl_wdog>; 507 fsl,ext-reset-output; 508}; 509 510&iomuxc { 511 pinctrl_audmux: audmuxgrp { 512 fsl,pins = < 513 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 514 MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 515 MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 516 >; 517 }; 518 519 pinctrl_flexcan1: flexcan1grp { 520 fsl,pins = < 521 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 522 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 523 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 524 >; 525 }; 526 527 pinctrl_gpio_leds: gpioledsgrp { 528 fsl,pins = < 529 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 530 >; 531 }; 532 533 pinctrl_gpmi_nand: gpminandgrp { 534 fsl,pins = < 535 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 536 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 537 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 538 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 539 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 540 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 541 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 542 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 543 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 544 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 545 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 546 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 547 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 548 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 549 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 550 >; 551 }; 552 553 pinctrl_i2c1: i2c1grp { 554 fsl,pins = < 555 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 556 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 557 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 558 >; 559 }; 560 561 pinctrl_i2c2: i2c2grp { 562 fsl,pins = < 563 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 564 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 565 >; 566 }; 567 568 pinctrl_i2c3: i2c3grp { 569 fsl,pins = < 570 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 571 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 572 >; 573 }; 574 575 pinctrl_ipu1_csi0: ipu1_csi0grp { 576 fsl,pins = < 577 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 578 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 579 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 580 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 581 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 582 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 583 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 584 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 585 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 586 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 587 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 588 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 589 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 590 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 591 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 592 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 593 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 594 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 595 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 596 >; 597 }; 598 599 pinctrl_pcie: pciegrp { 600 fsl,pins = < 601 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 602 >; 603 }; 604 605 pinctrl_pmic: pmicgrp { 606 fsl,pins = < 607 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 608 >; 609 }; 610 611 pinctrl_pwm2: pwm2grp { 612 fsl,pins = < 613 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 614 >; 615 }; 616 617 pinctrl_pwm3: pwm3grp { 618 fsl,pins = < 619 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 620 >; 621 }; 622 623 pinctrl_tda1997x: tda1997xgrp { 624 fsl,pins = < 625 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 626 >; 627 }; 628 629 pinctrl_uart2: uart2grp { 630 fsl,pins = < 631 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 632 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 633 >; 634 }; 635 636 pinctrl_uart3: uart3grp { 637 fsl,pins = < 638 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 639 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 640 >; 641 }; 642 643 pinctrl_usbotg: usbotggrp { 644 fsl,pins = < 645 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 646 >; 647 }; 648 649 pinctrl_wdog: wdoggrp { 650 fsl,pins = < 651 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 652 >; 653 }; 654}; 655