1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013 Gateworks Corporation 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 7*724ba675SRob Herring#include <dt-bindings/input/linux-event-codes.h> 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring /* these are used by bootloader for disabling nodes */ 12*724ba675SRob Herring aliases { 13*724ba675SRob Herring led0 = &led0; 14*724ba675SRob Herring led1 = &led1; 15*724ba675SRob Herring nand = &gpmi; 16*724ba675SRob Herring usb0 = &usbh1; 17*724ba675SRob Herring usb1 = &usbotg; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring chosen { 21*724ba675SRob Herring bootargs = "console=ttymxc1,115200"; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring gpio-keys { 25*724ba675SRob Herring compatible = "gpio-keys"; 26*724ba675SRob Herring 27*724ba675SRob Herring user-pb { 28*724ba675SRob Herring label = "user_pb"; 29*724ba675SRob Herring gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 30*724ba675SRob Herring linux,code = <BTN_0>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring user-pb1x { 34*724ba675SRob Herring label = "user_pb1x"; 35*724ba675SRob Herring linux,code = <BTN_1>; 36*724ba675SRob Herring interrupt-parent = <&gsc>; 37*724ba675SRob Herring interrupts = <0>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring key-erased { 41*724ba675SRob Herring label = "key-erased"; 42*724ba675SRob Herring linux,code = <BTN_2>; 43*724ba675SRob Herring interrupt-parent = <&gsc>; 44*724ba675SRob Herring interrupts = <1>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring eeprom-wp { 48*724ba675SRob Herring label = "eeprom_wp"; 49*724ba675SRob Herring linux,code = <BTN_3>; 50*724ba675SRob Herring interrupt-parent = <&gsc>; 51*724ba675SRob Herring interrupts = <2>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring tamper { 55*724ba675SRob Herring label = "tamper"; 56*724ba675SRob Herring linux,code = <BTN_4>; 57*724ba675SRob Herring interrupt-parent = <&gsc>; 58*724ba675SRob Herring interrupts = <5>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring switch-hold { 62*724ba675SRob Herring label = "switch_hold"; 63*724ba675SRob Herring linux,code = <BTN_5>; 64*724ba675SRob Herring interrupt-parent = <&gsc>; 65*724ba675SRob Herring interrupts = <7>; 66*724ba675SRob Herring }; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring leds { 70*724ba675SRob Herring compatible = "gpio-leds"; 71*724ba675SRob Herring pinctrl-names = "default"; 72*724ba675SRob Herring pinctrl-0 = <&pinctrl_gpio_leds>; 73*724ba675SRob Herring 74*724ba675SRob Herring led0: led-user1 { 75*724ba675SRob Herring label = "user1"; 76*724ba675SRob Herring gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 77*724ba675SRob Herring default-state = "on"; 78*724ba675SRob Herring linux,default-trigger = "heartbeat"; 79*724ba675SRob Herring }; 80*724ba675SRob Herring 81*724ba675SRob Herring led1: led-user2 { 82*724ba675SRob Herring label = "user2"; 83*724ba675SRob Herring gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 84*724ba675SRob Herring default-state = "off"; 85*724ba675SRob Herring }; 86*724ba675SRob Herring }; 87*724ba675SRob Herring 88*724ba675SRob Herring memory@10000000 { 89*724ba675SRob Herring device_type = "memory"; 90*724ba675SRob Herring reg = <0x10000000 0x20000000>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring pps { 94*724ba675SRob Herring compatible = "pps-gpio"; 95*724ba675SRob Herring pinctrl-names = "default"; 96*724ba675SRob Herring pinctrl-0 = <&pinctrl_pps>; 97*724ba675SRob Herring gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 98*724ba675SRob Herring status = "okay"; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring reg_3p3v: regulator-3p3v { 102*724ba675SRob Herring compatible = "regulator-fixed"; 103*724ba675SRob Herring regulator-name = "3P3V"; 104*724ba675SRob Herring regulator-min-microvolt = <3300000>; 105*724ba675SRob Herring regulator-max-microvolt = <3300000>; 106*724ba675SRob Herring regulator-always-on; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring reg_5p0v: regulator-5p0v { 110*724ba675SRob Herring compatible = "regulator-fixed"; 111*724ba675SRob Herring regulator-name = "5P0V"; 112*724ba675SRob Herring regulator-min-microvolt = <5000000>; 113*724ba675SRob Herring regulator-max-microvolt = <5000000>; 114*724ba675SRob Herring regulator-always-on; 115*724ba675SRob Herring }; 116*724ba675SRob Herring 117*724ba675SRob Herring reg_usb_otg_vbus: regulator-usb-otg-vbus { 118*724ba675SRob Herring compatible = "regulator-fixed"; 119*724ba675SRob Herring regulator-name = "usb_otg_vbus"; 120*724ba675SRob Herring regulator-min-microvolt = <5000000>; 121*724ba675SRob Herring regulator-max-microvolt = <5000000>; 122*724ba675SRob Herring gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 123*724ba675SRob Herring enable-active-high; 124*724ba675SRob Herring }; 125*724ba675SRob Herring}; 126*724ba675SRob Herring 127*724ba675SRob Herring&fec { 128*724ba675SRob Herring pinctrl-names = "default"; 129*724ba675SRob Herring pinctrl-0 = <&pinctrl_enet>; 130*724ba675SRob Herring phy-mode = "rgmii-id"; 131*724ba675SRob Herring phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 132*724ba675SRob Herring status = "okay"; 133*724ba675SRob Herring}; 134*724ba675SRob Herring 135*724ba675SRob Herring&gpmi { 136*724ba675SRob Herring pinctrl-names = "default"; 137*724ba675SRob Herring pinctrl-0 = <&pinctrl_gpmi_nand>; 138*724ba675SRob Herring status = "okay"; 139*724ba675SRob Herring}; 140*724ba675SRob Herring 141*724ba675SRob Herring&hdmi { 142*724ba675SRob Herring ddc-i2c-bus = <&i2c3>; 143*724ba675SRob Herring status = "okay"; 144*724ba675SRob Herring}; 145*724ba675SRob Herring 146*724ba675SRob Herring&i2c1 { 147*724ba675SRob Herring clock-frequency = <100000>; 148*724ba675SRob Herring pinctrl-names = "default"; 149*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c1>; 150*724ba675SRob Herring status = "okay"; 151*724ba675SRob Herring 152*724ba675SRob Herring gsc: gsc@20 { 153*724ba675SRob Herring compatible = "gw,gsc"; 154*724ba675SRob Herring reg = <0x20>; 155*724ba675SRob Herring interrupt-parent = <&gpio1>; 156*724ba675SRob Herring interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 157*724ba675SRob Herring interrupt-controller; 158*724ba675SRob Herring #interrupt-cells = <1>; 159*724ba675SRob Herring #size-cells = <0>; 160*724ba675SRob Herring 161*724ba675SRob Herring adc { 162*724ba675SRob Herring compatible = "gw,gsc-adc"; 163*724ba675SRob Herring #address-cells = <1>; 164*724ba675SRob Herring #size-cells = <0>; 165*724ba675SRob Herring 166*724ba675SRob Herring channel@0 { 167*724ba675SRob Herring gw,mode = <0>; 168*724ba675SRob Herring reg = <0x00>; 169*724ba675SRob Herring label = "temp"; 170*724ba675SRob Herring }; 171*724ba675SRob Herring 172*724ba675SRob Herring channel@2 { 173*724ba675SRob Herring gw,mode = <1>; 174*724ba675SRob Herring reg = <0x02>; 175*724ba675SRob Herring label = "vdd_vin"; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring channel@5 { 179*724ba675SRob Herring gw,mode = <1>; 180*724ba675SRob Herring reg = <0x05>; 181*724ba675SRob Herring label = "vdd_3p3"; 182*724ba675SRob Herring }; 183*724ba675SRob Herring 184*724ba675SRob Herring channel@8 { 185*724ba675SRob Herring gw,mode = <1>; 186*724ba675SRob Herring reg = <0x08>; 187*724ba675SRob Herring label = "vdd_bat"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring 190*724ba675SRob Herring channel@b { 191*724ba675SRob Herring gw,mode = <1>; 192*724ba675SRob Herring reg = <0x0b>; 193*724ba675SRob Herring label = "vdd_5p0"; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring channel@e { 197*724ba675SRob Herring gw,mode = <1>; 198*724ba675SRob Herring reg = <0xe>; 199*724ba675SRob Herring label = "vdd_arm"; 200*724ba675SRob Herring }; 201*724ba675SRob Herring 202*724ba675SRob Herring channel@11 { 203*724ba675SRob Herring gw,mode = <1>; 204*724ba675SRob Herring reg = <0x11>; 205*724ba675SRob Herring label = "vdd_soc"; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring channel@14 { 209*724ba675SRob Herring gw,mode = <1>; 210*724ba675SRob Herring reg = <0x14>; 211*724ba675SRob Herring label = "vdd_3p0"; 212*724ba675SRob Herring }; 213*724ba675SRob Herring 214*724ba675SRob Herring channel@17 { 215*724ba675SRob Herring gw,mode = <1>; 216*724ba675SRob Herring reg = <0x17>; 217*724ba675SRob Herring label = "vdd_1p5"; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring channel@1d { 221*724ba675SRob Herring gw,mode = <1>; 222*724ba675SRob Herring reg = <0x1d>; 223*724ba675SRob Herring label = "vdd_1p8"; 224*724ba675SRob Herring }; 225*724ba675SRob Herring 226*724ba675SRob Herring channel@20 { 227*724ba675SRob Herring gw,mode = <1>; 228*724ba675SRob Herring reg = <0x20>; 229*724ba675SRob Herring label = "vdd_an1"; 230*724ba675SRob Herring }; 231*724ba675SRob Herring 232*724ba675SRob Herring channel@23 { 233*724ba675SRob Herring gw,mode = <1>; 234*724ba675SRob Herring reg = <0x23>; 235*724ba675SRob Herring label = "vdd_2p5"; 236*724ba675SRob Herring }; 237*724ba675SRob Herring }; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring gsc_gpio: gpio@23 { 241*724ba675SRob Herring compatible = "nxp,pca9555"; 242*724ba675SRob Herring reg = <0x23>; 243*724ba675SRob Herring gpio-controller; 244*724ba675SRob Herring #gpio-cells = <2>; 245*724ba675SRob Herring interrupt-parent = <&gsc>; 246*724ba675SRob Herring interrupts = <4>; 247*724ba675SRob Herring }; 248*724ba675SRob Herring 249*724ba675SRob Herring eeprom1: eeprom@50 { 250*724ba675SRob Herring compatible = "atmel,24c02"; 251*724ba675SRob Herring reg = <0x50>; 252*724ba675SRob Herring pagesize = <16>; 253*724ba675SRob Herring }; 254*724ba675SRob Herring 255*724ba675SRob Herring eeprom2: eeprom@51 { 256*724ba675SRob Herring compatible = "atmel,24c02"; 257*724ba675SRob Herring reg = <0x51>; 258*724ba675SRob Herring pagesize = <16>; 259*724ba675SRob Herring }; 260*724ba675SRob Herring 261*724ba675SRob Herring eeprom3: eeprom@52 { 262*724ba675SRob Herring compatible = "atmel,24c02"; 263*724ba675SRob Herring reg = <0x52>; 264*724ba675SRob Herring pagesize = <16>; 265*724ba675SRob Herring }; 266*724ba675SRob Herring 267*724ba675SRob Herring eeprom4: eeprom@53 { 268*724ba675SRob Herring compatible = "atmel,24c02"; 269*724ba675SRob Herring reg = <0x53>; 270*724ba675SRob Herring pagesize = <16>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring rtc: ds1672@68 { 274*724ba675SRob Herring compatible = "dallas,ds1672"; 275*724ba675SRob Herring reg = <0x68>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring}; 278*724ba675SRob Herring 279*724ba675SRob Herring&i2c2 { 280*724ba675SRob Herring clock-frequency = <100000>; 281*724ba675SRob Herring pinctrl-names = "default"; 282*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c2>; 283*724ba675SRob Herring status = "okay"; 284*724ba675SRob Herring 285*724ba675SRob Herring ltc3676: pmic@3c { 286*724ba675SRob Herring compatible = "lltc,ltc3676"; 287*724ba675SRob Herring reg = <0x3c>; 288*724ba675SRob Herring pinctrl-names = "default"; 289*724ba675SRob Herring pinctrl-0 = <&pinctrl_pmic>; 290*724ba675SRob Herring interrupt-parent = <&gpio1>; 291*724ba675SRob Herring interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 292*724ba675SRob Herring 293*724ba675SRob Herring regulators { 294*724ba675SRob Herring /* VDD_SOC (1+R1/R2 = 1.635) */ 295*724ba675SRob Herring reg_vdd_soc: sw1 { 296*724ba675SRob Herring regulator-name = "vddsoc"; 297*724ba675SRob Herring regulator-min-microvolt = <674400>; 298*724ba675SRob Herring regulator-max-microvolt = <1308000>; 299*724ba675SRob Herring lltc,fb-voltage-divider = <127000 200000>; 300*724ba675SRob Herring regulator-ramp-delay = <7000>; 301*724ba675SRob Herring regulator-boot-on; 302*724ba675SRob Herring regulator-always-on; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 306*724ba675SRob Herring reg_1p8v: sw2 { 307*724ba675SRob Herring regulator-name = "vdd1p8"; 308*724ba675SRob Herring regulator-min-microvolt = <1033310>; 309*724ba675SRob Herring regulator-max-microvolt = <2004000>; 310*724ba675SRob Herring lltc,fb-voltage-divider = <301000 200000>; 311*724ba675SRob Herring regulator-ramp-delay = <7000>; 312*724ba675SRob Herring regulator-boot-on; 313*724ba675SRob Herring regulator-always-on; 314*724ba675SRob Herring }; 315*724ba675SRob Herring 316*724ba675SRob Herring /* VDD_ARM (1+R1/R2 = 1.635) */ 317*724ba675SRob Herring reg_vdd_arm: sw3 { 318*724ba675SRob Herring regulator-name = "vddarm"; 319*724ba675SRob Herring regulator-min-microvolt = <674400>; 320*724ba675SRob Herring regulator-max-microvolt = <1308000>; 321*724ba675SRob Herring lltc,fb-voltage-divider = <127000 200000>; 322*724ba675SRob Herring regulator-ramp-delay = <7000>; 323*724ba675SRob Herring regulator-boot-on; 324*724ba675SRob Herring regulator-always-on; 325*724ba675SRob Herring }; 326*724ba675SRob Herring 327*724ba675SRob Herring /* VDD_DDR (1+R1/R2 = 2.105) */ 328*724ba675SRob Herring reg_vdd_ddr: sw4 { 329*724ba675SRob Herring regulator-name = "vddddr"; 330*724ba675SRob Herring regulator-min-microvolt = <868310>; 331*724ba675SRob Herring regulator-max-microvolt = <1684000>; 332*724ba675SRob Herring lltc,fb-voltage-divider = <221000 200000>; 333*724ba675SRob Herring regulator-ramp-delay = <7000>; 334*724ba675SRob Herring regulator-boot-on; 335*724ba675SRob Herring regulator-always-on; 336*724ba675SRob Herring }; 337*724ba675SRob Herring 338*724ba675SRob Herring /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 339*724ba675SRob Herring reg_2p5v: ldo2 { 340*724ba675SRob Herring regulator-name = "vdd2p5"; 341*724ba675SRob Herring regulator-min-microvolt = <2490375>; 342*724ba675SRob Herring regulator-max-microvolt = <2490375>; 343*724ba675SRob Herring lltc,fb-voltage-divider = <487000 200000>; 344*724ba675SRob Herring regulator-boot-on; 345*724ba675SRob Herring regulator-always-on; 346*724ba675SRob Herring }; 347*724ba675SRob Herring 348*724ba675SRob Herring /* VDD_HIGH (1+R1/R2 = 4.17) */ 349*724ba675SRob Herring reg_3p0v: ldo4 { 350*724ba675SRob Herring regulator-name = "vdd3p0"; 351*724ba675SRob Herring regulator-min-microvolt = <3023250>; 352*724ba675SRob Herring regulator-max-microvolt = <3023250>; 353*724ba675SRob Herring lltc,fb-voltage-divider = <634000 200000>; 354*724ba675SRob Herring regulator-boot-on; 355*724ba675SRob Herring regulator-always-on; 356*724ba675SRob Herring }; 357*724ba675SRob Herring }; 358*724ba675SRob Herring }; 359*724ba675SRob Herring}; 360*724ba675SRob Herring 361*724ba675SRob Herring&i2c3 { 362*724ba675SRob Herring clock-frequency = <100000>; 363*724ba675SRob Herring pinctrl-names = "default"; 364*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c3>; 365*724ba675SRob Herring status = "okay"; 366*724ba675SRob Herring 367*724ba675SRob Herring adv7180: camera@20 { 368*724ba675SRob Herring compatible = "adi,adv7180"; 369*724ba675SRob Herring pinctrl-names = "default"; 370*724ba675SRob Herring pinctrl-0 = <&pinctrl_adv7180>; 371*724ba675SRob Herring reg = <0x20>; 372*724ba675SRob Herring powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 373*724ba675SRob Herring interrupt-parent = <&gpio5>; 374*724ba675SRob Herring interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 375*724ba675SRob Herring 376*724ba675SRob Herring port { 377*724ba675SRob Herring adv7180_to_ipu1_csi0_mux: endpoint { 378*724ba675SRob Herring remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 379*724ba675SRob Herring bus-width = <8>; 380*724ba675SRob Herring }; 381*724ba675SRob Herring }; 382*724ba675SRob Herring }; 383*724ba675SRob Herring}; 384*724ba675SRob Herring 385*724ba675SRob Herring&ipu1_csi0_from_ipu1_csi0_mux { 386*724ba675SRob Herring bus-width = <8>; 387*724ba675SRob Herring}; 388*724ba675SRob Herring 389*724ba675SRob Herring&ipu1_csi0_mux_from_parallel_sensor { 390*724ba675SRob Herring remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 391*724ba675SRob Herring bus-width = <8>; 392*724ba675SRob Herring}; 393*724ba675SRob Herring 394*724ba675SRob Herring&ipu1_csi0 { 395*724ba675SRob Herring pinctrl-names = "default"; 396*724ba675SRob Herring pinctrl-0 = <&pinctrl_ipu1_csi0>; 397*724ba675SRob Herring}; 398*724ba675SRob Herring 399*724ba675SRob Herring&pcie { 400*724ba675SRob Herring pinctrl-names = "default"; 401*724ba675SRob Herring pinctrl-0 = <&pinctrl_pcie>; 402*724ba675SRob Herring reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 403*724ba675SRob Herring status = "okay"; 404*724ba675SRob Herring}; 405*724ba675SRob Herring 406*724ba675SRob Herring&pwm2 { 407*724ba675SRob Herring pinctrl-names = "default"; 408*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 409*724ba675SRob Herring status = "disabled"; 410*724ba675SRob Herring}; 411*724ba675SRob Herring 412*724ba675SRob Herring&pwm3 { 413*724ba675SRob Herring pinctrl-names = "default"; 414*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 415*724ba675SRob Herring status = "disabled"; 416*724ba675SRob Herring}; 417*724ba675SRob Herring 418*724ba675SRob Herring&pwm4 { 419*724ba675SRob Herring pinctrl-names = "default"; 420*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 421*724ba675SRob Herring status = "disabled"; 422*724ba675SRob Herring}; 423*724ba675SRob Herring 424*724ba675SRob Herring&uart1 { 425*724ba675SRob Herring pinctrl-names = "default"; 426*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart1>; 427*724ba675SRob Herring status = "okay"; 428*724ba675SRob Herring}; 429*724ba675SRob Herring 430*724ba675SRob Herring&uart2 { 431*724ba675SRob Herring pinctrl-names = "default"; 432*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart2>; 433*724ba675SRob Herring status = "okay"; 434*724ba675SRob Herring}; 435*724ba675SRob Herring 436*724ba675SRob Herring&uart3 { 437*724ba675SRob Herring pinctrl-names = "default"; 438*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart3>; 439*724ba675SRob Herring status = "okay"; 440*724ba675SRob Herring}; 441*724ba675SRob Herring 442*724ba675SRob Herring&uart5 { 443*724ba675SRob Herring pinctrl-names = "default"; 444*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart5>; 445*724ba675SRob Herring status = "okay"; 446*724ba675SRob Herring}; 447*724ba675SRob Herring 448*724ba675SRob Herring&usbotg { 449*724ba675SRob Herring vbus-supply = <®_usb_otg_vbus>; 450*724ba675SRob Herring pinctrl-names = "default"; 451*724ba675SRob Herring pinctrl-0 = <&pinctrl_usbotg>; 452*724ba675SRob Herring disable-over-current; 453*724ba675SRob Herring status = "okay"; 454*724ba675SRob Herring}; 455*724ba675SRob Herring 456*724ba675SRob Herring&usbh1 { 457*724ba675SRob Herring status = "okay"; 458*724ba675SRob Herring}; 459*724ba675SRob Herring 460*724ba675SRob Herring&wdog1 { 461*724ba675SRob Herring pinctrl-names = "default"; 462*724ba675SRob Herring pinctrl-0 = <&pinctrl_wdog>; 463*724ba675SRob Herring fsl,ext-reset-output; 464*724ba675SRob Herring}; 465*724ba675SRob Herring 466*724ba675SRob Herring&iomuxc { 467*724ba675SRob Herring pinctrl_adv7180: adv7180grp { 468*724ba675SRob Herring fsl,pins = < 469*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 470*724ba675SRob Herring MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 471*724ba675SRob Herring >; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring pinctrl_enet: enetgrp { 475*724ba675SRob Herring fsl,pins = < 476*724ba675SRob Herring MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 477*724ba675SRob Herring MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 478*724ba675SRob Herring MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 479*724ba675SRob Herring MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 480*724ba675SRob Herring MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 481*724ba675SRob Herring MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 482*724ba675SRob Herring MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 483*724ba675SRob Herring MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 484*724ba675SRob Herring MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 485*724ba675SRob Herring MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 486*724ba675SRob Herring MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 487*724ba675SRob Herring MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 488*724ba675SRob Herring MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 489*724ba675SRob Herring MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 490*724ba675SRob Herring MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 491*724ba675SRob Herring MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 492*724ba675SRob Herring MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 493*724ba675SRob Herring >; 494*724ba675SRob Herring }; 495*724ba675SRob Herring 496*724ba675SRob Herring pinctrl_gpio_leds: gpioledsgrp { 497*724ba675SRob Herring fsl,pins = < 498*724ba675SRob Herring MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 499*724ba675SRob Herring MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 500*724ba675SRob Herring >; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring pinctrl_gpmi_nand: gpminandgrp { 504*724ba675SRob Herring fsl,pins = < 505*724ba675SRob Herring MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 506*724ba675SRob Herring MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 507*724ba675SRob Herring MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 508*724ba675SRob Herring MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 509*724ba675SRob Herring MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 510*724ba675SRob Herring MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 511*724ba675SRob Herring MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 512*724ba675SRob Herring MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 513*724ba675SRob Herring MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 514*724ba675SRob Herring MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 515*724ba675SRob Herring MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 516*724ba675SRob Herring MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 517*724ba675SRob Herring MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 518*724ba675SRob Herring MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 519*724ba675SRob Herring MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 520*724ba675SRob Herring >; 521*724ba675SRob Herring }; 522*724ba675SRob Herring 523*724ba675SRob Herring pinctrl_i2c1: i2c1grp { 524*724ba675SRob Herring fsl,pins = < 525*724ba675SRob Herring MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 526*724ba675SRob Herring MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 527*724ba675SRob Herring MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 528*724ba675SRob Herring >; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring pinctrl_i2c2: i2c2grp { 532*724ba675SRob Herring fsl,pins = < 533*724ba675SRob Herring MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 534*724ba675SRob Herring MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 535*724ba675SRob Herring >; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring pinctrl_i2c3: i2c3grp { 539*724ba675SRob Herring fsl,pins = < 540*724ba675SRob Herring MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 541*724ba675SRob Herring MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 542*724ba675SRob Herring >; 543*724ba675SRob Herring }; 544*724ba675SRob Herring 545*724ba675SRob Herring pinctrl_ipu1_csi0: ipu1csi0grp { 546*724ba675SRob Herring fsl,pins = < 547*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 548*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 549*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 550*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 551*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 552*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 553*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 554*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 555*724ba675SRob Herring MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 556*724ba675SRob Herring MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 557*724ba675SRob Herring MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 558*724ba675SRob Herring >; 559*724ba675SRob Herring }; 560*724ba675SRob Herring 561*724ba675SRob Herring pinctrl_pcie: pciegrp { 562*724ba675SRob Herring fsl,pins = < 563*724ba675SRob Herring MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 564*724ba675SRob Herring >; 565*724ba675SRob Herring }; 566*724ba675SRob Herring 567*724ba675SRob Herring pinctrl_pmic: pmicgrp { 568*724ba675SRob Herring fsl,pins = < 569*724ba675SRob Herring MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 570*724ba675SRob Herring >; 571*724ba675SRob Herring }; 572*724ba675SRob Herring 573*724ba675SRob Herring pinctrl_pps: ppsgrp { 574*724ba675SRob Herring fsl,pins = < 575*724ba675SRob Herring MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 576*724ba675SRob Herring >; 577*724ba675SRob Herring }; 578*724ba675SRob Herring 579*724ba675SRob Herring pinctrl_pwm2: pwm2grp { 580*724ba675SRob Herring fsl,pins = < 581*724ba675SRob Herring MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 582*724ba675SRob Herring >; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring pinctrl_pwm3: pwm3grp { 586*724ba675SRob Herring fsl,pins = < 587*724ba675SRob Herring MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 588*724ba675SRob Herring >; 589*724ba675SRob Herring }; 590*724ba675SRob Herring 591*724ba675SRob Herring pinctrl_pwm4: pwm4grp { 592*724ba675SRob Herring fsl,pins = < 593*724ba675SRob Herring MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 594*724ba675SRob Herring >; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring pinctrl_uart1: uart1grp { 598*724ba675SRob Herring fsl,pins = < 599*724ba675SRob Herring MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 600*724ba675SRob Herring MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 601*724ba675SRob Herring >; 602*724ba675SRob Herring }; 603*724ba675SRob Herring 604*724ba675SRob Herring pinctrl_uart2: uart2grp { 605*724ba675SRob Herring fsl,pins = < 606*724ba675SRob Herring MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 607*724ba675SRob Herring MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 608*724ba675SRob Herring >; 609*724ba675SRob Herring }; 610*724ba675SRob Herring 611*724ba675SRob Herring pinctrl_uart3: uart3grp { 612*724ba675SRob Herring fsl,pins = < 613*724ba675SRob Herring MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 614*724ba675SRob Herring MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 615*724ba675SRob Herring >; 616*724ba675SRob Herring }; 617*724ba675SRob Herring 618*724ba675SRob Herring pinctrl_uart5: uart5grp { 619*724ba675SRob Herring fsl,pins = < 620*724ba675SRob Herring MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 621*724ba675SRob Herring MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 622*724ba675SRob Herring >; 623*724ba675SRob Herring }; 624*724ba675SRob Herring 625*724ba675SRob Herring pinctrl_usbotg: usbotggrp { 626*724ba675SRob Herring fsl,pins = < 627*724ba675SRob Herring MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 628*724ba675SRob Herring MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 629*724ba675SRob Herring MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 630*724ba675SRob Herring >; 631*724ba675SRob Herring }; 632*724ba675SRob Herring 633*724ba675SRob Herring pinctrl_wdog: wdoggrp { 634*724ba675SRob Herring fsl,pins = < 635*724ba675SRob Herring MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 636*724ba675SRob Herring >; 637*724ba675SRob Herring }; 638*724ba675SRob Herring}; 639