1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015-2021 DH electronics GmbH 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de> 5 */ 6 7#include <dt-bindings/pwm/pwm.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/imx6qdl-clock.h> 10#include <dt-bindings/input/input.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c2; 15 i2c1 = &i2c1; 16 i2c2 = &i2c3; 17 mmc0 = &usdhc2; 18 mmc1 = &usdhc3; 19 mmc2 = &usdhc4; 20 mmc3 = &usdhc1; 21 rtc0 = &rtc_i2c; 22 rtc1 = &snvs_rtc; 23 serial0 = &uart1; 24 serial1 = &uart5; 25 serial2 = &uart4; 26 serial3 = &uart2; 27 serial4 = &uart3; 28 }; 29 30 memory@10000000 { /* Appropriate memory size will be filled by U-Boot */ 31 device_type = "memory"; 32 reg = <0x10000000 0x20000000>; 33 }; 34 35 reg_3p3v: regulator-3P3V { 36 compatible = "regulator-fixed"; 37 regulator-always-on; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-name = "3P3V"; 41 }; 42 43 reg_eth_vio: regulator-eth-vio { 44 compatible = "regulator-fixed"; 45 gpio = <&gpio1 7 0>; 46 pinctrl-0 = <&pinctrl_enet_vio>; 47 pinctrl-names = "default"; 48 regulator-always-on; 49 regulator-boot-on; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 regulator-name = "eth_vio"; 53 vin-supply = <&sw2_reg>; 54 }; 55 56 /* OE pin of the latch is low active */ 57 reg_latch_oe_on: regulator-latch-oe-on { 58 compatible = "regulator-fixed"; 59 gpio = <&gpio3 22 0>; 60 regulator-always-on; 61 regulator-name = "latch_oe_on"; 62 }; 63 64 reg_usb_h1_vbus: regulator-usb-h1-vbus { 65 compatible = "regulator-fixed"; 66 enable-active-high; 67 gpio = <&gpio3 31 0>; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-name = "usb_h1_vbus"; 71 }; 72 73 reg_usb_otg_vbus: regulator-usb-otg-vbus { 74 compatible = "regulator-fixed"; 75 regulator-min-microvolt = <5000000>; 76 regulator-max-microvolt = <5000000>; 77 regulator-name = "usb_otg_vbus"; 78 }; 79}; 80 81&can1 { 82 pinctrl-0 = <&pinctrl_flexcan1>; 83 pinctrl-names = "default"; 84 status = "okay"; 85}; 86 87/* 88 * Special SoM hardware required which uses the pins from micro SD card. The 89 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 90 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on 91 * the board device tree file, the micro SD card must be disabled and the uart1 92 * rts/cts must be disabled or output on other DHCOM pins. 93 */ 94&can2 { 95 pinctrl-0 = <&pinctrl_flexcan2>; 96 pinctrl-names = "default"; 97 status = "disabled"; 98}; 99 100&ecspi1 { 101 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; 102 pinctrl-0 = <&pinctrl_ecspi1>; 103 pinctrl-names = "default"; 104 status = "okay"; 105 106 flash@0 { /* S25FL116K */ 107 #address-cells = <1>; 108 #size-cells = <1>; 109 compatible = "jedec,spi-nor"; 110 m25p,fast-read; 111 reg = <0>; 112 spi-max-frequency = <50000000>; 113 }; 114}; 115 116&ecspi2 { 117 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; 118 pinctrl-0 = <&pinctrl_ecspi2>; 119 pinctrl-names = "default"; 120 status = "disabled"; 121}; 122 123&fec { 124 phy-mode = "rmii"; 125 phy-handle = <ðphy0>; 126 pinctrl-0 = <&pinctrl_enet_100M>; 127 pinctrl-names = "default"; 128 status = "okay"; 129 130 mdio { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ 135 compatible = "ethernet-phy-id0007.c0f0", 136 "ethernet-phy-ieee802.3-c22"; 137 interrupt-parent = <&gpio4>; 138 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 139 pinctrl-0 = <&pinctrl_ethphy0>; 140 pinctrl-names = "default"; 141 reg = <0>; 142 reset-assert-us = <500>; 143 reset-deassert-us = <500>; 144 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 145 smsc,disable-energy-detect; /* Make plugin detection reliable */ 146 }; 147 }; 148}; 149 150&gpio1 { 151 gpio-line-names = 152 "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "", 153 "", "", "", "", "", "", "", "", 154 "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", 155 "", "", "", "", "", "", "", ""; 156}; 157 158&gpio2 { 159 gpio-line-names = 160 "", "", "", "", "", "", "", "", 161 "", "", "", "", "", "", "", "", 162 "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "", 163 "", "", "", "", "", "", "", ""; 164}; 165 166&gpio3 { 167 gpio-line-names = 168 "", "", "", "", "", "", "", "", 169 "", "", "", "", "", "", "", "", 170 "", "", "", "", "", "", "", "", 171 "", "", "", "DHCOM-G", "", "", "", ""; 172}; 173 174&gpio4 { 175 gpio-line-names = 176 "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H", 177 "DHCOM-I", "DHCOM-L", "", "", "", "", "", "", 178 "", "", "", "", "DHCOM-F", "", "", "", 179 "", "", "", "", "", "", "", ""; 180}; 181 182&gpio5 { 183 gpio-line-names = 184 "", "", "", "", "", "", "", "", 185 "", "", "", "", "", "", "", "", 186 "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "", 187 "", "", "", "", "", "", "", ""; 188}; 189 190&gpio6 { 191 gpio-line-names = 192 "", "", "", "DHCOM-D", "", "", "SOM-HW1", "", 193 "", "", "", "", "", "", "DHCOM-J", "DHCOM-K", 194 "", "", "", "", "", "", "", "", 195 "", "", "", "", "", "", "", ""; 196}; 197 198&gpio7 { 199 gpio-line-names = 200 "DHCOM-M", "DHCOM-N", "", "", "", "", "", "", 201 "", "", "", "", "", "DHCOM-P", "", "", 202 "", "", "", "", "", "", "", "", 203 "", "", "", "", "", "", "", ""; 204}; 205 206&i2c1 { 207 /* 208 * Info: According to erratum ERR007805 clock frequency limit is 375000. 209 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2]. 210 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf 211 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf 212 */ 213 clock-frequency = <100000>; 214 pinctrl-0 = <&pinctrl_i2c1>; 215 pinctrl-1 = <&pinctrl_i2c1_gpio>; 216 pinctrl-names = "default", "gpio"; 217 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 218 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 219 status = "okay"; 220}; 221 222&i2c2 { 223 /* Info: Clock frequency limit is 375000 (for details see i2c1) */ 224 clock-frequency = <100000>; 225 pinctrl-0 = <&pinctrl_i2c2>; 226 pinctrl-1 = <&pinctrl_i2c2_gpio>; 227 pinctrl-names = "default", "gpio"; 228 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 229 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 230 status = "okay"; 231}; 232 233&i2c3 { 234 /* Info: Clock frequency limit is 375000 (for details see i2c1) */ 235 clock-frequency = <100000>; 236 pinctrl-0 = <&pinctrl_i2c3>; 237 pinctrl-1 = <&pinctrl_i2c3_gpio>; 238 pinctrl-names = "default", "gpio"; 239 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 240 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 241 status = "okay"; 242 243 ltc3676: pmic@3c { 244 compatible = "lltc,ltc3676"; 245 interrupt-parent = <&gpio5>; 246 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 247 pinctrl-0 = <&pinctrl_pmic>; 248 pinctrl-names = "default"; 249 reg = <0x3c>; 250 251 regulators { 252 sw1_reg: sw1 { 253 lltc,fb-voltage-divider = <100000 110000>; 254 regulator-always-on; 255 regulator-boot-on; 256 regulator-max-microvolt = <1527272>; 257 regulator-min-microvolt = <787500>; 258 regulator-ramp-delay = <7000>; 259 }; 260 261 sw2_reg: sw2 { 262 lltc,fb-voltage-divider = <100000 28000>; 263 regulator-always-on; 264 regulator-boot-on; 265 regulator-max-microvolt = <3657142>; 266 regulator-min-microvolt = <1885714>; 267 regulator-ramp-delay = <7000>; 268 }; 269 270 sw3_reg: sw3 { 271 lltc,fb-voltage-divider = <100000 110000>; 272 regulator-always-on; 273 regulator-boot-on; 274 regulator-max-microvolt = <1527272>; 275 regulator-min-microvolt = <787500>; 276 regulator-ramp-delay = <7000>; 277 }; 278 279 sw4_reg: sw4 { 280 lltc,fb-voltage-divider = <100000 93100>; 281 regulator-always-on; 282 regulator-boot-on; 283 regulator-max-microvolt = <1659291>; 284 regulator-min-microvolt = <855571>; 285 regulator-ramp-delay = <7000>; 286 }; 287 288 ldo1_reg: ldo1 { 289 lltc,fb-voltage-divider = <102000 29400>; 290 regulator-always-on; 291 regulator-boot-on; 292 regulator-max-microvolt = <3240306>; 293 regulator-min-microvolt = <3240306>; 294 }; 295 296 ldo2_reg: ldo2 { 297 lltc,fb-voltage-divider = <100000 41200>; 298 regulator-always-on; 299 regulator-boot-on; 300 regulator-max-microvolt = <2484708>; 301 regulator-min-microvolt = <2484708>; 302 }; 303 }; 304 }; 305 306 touchscreen@49 { /* TSC2004 */ 307 compatible = "ti,tsc2004"; 308 interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; 309 pinctrl-0 = <&pinctrl_tsc2004>; 310 pinctrl-names = "default"; 311 reg = <0x49>; 312 vio-supply = <®_3p3v>; 313 status = "disabled"; 314 }; 315 316 eeprom@50 { 317 compatible = "atmel,24c02"; 318 pagesize = <16>; 319 reg = <0x50>; 320 }; 321 322 rtc_i2c: rtc@56 { 323 compatible = "microcrystal,rv3029"; 324 interrupt-parent = <&gpio7>; 325 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 326 pinctrl-0 = <&pinctrl_rtc>; 327 pinctrl-names = "default"; 328 reg = <0x56>; 329 }; 330}; 331 332&pcie { 333 pinctrl-0 = <&pinctrl_pcie>; 334 pinctrl-names = "default"; 335}; 336 337&pwm1 { 338 pinctrl-0 = <&pinctrl_pwm1>; 339 pinctrl-names = "default"; 340}; 341 342®_arm { 343 vin-supply = <&sw3_reg>; 344}; 345 346®_pu { 347 vin-supply = <&sw1_reg>; 348}; 349 350®_soc { 351 vin-supply = <&sw1_reg>; 352}; 353 354®_vdd1p1 { 355 vin-supply = <&sw2_reg>; 356}; 357 358®_vdd2p5 { 359 vin-supply = <&sw2_reg>; 360}; 361 362&uart1 { /* DHCOM UART1 */ 363 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 364 dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 365 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 366 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; 367 pinctrl-0 = <&pinctrl_uart1>; 368 pinctrl-names = "default"; 369 uart-has-rtscts; 370 status = "okay"; 371}; 372 373&uart4 { /* DHCOM UART3 */ 374 pinctrl-0 = <&pinctrl_uart4>; 375 pinctrl-names = "default"; 376 status = "okay"; 377}; 378 379&uart5 { /* DHCOM UART2 */ 380 pinctrl-0 = <&pinctrl_uart5>; 381 pinctrl-names = "default"; 382 uart-has-rtscts; 383 status = "okay"; 384}; 385 386&usbh1 { 387 dr_mode = "host"; 388 pinctrl-0 = <&pinctrl_usbh1>; 389 pinctrl-names = "default"; 390 vbus-supply = <®_usb_h1_vbus>; 391 status = "okay"; 392}; 393 394&usbotg { 395 disable-over-current; 396 dr_mode = "otg"; 397 pinctrl-0 = <&pinctrl_usbotg>; 398 pinctrl-names = "default"; 399 vbus-supply = <®_usb_otg_vbus>; 400 status = "okay"; 401}; 402 403&usdhc2 { /* External SD card via DHCOM */ 404 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 405 keep-power-in-suspend; 406 pinctrl-0 = <&pinctrl_usdhc2>; 407 pinctrl-names = "default"; 408 status = "disabled"; 409}; 410 411&usdhc3 { /* Micro SD card on module */ 412 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 413 fsl,wp-controller; 414 keep-power-in-suspend; 415 pinctrl-0 = <&pinctrl_usdhc3>; 416 pinctrl-names = "default"; 417 status = "okay"; 418}; 419 420&usdhc4 { /* eMMC on module */ 421 bus-width = <8>; 422 keep-power-in-suspend; 423 no-1-8-v; 424 non-removable; 425 pinctrl-0 = <&pinctrl_usdhc4>; 426 pinctrl-names = "default"; 427 status = "okay"; 428}; 429 430&weim { 431 #address-cells = <2>; 432 #size-cells = <1>; 433 fsl,weim-cs-gpr = <&gpr>; 434 pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>; 435 pinctrl-names = "default"; 436 /* It is necessary to setup 2x 64MB otherwise setting gpr fails */ 437 ranges = <0 0 0x08000000 0x04000000>, /* CS0 */ 438 <1 0 0x0c000000 0x04000000>; /* CS1 */ 439 status = "disabled"; 440}; 441 442&iomuxc { 443 pinctrl-0 = < 444 &pinctrl_hog_base 445 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 446 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 447 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i 448 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 449 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o 450 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r 451 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u 452 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int 453 >; 454 pinctrl-names = "default"; 455 456 pinctrl_hog_base: hog-base-grp { 457 fsl,pins = < 458 /* GPIOs for memory coding */ 459 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 460 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 461 /* GPIOs for hardware coding */ 462 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 463 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 464 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 465 >; 466 }; 467 468 /* DHCOM GPIOs */ 469 pinctrl_dhcom_a: dhcom-a-grp { 470 fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>; 471 }; 472 473 pinctrl_dhcom_b: dhcom-b-grp { 474 fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>; 475 }; 476 477 pinctrl_dhcom_c: dhcom-c-grp { 478 fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>; 479 }; 480 481 pinctrl_dhcom_d: dhcom-d-grp { 482 fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>; 483 }; 484 485 pinctrl_dhcom_e: dhcom-e-grp { 486 fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>; 487 }; 488 489 pinctrl_dhcom_f: dhcom-f-grp { 490 fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>; 491 }; 492 493 pinctrl_dhcom_g: dhcom-g-grp { 494 fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>; 495 }; 496 497 pinctrl_dhcom_h: dhcom-h-grp { 498 fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>; 499 }; 500 501 pinctrl_dhcom_i: dhcom-i-grp { 502 fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>; 503 }; 504 505 pinctrl_dhcom_j: dhcom-j-grp { 506 fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>; 507 }; 508 509 pinctrl_dhcom_k: dhcom-k-grp { 510 fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>; 511 }; 512 513 pinctrl_dhcom_l: dhcom-l-grp { 514 fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>; 515 }; 516 517 pinctrl_dhcom_m: dhcom-m-grp { 518 fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>; 519 }; 520 521 pinctrl_dhcom_n: dhcom-n-grp { 522 fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>; 523 }; 524 525 pinctrl_dhcom_o: dhcom-o-grp { 526 fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>; 527 }; 528 529 pinctrl_dhcom_p: dhcom-p-grp { 530 fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>; 531 }; 532 533 pinctrl_dhcom_q: dhcom-q-grp { 534 fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>; 535 }; 536 537 pinctrl_dhcom_r: dhcom-r-grp { 538 fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>; 539 }; 540 541 pinctrl_dhcom_s: dhcom-s-grp { 542 fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>; 543 }; 544 545 pinctrl_dhcom_t: dhcom-t-grp { 546 fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>; 547 }; 548 549 pinctrl_dhcom_u: dhcom-u-grp { 550 fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>; 551 }; 552 553 pinctrl_dhcom_v: dhcom-v-grp { 554 fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>; 555 }; 556 557 pinctrl_dhcom_w: dhcom-w-grp { 558 fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>; 559 }; 560 561 pinctrl_dhcom_int: dhcom-int-grp { 562 fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>; 563 }; 564 565 pinctrl_ecspi1: ecspi1-grp { 566 fsl,pins = < 567 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 568 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 569 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 570 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 571 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 572 >; 573 }; 574 575 pinctrl_ecspi2: ecspi2-grp { 576 fsl,pins = < 577 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 578 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 579 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 580 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 581 >; 582 }; 583 584 pinctrl_enet_100M: enet-100M-grp { 585 fsl,pins = < 586 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 587 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 588 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 589 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 590 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 591 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 592 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 593 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 594 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 595 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 596 >; 597 }; 598 599 pinctrl_enet_vio: enet-vio-grp { 600 fsl,pins = < 601 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 602 >; 603 }; 604 605 pinctrl_ethphy0: ethphy0-grp { 606 fsl,pins = < 607 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */ 608 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */ 609 >; 610 }; 611 612 pinctrl_flexcan1: flexcan1-grp { 613 fsl,pins = < 614 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 615 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 616 >; 617 }; 618 619 pinctrl_flexcan2: flexcan2-grp { 620 fsl,pins = < 621 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 622 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 623 >; 624 }; 625 626 pinctrl_i2c1: i2c1-grp { 627 fsl,pins = < 628 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 629 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 630 >; 631 }; 632 633 pinctrl_i2c1_gpio: i2c1-gpio-grp { 634 fsl,pins = < 635 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 636 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 637 >; 638 }; 639 640 pinctrl_i2c2: i2c2-grp { 641 fsl,pins = < 642 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 643 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 644 >; 645 }; 646 647 pinctrl_i2c2_gpio: i2c2-gpio-grp { 648 fsl,pins = < 649 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 650 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 651 >; 652 }; 653 654 pinctrl_i2c3: i2c3-grp { 655 fsl,pins = < 656 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 657 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 658 >; 659 }; 660 661 pinctrl_i2c3_gpio: i2c3-gpio-grp { 662 fsl,pins = < 663 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 664 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 665 >; 666 }; 667 668 pinctrl_ipu1_lcdif: ipu1-lcdif-grp { 669 fsl,pins = < 670 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 671 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 672 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 673 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 674 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 675 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 676 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 677 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 678 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 679 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 680 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 681 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 682 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 683 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 684 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 685 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 686 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 687 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 688 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 689 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 690 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 691 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 692 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 693 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 694 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 695 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 696 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 697 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 698 >; 699 }; 700 701 pinctrl_pcie: pcie-grp { 702 fsl,pins = < 703 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ 704 >; 705 }; 706 707 pinctrl_pmic: pmic-grp { 708 fsl,pins = < 709 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 710 >; 711 }; 712 713 pinctrl_pwm1: pwm1-grp { 714 fsl,pins = < 715 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 716 >; 717 }; 718 719 pinctrl_rtc: rtc-grp { 720 fsl,pins = < 721 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0 722 >; 723 }; 724 725 pinctrl_tsc2004: tsc2004-grp { 726 fsl,pins = < 727 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0 728 >; 729 }; 730 731 pinctrl_uart1: uart1-grp { 732 fsl,pins = < 733 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 734 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 735 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 736 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 737 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 738 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 739 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 740 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 741 >; 742 }; 743 744 pinctrl_uart4: uart4-grp { 745 fsl,pins = < 746 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 747 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 748 >; 749 }; 750 751 pinctrl_uart5: uart5-grp { 752 fsl,pins = < 753 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 754 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 755 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 756 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1 757 >; 758 }; 759 760 pinctrl_usbh1: usbh1-grp { 761 fsl,pins = < 762 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0 763 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1 764 >; 765 }; 766 767 pinctrl_usbotg: usbotg-grp { 768 fsl,pins = < 769 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 770 >; 771 }; 772 773 pinctrl_usdhc2: usdhc2-grp { 774 fsl,pins = < 775 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0 776 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 777 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 778 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 779 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 780 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 781 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 782 >; 783 }; 784 785 pinctrl_usdhc3: usdhc3-grp { 786 fsl,pins = < 787 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 788 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 789 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 790 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 791 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 792 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 793 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0 794 >; 795 }; 796 797 pinctrl_usdhc4: usdhc4-grp { 798 fsl,pins = < 799 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 800 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 801 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 802 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 803 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 804 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 805 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 806 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 807 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 808 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 809 >; 810 }; 811 812 pinctrl_weim: weim-grp { 813 fsl,pins = < 814 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6 815 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6 816 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6 817 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6 818 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6 819 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6 820 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6 821 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6 822 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6 823 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6 824 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6 825 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6 826 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6 827 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6 828 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6 829 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6 830 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 831 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */ 832 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6 833 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */ 834 >; 835 }; 836 837 pinctrl_weim_cs0: weim-cs0-grp { 838 fsl,pins = < 839 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 840 >; 841 }; 842 843 pinctrl_weim_cs1: weim-cs1-grp { 844 fsl,pins = < 845 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 846 >; 847 }; 848}; 849