1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * support for the imx6 based aristainetos2 board 4 * 5 * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 6 */ 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/imx6qdl-clock.h> 9 10/ { 11 backlight: backlight { 12 compatible = "pwm-backlight"; 13 pwms = <&pwm1 0 5000000 0>; 14 brightness-levels = <0 4 8 16 32 64 128 255>; 15 default-brightness-level = <7>; 16 enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; 17 }; 18 19 reg_2p5v: regulator-2p5v { 20 compatible = "regulator-fixed"; 21 regulator-name = "2P5V"; 22 regulator-min-microvolt = <2500000>; 23 regulator-max-microvolt = <2500000>; 24 regulator-always-on; 25 }; 26 27 reg_3p3v: regulator-3p3v { 28 compatible = "regulator-fixed"; 29 regulator-name = "3P3V"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 regulator-always-on; 33 }; 34 35 reg_usbh1_vbus: regulator-usbh1-vbus { 36 compatible = "regulator-fixed"; 37 enable-active-high; 38 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; 41 regulator-name = "usb_h1_vbus"; 42 regulator-min-microvolt = <5000000>; 43 regulator-max-microvolt = <5000000>; 44 }; 45 46 reg_usbotg_vbus: regulator-usbotg-vbus { 47 compatible = "regulator-fixed"; 48 enable-active-high; 49 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; 52 regulator-name = "usb_otg_vbus"; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 }; 56}; 57 58&audmux { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_audmux>; 61 status = "okay"; 62}; 63 64&can1 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_flexcan1>; 67 status = "okay"; 68}; 69 70&can2 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_flexcan2>; 73 status = "okay"; 74}; 75 76&ecspi1 { 77 cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW 78 &gpio4 10 GPIO_ACTIVE_LOW 79 &gpio4 11 GPIO_ACTIVE_LOW>; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_ecspi1>; 82 status = "okay"; 83}; 84 85&ecspi2 { 86 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_ecspi2>; 89 status = "okay"; 90}; 91 92&ecspi4 { 93 cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_ecspi4>; 96 status = "okay"; 97 98 flash: flash@1 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "micron,n25q128a11", "jedec,spi-nor"; 102 spi-max-frequency = <20000000>; 103 reg = <1>; 104 }; 105}; 106 107&i2c1 { 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_i2c1>; 110 status = "okay"; 111 112 pmic@58 { 113 compatible = "dlg,da9063"; 114 reg = <0x58>; 115 interrupt-parent = <&gpio1>; 116 interrupts = <04 0x8>; 117 #interrupt-cells = <2>; 118 interrupt-controller; 119 120 regulators { 121 bcore1 { 122 regulator-name = "bcore1"; 123 regulator-always-on; 124 regulator-min-microvolt = <300000>; 125 regulator-max-microvolt = <3300000>; 126 }; 127 128 bcore2 { 129 regulator-name = "bcore2"; 130 regulator-always-on; 131 regulator-min-microvolt = <300000>; 132 regulator-max-microvolt = <3300000>; 133 }; 134 135 bpro { 136 regulator-name = "bpro"; 137 regulator-always-on; 138 regulator-min-microvolt = <300000>; 139 regulator-max-microvolt = <3300000>; 140 }; 141 142 bperi { 143 regulator-name = "bperi"; 144 regulator-always-on; 145 regulator-min-microvolt = <300000>; 146 regulator-max-microvolt = <3300000>; 147 }; 148 149 bmem { 150 regulator-name = "bmem"; 151 regulator-always-on; 152 regulator-min-microvolt = <300000>; 153 regulator-max-microvolt = <3300000>; 154 }; 155 156 ldo2 { 157 regulator-name = "ldo2"; 158 regulator-always-on; 159 regulator-min-microvolt = <300000>; 160 regulator-max-microvolt = <1800000>; 161 }; 162 163 ldo3 { 164 regulator-name = "ldo3"; 165 regulator-always-on; 166 regulator-min-microvolt = <300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 170 ldo4 { 171 regulator-name = "ldo4"; 172 regulator-always-on; 173 regulator-min-microvolt = <300000>; 174 regulator-max-microvolt = <3300000>; 175 }; 176 177 ldo5 { 178 regulator-name = "ldo5"; 179 regulator-always-on; 180 regulator-min-microvolt = <300000>; 181 regulator-max-microvolt = <3300000>; 182 }; 183 184 ldo6 { 185 regulator-name = "ldo6"; 186 regulator-always-on; 187 regulator-min-microvolt = <300000>; 188 regulator-max-microvolt = <3300000>; 189 }; 190 191 ldo7 { 192 regulator-name = "ldo7"; 193 regulator-always-on; 194 regulator-min-microvolt = <300000>; 195 regulator-max-microvolt = <3300000>; 196 }; 197 198 ldo8 { 199 regulator-name = "ldo8"; 200 regulator-always-on; 201 regulator-min-microvolt = <300000>; 202 regulator-max-microvolt = <3300000>; 203 }; 204 205 ldo9 { 206 regulator-name = "ldo9"; 207 regulator-always-on; 208 regulator-min-microvolt = <300000>; 209 regulator-max-microvolt = <3300000>; 210 }; 211 212 ldo10 { 213 regulator-name = "ldo10"; 214 regulator-always-on; 215 regulator-min-microvolt = <300000>; 216 regulator-max-microvolt = <3300000>; 217 }; 218 219 ldo11 { 220 regulator-name = "ldo11"; 221 regulator-always-on; 222 regulator-min-microvolt = <300000>; 223 regulator-max-microvolt = <3300000>; 224 }; 225 226 bio { 227 regulator-name = "bio"; 228 regulator-always-on; 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <1800000>; 231 }; 232 }; 233 }; 234 235 tmp103: tmp103@71 { 236 compatible = "ti,tmp103"; 237 reg = <0x71>; 238 }; 239}; 240 241&i2c2 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_i2c2>; 244 status = "okay"; 245}; 246 247&i2c3 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_i2c3>; 250 status = "okay"; 251 252 expander: tca6416@20 { 253 compatible = "ti,tca6416"; 254 reg = <0x20>; 255 #gpio-cells = <2>; 256 gpio-controller; 257 }; 258 259 rtc@68 { 260 compatible = "dallas,m41t00"; 261 reg = <0x68>; 262 }; 263}; 264 265&i2c4 { 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_i2c4>; 268 status = "okay"; 269 270 eeprom@50 { 271 compatible = "atmel,24c64"; 272 reg = <0x50>; 273 }; 274 275 eeprom@57 { 276 compatible = "atmel,24c64"; 277 reg = <0x57>; 278 }; 279}; 280 281&fec { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_enet>; 284 phy-mode = "rgmii"; 285 phy-handle = <ðphy>; 286 phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; 287 status = "okay"; 288 289 mdio { 290 #address-cells = <1>; 291 #size-cells = <0>; 292 293 ethphy: ethernet-phy@0 { 294 compatible = "ethernet-phy-ieee802.3-c22"; 295 reg = <0>; 296 txd0-skew-ps = <0>; 297 txd1-skew-ps = <0>; 298 txd2-skew-ps = <0>; 299 txd3-skew-ps = <0>; 300 }; 301 }; 302}; 303 304&gpmi { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_gpmi_nand>; 307 status = "okay"; 308}; 309 310&pcie { 311 reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; 312 status = "okay"; 313}; 314 315&pwm1 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_pwm1>; 318 status = "okay"; 319}; 320 321&uart1 { 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_uart1>; 324 uart-has-rtscts; 325 status = "okay"; 326}; 327 328&uart2 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart2>; 331 status = "okay"; 332}; 333 334&uart3 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart3>; 337 uart-has-rtscts; 338 status = "okay"; 339}; 340 341&uart4 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_uart4>; 344 status = "okay"; 345}; 346 347&usbh1 { 348 vbus-supply = <®_usbh1_vbus>; 349 dr_mode = "host"; 350 status = "okay"; 351}; 352 353&usbotg { 354 vbus-supply = <®_usbotg_vbus>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_usbotg>; 357 disable-over-current; 358 dr_mode = "host"; 359 status = "okay"; 360}; 361 362&usdhc1 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_usdhc1>; 365 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 366 no-1-8-v; 367 status = "okay"; 368}; 369 370&usdhc2 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pinctrl_usdhc2>; 373 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; 374 wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 375 no-1-8-v; 376 status = "okay"; 377}; 378 379&iomuxc { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pinctrl_gpio>; 382 383 pinctrl_audmux: audmuxgrp { 384 fsl,pins = < 385 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 386 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 387 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 388 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 389 >; 390 }; 391 392 pinctrl_ecspi1: ecspi1grp { 393 fsl,pins = < 394 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 395 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 396 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 397 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ 398 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ 399 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ 400 >; 401 }; 402 403 pinctrl_ecspi2: ecspi2grp { 404 fsl,pins = < 405 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 406 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 407 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 408 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ 409 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ 410 >; 411 }; 412 413 pinctrl_ecspi4: ecspi4grp { 414 fsl,pins = < 415 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 416 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 417 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 418 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ 419 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ 420 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ 421 >; 422 }; 423 424 pinctrl_enet: enetgrp { 425 fsl,pins = < 426 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 427 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 428 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 429 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 430 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 431 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 432 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 433 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 434 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 435 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 436 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 437 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 438 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 439 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 440 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 441 >; 442 }; 443 444 pinctrl_flexcan1: flexcan1grp { 445 fsl,pins = < 446 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 447 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 448 >; 449 }; 450 451 pinctrl_flexcan2: flexcan2grp { 452 fsl,pins = < 453 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 454 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 455 >; 456 }; 457 458 pinctrl_gpio: gpiogrp { 459 fsl,pins = < 460 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ 461 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ 462 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ 463 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ 464 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ 465 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ 466 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ 467 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ 468 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ 469 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ 470 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ 471 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ 472 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ 473 >; 474 }; 475 476 pinctrl_gpmi_nand: gpminandgrp { 477 fsl,pins = < 478 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 479 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 480 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 481 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 482 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 483 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 484 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 485 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 486 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 487 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 488 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 489 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 490 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 491 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 492 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 493 >; 494 }; 495 496 pinctrl_i2c1: i2c1grp { 497 fsl,pins = < 498 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 499 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 500 >; 501 }; 502 503 pinctrl_i2c2: i2c2grp { 504 fsl,pins = < 505 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 506 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 507 >; 508 }; 509 510 pinctrl_i2c3: i2c3grp { 511 fsl,pins = < 512 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 513 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 514 >; 515 }; 516 517 pinctrl_i2c4: i2c4grp { 518 fsl,pins = < 519 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 520 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 521 >; 522 }; 523 524 pinctrl_pwm1: pwm1grp { 525 fsl,pins = < 526 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 527 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ 528 >; 529 }; 530 531 pinctrl_uart1: uart1grp { 532 fsl,pins = < 533 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 534 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 535 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 536 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 537 >; 538 }; 539 540 pinctrl_uart2: uart2grp { 541 fsl,pins = < 542 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 543 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 544 >; 545 }; 546 547 pinctrl_uart3: uart3grp { 548 fsl,pins = < 549 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 550 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 551 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 552 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 553 >; 554 }; 555 556 pinctrl_uart4: uart4grp { 557 fsl,pins = < 558 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 559 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 560 >; 561 }; 562 563 pinctrl_usbotg: usbotggrp { 564 fsl,pins = < 565 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 566 >; 567 }; 568 569 pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbusgrp { 570 fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>; 571 }; 572 573 pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbusgrp { 574 fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>; 575 }; 576 577 pinctrl_usdhc1: usdhc1grp { 578 fsl,pins = < 579 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 580 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 581 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 582 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 583 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 584 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 585 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ 586 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ 587 >; 588 }; 589 590 pinctrl_usdhc2: usdhc2grp { 591 fsl,pins = < 592 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 593 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 594 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 595 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 596 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 597 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 598 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ 599 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ 600 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ 601 >; 602 }; 603}; 604