1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2016-2017 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7/dts-v1/; 8 9#include "imx6q.dtsi" 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/pwm/pwm.h> 13 14/ { 15 model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; 16 compatible = "lwn,mccmon6", "fsl,imx6q"; 17 18 memory@10000000 { 19 device_type = "memory"; 20 reg = <0x10000000 0x80000000>; 21 }; 22 23 backlight_lvds: backlight { 24 compatible = "pwm-backlight"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_backlight>; 27 pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; 28 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 29 10 11 12 13 14 15 16 17 18 19 30 20 21 22 23 24 25 26 27 28 29 31 30 31 32 33 34 35 36 37 38 39 32 40 41 42 43 44 45 46 47 48 49 33 50 51 52 53 54 55 56 57 58 59 34 60 61 62 63 64 65 66 67 68 69 35 70 71 72 73 74 75 76 77 78 79 36 80 81 82 83 84 85 86 87 88 89 37 90 91 92 93 94 95 96 97 98 99 38 100 101 102 103 104 105 106 107 108 109 39 110 111 112 113 114 115 116 117 118 119 40 120 121 122 123 124 125 126 127 128 129 41 130 131 132 133 134 135 136 137 138 139 42 140 141 142 143 144 145 146 147 148 149 43 150 151 152 153 154 155 156 157 158 159 44 160 161 162 163 164 165 166 167 168 169 45 170 171 172 173 174 175 176 177 178 179 46 180 181 182 183 184 185 186 187 188 189 47 190 191 192 193 194 195 196 197 198 199 48 200 201 202 203 204 205 206 207 208 209 49 210 211 212 213 214 215 216 217 218 219 50 220 221 222 223 224 225 226 227 228 229 51 230 231 232 233 234 235 236 237 238 239 52 240 241 242 243 244 245 246 247 248 249 53 250 251 252 253 254 255>; 54 default-brightness-level = <50>; 55 enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 56 }; 57 58 reg_lvds: regulator-lvds { 59 compatible = "regulator-fixed"; 60 regulator-name = "lvds_ppen"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-boot-on; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_reg_lvds>; 66 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 }; 69 70 panel-lvds0 { 71 compatible = "innolux,g121x1-l03"; 72 backlight = <&backlight_lvds>; 73 power-supply = <®_lvds>; 74 75 port { 76 panel_in_lvds0: endpoint { 77 remote-endpoint = <&lvds0_out>; 78 }; 79 }; 80 }; 81}; 82 83&ecspi3 { 84 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; 87 status = "okay"; 88 89 s25sl032p: flash@0 { 90 #address-cells = <1>; 91 #size-cells = <1>; 92 compatible = "jedec,spi-nor"; 93 spi-max-frequency = <40000000>; 94 reg = <0>; 95 }; 96}; 97 98&fec { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_enet>; 101 phy-mode = "rgmii"; 102 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 103 /delete-property/ interrupts; 104 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 105 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 106 fsl,err006687-workaround-present; 107 status = "okay"; 108}; 109 110&i2c1 { 111 clock-frequency = <100000>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_i2c1>; 114 status = "okay"; 115}; 116 117&i2c2 { 118 clock-frequency = <100000>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_i2c2>; 121 status = "okay"; 122 123 pfuze100: pmic@8 { 124 compatible = "fsl,pfuze100"; 125 reg = <0x08>; 126 127 regulators { 128 sw1a_reg: sw1ab { 129 regulator-min-microvolt = <300000>; 130 regulator-max-microvolt = <1875000>; 131 regulator-boot-on; 132 regulator-always-on; 133 regulator-ramp-delay = <6250>; 134 }; 135 136 sw1c_reg: sw1c { 137 regulator-min-microvolt = <300000>; 138 regulator-max-microvolt = <1875000>; 139 regulator-boot-on; 140 regulator-always-on; 141 regulator-ramp-delay = <6250>; 142 }; 143 144 sw2_reg: sw2 { 145 regulator-min-microvolt = <800000>; 146 regulator-max-microvolt = <3950000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 sw3a_reg: sw3a { 152 regulator-min-microvolt = <400000>; 153 regulator-max-microvolt = <1975000>; 154 regulator-boot-on; 155 regulator-always-on; 156 }; 157 158 sw3b_reg: sw3b { 159 regulator-min-microvolt = <400000>; 160 regulator-max-microvolt = <1975000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 sw4_reg: sw4 { 166 regulator-min-microvolt = <800000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 170 swbst_reg: swbst { 171 regulator-min-microvolt = <5000000>; 172 regulator-max-microvolt = <5150000>; 173 }; 174 175 snvs_reg: vsnvs { 176 regulator-min-microvolt = <1000000>; 177 regulator-max-microvolt = <3000000>; 178 regulator-boot-on; 179 regulator-always-on; 180 }; 181 182 vref_reg: vrefddr { 183 regulator-boot-on; 184 regulator-always-on; 185 }; 186 187 vgen1_reg: vgen1 { 188 regulator-min-microvolt = <800000>; 189 regulator-max-microvolt = <1550000>; 190 }; 191 192 vgen2_reg: vgen2 { 193 regulator-min-microvolt = <800000>; 194 regulator-max-microvolt = <1550000>; 195 }; 196 197 vgen3_reg: vgen3 { 198 regulator-min-microvolt = <1800000>; 199 regulator-max-microvolt = <3300000>; 200 }; 201 202 vgen4_reg: vgen4 { 203 regulator-min-microvolt = <1800000>; 204 regulator-max-microvolt = <3300000>; 205 regulator-always-on; 206 }; 207 208 vgen5_reg: vgen5 { 209 regulator-min-microvolt = <1800000>; 210 regulator-max-microvolt = <3300000>; 211 regulator-always-on; 212 }; 213 214 vgen6_reg: vgen6 { 215 regulator-min-microvolt = <1800000>; 216 regulator-max-microvolt = <3300000>; 217 regulator-always-on; 218 }; 219 }; 220 }; 221}; 222 223&ldb { 224 status = "okay"; 225 226 lvds0: lvds-channel@0 { 227 fsl,data-mapping = "spwg"; 228 fsl,data-width = <24>; 229 status = "okay"; 230 231 port@4 { 232 reg = <4>; 233 234 lvds0_out: endpoint { 235 remote-endpoint = <&panel_in_lvds0>; 236 }; 237 }; 238 }; 239}; 240 241&pwm2 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_pwm2>; 244 status = "okay"; 245}; 246 247&uart1 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_uart1>; 250 status = "okay"; 251}; 252 253&uart4 { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_uart4>; 256 uart-has-rtscts; 257 status = "okay"; 258}; 259 260&usdhc2 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_usdhc2>; 263 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 264 bus-width = <4>; 265 status = "okay"; 266}; 267 268&usdhc3 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_usdhc3>; 271 bus-width = <8>; 272 non-removable; 273 status = "okay"; 274}; 275 276&weim { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; 279 ranges = <0 0 0x08000000 0x08000000>; 280 status = "okay"; 281 282 nor@0,0 { 283 compatible = "cfi-flash"; 284 reg = <0 0 0x02000000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 bank-width = <2>; 288 use-advanced-sector-protection; 289 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 290 0x0000c000 0x1404a38e 0x00000000>; 291 }; 292}; 293 294&iomuxc { 295 pinctrl-names = "default"; 296 297 pinctrl_backlight: dispgrp { 298 fsl,pins = < 299 /* BLEN_OUT */ 300 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 301 >; 302 }; 303 304 pinctrl_ecspi3: ecspi3grp { 305 fsl,pins = < 306 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 307 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 308 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 309 >; 310 }; 311 312 pinctrl_ecspi3_cs: ecspi3csgrp { 313 fsl,pins = < 314 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 315 >; 316 }; 317 318 pinctrl_ecspi3_flwp: ecspi3flwpgrp { 319 fsl,pins = < 320 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 321 >; 322 }; 323 324 pinctrl_enet: enetgrp { 325 fsl,pins = < 326 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 327 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 328 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 329 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 330 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 331 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 332 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 333 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 334 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 335 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 336 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 337 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 338 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 339 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 340 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 341 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 342 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 343 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 344 >; 345 }; 346 347 pinctrl_i2c1: i2c1grp { 348 fsl,pins = < 349 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 350 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 351 >; 352 }; 353 354 pinctrl_i2c2: i2c2grp { 355 fsl,pins = < 356 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 357 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 358 >; 359 }; 360 361 pinctrl_pwm2: pwm2grp { 362 fsl,pins = < 363 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 364 >; 365 }; 366 367 pinctrl_reg_lvds: reqlvdsgrp { 368 fsl,pins = < 369 /* LVDS_PPEN_OUT */ 370 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 371 >; 372 }; 373 374 pinctrl_uart1: uart1grp { 375 fsl,pins = < 376 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 377 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 378 >; 379 }; 380 381 pinctrl_uart4: uart4grp { 382 fsl,pins = < 383 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 384 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 385 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 386 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 387 >; 388 }; 389 390 pinctrl_usdhc2: usdhc2grp { 391 fsl,pins = < 392 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 393 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 394 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 395 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 396 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 397 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 398 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 399 >; 400 }; 401 402 pinctrl_usdhc3: usdhc3grp { 403 fsl,pins = < 404 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 405 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 406 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 407 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 408 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 409 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 410 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 411 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 412 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 413 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 414 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 415 >; 416 }; 417 418 pinctrl_weim_cs0: weimcs0grp { 419 fsl,pins = < 420 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 421 >; 422 }; 423 424 pinctrl_weim_nor: weimnorgrp { 425 fsl,pins = < 426 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 427 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 428 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 429 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 430 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 431 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 432 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 433 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 434 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 435 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 436 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 437 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 438 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 439 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 440 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 441 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 442 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 443 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 444 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 445 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 446 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 447 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 448 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 449 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 450 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 451 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 452 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 453 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 454 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 455 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 456 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 457 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 458 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 459 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 460 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 461 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 462 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 463 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 464 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 465 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 466 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 467 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 468 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 469 >; 470 }; 471}; 472