1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// 3// Copyright 2024 Comvetia AG 4 5/dts-v1/; 6#include "imx6q-phytec-pfla02.dtsi" 7 8/ { 9 model = "COMVETIA QSoIP LXR-2"; 10 compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; 11 12 chosen { 13 stdout-path = &uart4; 14 }; 15 16 spi { 17 compatible = "spi-gpio"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_spi_gpio>; 20 sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 21 mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; 22 num-chipselects = <0>; 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 fpga@0 { 27 compatible = "altr,fpga-passive-serial"; 28 reg = <0>; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_fpga>; 31 nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 32 nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 33 confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 34 }; 35 }; 36}; 37 38&ecspi3 { 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_ecspi3>; 41 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 42 status = "okay"; 43 44 flash@0 { 45 compatible = "jedec,spi-nor"; 46 reg = <0>; 47 spi-max-frequency = <20000000>; 48 }; 49}; 50 51&fec { 52 status = "okay"; 53}; 54 55&i2c3 { 56 status = "okay"; 57}; 58 59&uart3 { 60 status = "okay"; 61}; 62 63&uart4 { 64 status = "okay"; 65}; 66 67&usdhc3 { 68 no-1-8-v; 69 status = "okay"; 70}; 71 72&iomuxc { 73 pinctrl_fpga: fpgagrp { 74 fsl,pins = < 75 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 76 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 77 MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 78 >; 79 }; 80 81 pinctrl_spi_gpio: spigpiogrp { 82 fsl,pins = < 83 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 84 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 85 >; 86 }; 87}; 88