1*178edf15SFabio Estevam// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*178edf15SFabio Estevam// 3*178edf15SFabio Estevam// Copyright 2024 Comvetia AG 4*178edf15SFabio Estevam 5*178edf15SFabio Estevam/dts-v1/; 6*178edf15SFabio Estevam#include "imx6q-phytec-pfla02.dtsi" 7*178edf15SFabio Estevam 8*178edf15SFabio Estevam/ { 9*178edf15SFabio Estevam model = "COMVETIA QSoIP LXR-2"; 10*178edf15SFabio Estevam compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; 11*178edf15SFabio Estevam 12*178edf15SFabio Estevam chosen { 13*178edf15SFabio Estevam stdout-path = &uart4; 14*178edf15SFabio Estevam }; 15*178edf15SFabio Estevam 16*178edf15SFabio Estevam spi { 17*178edf15SFabio Estevam compatible = "spi-gpio"; 18*178edf15SFabio Estevam pinctrl-names = "default"; 19*178edf15SFabio Estevam pinctrl-0 = <&pinctrl_spi_gpio>; 20*178edf15SFabio Estevam sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 21*178edf15SFabio Estevam mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; 22*178edf15SFabio Estevam num-chipselects = <0>; 23*178edf15SFabio Estevam #address-cells = <1>; 24*178edf15SFabio Estevam #size-cells = <0>; 25*178edf15SFabio Estevam 26*178edf15SFabio Estevam fpga@0 { 27*178edf15SFabio Estevam compatible = "altr,fpga-passive-serial"; 28*178edf15SFabio Estevam reg = <0>; 29*178edf15SFabio Estevam pinctrl-names = "default"; 30*178edf15SFabio Estevam pinctrl-0 = <&pinctrl_fpga>; 31*178edf15SFabio Estevam nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 32*178edf15SFabio Estevam nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 33*178edf15SFabio Estevam confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 34*178edf15SFabio Estevam }; 35*178edf15SFabio Estevam }; 36*178edf15SFabio Estevam}; 37*178edf15SFabio Estevam 38*178edf15SFabio Estevam&ecspi3 { 39*178edf15SFabio Estevam pinctrl-names = "default"; 40*178edf15SFabio Estevam pinctrl-0 = <&pinctrl_ecspi3>; 41*178edf15SFabio Estevam cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 42*178edf15SFabio Estevam status = "okay"; 43*178edf15SFabio Estevam 44*178edf15SFabio Estevam flash@0 { 45*178edf15SFabio Estevam compatible = "jedec,spi-nor"; 46*178edf15SFabio Estevam reg = <0>; 47*178edf15SFabio Estevam spi-max-frequency = <20000000>; 48*178edf15SFabio Estevam }; 49*178edf15SFabio Estevam}; 50*178edf15SFabio Estevam 51*178edf15SFabio Estevam&fec { 52*178edf15SFabio Estevam status = "okay"; 53*178edf15SFabio Estevam}; 54*178edf15SFabio Estevam 55*178edf15SFabio Estevam&i2c3 { 56*178edf15SFabio Estevam status = "okay"; 57*178edf15SFabio Estevam}; 58*178edf15SFabio Estevam 59*178edf15SFabio Estevam&uart3 { 60*178edf15SFabio Estevam status = "okay"; 61*178edf15SFabio Estevam}; 62*178edf15SFabio Estevam 63*178edf15SFabio Estevam&uart4 { 64*178edf15SFabio Estevam status = "okay"; 65*178edf15SFabio Estevam}; 66*178edf15SFabio Estevam 67*178edf15SFabio Estevam&usdhc3 { 68*178edf15SFabio Estevam no-1-8-v; 69*178edf15SFabio Estevam status = "okay"; 70*178edf15SFabio Estevam}; 71*178edf15SFabio Estevam 72*178edf15SFabio Estevam&iomuxc { 73*178edf15SFabio Estevam pinctrl_fpga: fpgagrp { 74*178edf15SFabio Estevam fsl,pins = < 75*178edf15SFabio Estevam MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 76*178edf15SFabio Estevam MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 77*178edf15SFabio Estevam MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 78*178edf15SFabio Estevam >; 79*178edf15SFabio Estevam }; 80*178edf15SFabio Estevam 81*178edf15SFabio Estevam pinctrl_spi_gpio: spigpiogrp { 82*178edf15SFabio Estevam fsl,pins = < 83*178edf15SFabio Estevam MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 84*178edf15SFabio Estevam MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 85*178edf15SFabio Estevam >; 86*178edf15SFabio Estevam }; 87*178edf15SFabio Estevam}; 88