xref: /linux/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright 2013 Gateworks Corporation
4*724ba675SRob Herring */
5*724ba675SRob Herring
6*724ba675SRob Herring/dts-v1/;
7*724ba675SRob Herring#include "imx6q.dtsi"
8*724ba675SRob Herring#include "imx6qdl-gw53xx.dtsi"
9*724ba675SRob Herring
10*724ba675SRob Herring/ {
11*724ba675SRob Herring	model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
12*724ba675SRob Herring	compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
13*724ba675SRob Herring};
14*724ba675SRob Herring
15*724ba675SRob Herring&i2c3 {
16*724ba675SRob Herring	adv7180: camera@20 {
17*724ba675SRob Herring		compatible = "adi,adv7180";
18*724ba675SRob Herring		pinctrl-names = "default";
19*724ba675SRob Herring		pinctrl-0 = <&pinctrl_adv7180>;
20*724ba675SRob Herring		reg = <0x20>;
21*724ba675SRob Herring		powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
22*724ba675SRob Herring		interrupt-parent = <&gpio3>;
23*724ba675SRob Herring		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
24*724ba675SRob Herring
25*724ba675SRob Herring		port {
26*724ba675SRob Herring			adv7180_to_ipu2_csi1_mux: endpoint {
27*724ba675SRob Herring				remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
28*724ba675SRob Herring				bus-width = <8>;
29*724ba675SRob Herring			};
30*724ba675SRob Herring		};
31*724ba675SRob Herring	};
32*724ba675SRob Herring};
33*724ba675SRob Herring
34*724ba675SRob Herring&ipu2_csi1_from_ipu2_csi1_mux {
35*724ba675SRob Herring	bus-width = <8>;
36*724ba675SRob Herring};
37*724ba675SRob Herring
38*724ba675SRob Herring&ipu2_csi1_mux_from_parallel_sensor {
39*724ba675SRob Herring	remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
40*724ba675SRob Herring	bus-width = <8>;
41*724ba675SRob Herring};
42*724ba675SRob Herring
43*724ba675SRob Herring&ipu2_csi1 {
44*724ba675SRob Herring	pinctrl-names = "default";
45*724ba675SRob Herring	pinctrl-0 = <&pinctrl_ipu2_csi1>;
46*724ba675SRob Herring};
47*724ba675SRob Herring
48*724ba675SRob Herring&sata {
49*724ba675SRob Herring	status = "okay";
50*724ba675SRob Herring};
51*724ba675SRob Herring
52*724ba675SRob Herring&iomuxc {
53*724ba675SRob Herring	pinctrl_adv7180: adv7180grp {
54*724ba675SRob Herring		fsl,pins = <
55*724ba675SRob Herring			MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
56*724ba675SRob Herring			MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
57*724ba675SRob Herring		>;
58*724ba675SRob Herring	};
59*724ba675SRob Herring
60*724ba675SRob Herring	pinctrl_ipu2_csi1: ipu2_csi1grp {
61*724ba675SRob Herring		fsl,pins = <
62*724ba675SRob Herring			MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
63*724ba675SRob Herring			MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
64*724ba675SRob Herring			MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
65*724ba675SRob Herring			MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
66*724ba675SRob Herring			MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
67*724ba675SRob Herring			MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
68*724ba675SRob Herring			MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
69*724ba675SRob Herring			MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
70*724ba675SRob Herring			MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
71*724ba675SRob Herring			MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
72*724ba675SRob Herring			MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
73*724ba675SRob Herring		>;
74*724ba675SRob Herring	};
75*724ba675SRob Herring};
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