1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2017 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7/dts-v1/; 8 9#include "imx6q.dtsi" 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/pwm/pwm.h> 13#include <dt-bindings/sound/fsl-imx-audmux.h> 14 15/ { 16 model = "Liebherr (LWN) display5 i.MX6 Quad Board"; 17 compatible = "lwn,display5", "fsl,imx6q"; 18 19 memory@10000000 { 20 device_type = "memory"; 21 reg = <0x10000000 0x40000000>; 22 }; 23 24 backlight_lvds: backlight { 25 compatible = "pwm-backlight"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_backlight>; 28 pwms = <&pwm2 0 5000000 0>; 29 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 30 10 11 12 13 14 15 16 17 18 19 31 20 21 22 23 24 25 26 27 28 29 32 30 31 32 33 34 35 36 37 38 39 33 40 41 42 43 44 45 46 47 48 49 34 50 51 52 53 54 55 56 57 58 59 35 60 61 62 63 64 65 66 67 68 69 36 70 71 72 73 74 75 76 77 78 79 37 80 81 82 83 84 85 86 87 88 89 38 90 91 92 93 94 95 96 97 98 99 39 100 101 102 103 104 105 106 107 108 109 40 110 111 112 113 114 115 116 117 118 119 41 120 121 122 123 124 125 126 127 128 129 42 130 131 132 133 134 135 136 137 138 139 43 140 141 142 143 144 145 146 147 148 149 44 150 151 152 153 154 155 156 157 158 159 45 160 161 162 163 164 165 166 167 168 169 46 170 171 172 173 174 175 176 177 178 179 47 180 181 182 183 184 185 186 187 188 189 48 190 191 192 193 194 195 196 197 198 199 49 200 201 202 203 204 205 206 207 208 209 50 210 211 212 213 214 215 216 217 218 219 51 220 221 222 223 224 225 226 227 228 229 52 230 231 232 233 234 235 236 237 238 239 53 240 241 242 243 244 245 246 247 248 249 54 250 251 252 253 254 255>; 55 default-brightness-level = <250>; 56 enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; 57 }; 58 59 reg_lvds: regulator-lvds { 60 compatible = "regulator-fixed"; 61 regulator-name = "lvds_ppen"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 regulator-boot-on; 65 regulator-always-on; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_reg_lvds>; 68 gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_usbh1_vbus: usb-h1-vbus { 73 compatible = "regulator-fixed"; 74 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_usbh1_vbus>; 77 regulator-name = "usb_h1_vbus"; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 regulator-enable-ramp-delay = <300000>; 81 }; 82 83 sound { 84 compatible = "simple-audio-card"; 85 label = "tfa9879-mono"; 86 87 simple-audio-card,dai-link { 88 /* DAC */ 89 format = "i2s"; 90 bitclock-master = <&dailink_master>; 91 frame-master = <&dailink_master>; 92 93 dailink_master: cpu { 94 sound-dai = <&ssi2>; 95 }; 96 codec { 97 sound-dai = <&codec>; 98 }; 99 }; 100 }; 101 102 panel: panel-lvds0 { 103 backlight = <&backlight_lvds>; 104 power-supply = <®_lvds>; 105 106 port { 107 panel_in_lvds0: endpoint { 108 remote-endpoint = <&lvds0_out>; 109 }; 110 }; 111 }; 112}; 113 114&audmux { 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_audmux>; 117 status = "okay"; 118 119 mux-ssi2 { 120 fsl,audmux-port = <1>; 121 fsl,port-config = < 122 (IMX_AUDMUX_V2_PTCR_SYN | 123 IMX_AUDMUX_V2_PTCR_TFSEL(5) | 124 IMX_AUDMUX_V2_PTCR_TCSEL(5) | 125 IMX_AUDMUX_V2_PTCR_TFSDIR | 126 IMX_AUDMUX_V2_PTCR_TCLKDIR) 127 IMX_AUDMUX_V2_PDCR_RXDSEL(5) 128 >; 129 }; 130 131 mux-aud6 { 132 fsl,audmux-port = <5>; 133 fsl,port-config = < 134 (IMX_AUDMUX_V2_PTCR_RFSEL(8) | 135 IMX_AUDMUX_V2_PTCR_RCSEL(8) | 136 IMX_AUDMUX_V2_PTCR_TFSEL(1) | 137 IMX_AUDMUX_V2_PTCR_TCSEL(1) | 138 IMX_AUDMUX_V2_PTCR_RFSDIR | 139 IMX_AUDMUX_V2_PTCR_RCLKDIR | 140 IMX_AUDMUX_V2_PTCR_TFSDIR | 141 IMX_AUDMUX_V2_PTCR_TCLKDIR) 142 IMX_AUDMUX_V2_PDCR_RXDSEL(1) 143 >; 144 }; 145}; 146 147&ecspi2 { 148 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; 151 status = "okay"; 152 153 s25fl256s: flash@0 { 154 #address-cells = <1>; 155 #size-cells = <1>; 156 compatible = "jedec,spi-nor"; 157 spi-max-frequency = <40000000>; 158 reg = <0>; 159 160 partition@0 { 161 label = "SPL (spi)"; 162 reg = <0x0 0x20000>; 163 read-only; 164 }; 165 partition@1 { 166 label = "u-boot (spi)"; 167 reg = <0x20000 0x100000>; 168 read-only; 169 }; 170 partition@2 { 171 label = "uboot-env (spi)"; 172 reg = <0x120000 0x10000>; 173 }; 174 partition@3 { 175 label = "uboot-envr (spi)"; 176 reg = <0x130000 0x10000>; 177 }; 178 partition@4 { 179 label = "linux-recovery (spi)"; 180 reg = <0x140000 0x800000>; 181 }; 182 partition@5 { 183 label = "swupdate-fitImg (spi)"; 184 reg = <0x940000 0x400000>; 185 }; 186 partition@6 { 187 label = "swupdate-initramfs (spi)"; 188 reg = <0xD40000 0x800000>; 189 }; 190 }; 191}; 192 193&ecspi3 { 194 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; 197 status = "okay"; 198}; 199 200&fec { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_enet>; 203 phy-handle = <ðernet_phy0>; 204 phy-mode = "rgmii-id"; 205 status = "okay"; 206 207 mdio { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 ethernet_phy0: ethernet-phy@0 { 211 compatible = "marvell,88E1510"; 212 device_type = "ethernet-phy"; 213 /* Set LED0 control: */ 214 /* On - Link, Blink - Activity, Off - No Link */ 215 marvell,reg-init = <3 0x10 0 0x1011>; 216 max-speed = <100>; 217 reg = <0>; 218 }; 219 }; 220}; 221 222&i2c1 { 223 clock-frequency = <400000>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_i2c1>; 226 status = "okay"; 227 228 codec: tfa9879@6c { 229 #sound-dai-cells = <0>; 230 compatible = "nxp,tfa9879"; 231 reg = <0x6C>; 232 }; 233}; 234 235&i2c2 { 236 clock-frequency = <400000>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_i2c2>; 239 status = "okay"; 240}; 241 242&i2c3 { 243 clock-frequency = <400000>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c3>; 246 status = "okay"; 247 248 eeprom@50 { 249 compatible = "atmel,24c256"; 250 pagesize = <64>; 251 reg = <0x50>; 252 }; 253 254 pfuze100: pmic@8 { 255 compatible = "fsl,pfuze100"; 256 reg = <0x08>; 257 258 regulators { 259 sw1a_reg: sw1ab { 260 regulator-min-microvolt = <300000>; 261 regulator-max-microvolt = <1875000>; 262 regulator-boot-on; 263 regulator-always-on; 264 regulator-ramp-delay = <6250>; 265 }; 266 267 sw1c_reg: sw1c { 268 regulator-min-microvolt = <300000>; 269 regulator-max-microvolt = <1875000>; 270 regulator-boot-on; 271 regulator-always-on; 272 regulator-ramp-delay = <6250>; 273 }; 274 275 sw2_reg: sw2 { 276 regulator-min-microvolt = <800000>; 277 regulator-max-microvolt = <3950000>; 278 regulator-boot-on; 279 regulator-always-on; 280 }; 281 282 sw3a_reg: sw3a { 283 regulator-min-microvolt = <400000>; 284 regulator-max-microvolt = <1975000>; 285 regulator-boot-on; 286 regulator-always-on; 287 }; 288 289 sw3b_reg: sw3b { 290 regulator-min-microvolt = <400000>; 291 regulator-max-microvolt = <1975000>; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 sw4_reg: sw4 { 297 regulator-min-microvolt = <800000>; 298 regulator-max-microvolt = <3300000>; 299 }; 300 301 swbst_reg: swbst { 302 regulator-min-microvolt = <5000000>; 303 regulator-max-microvolt = <5150000>; 304 }; 305 306 snvs_reg: vsnvs { 307 regulator-min-microvolt = <1000000>; 308 regulator-max-microvolt = <3000000>; 309 regulator-boot-on; 310 regulator-always-on; 311 }; 312 313 vref_reg: vrefddr { 314 regulator-boot-on; 315 regulator-always-on; 316 }; 317 318 vgen1_reg: vgen1 { 319 regulator-min-microvolt = <800000>; 320 regulator-max-microvolt = <1550000>; 321 }; 322 323 vgen2_reg: vgen2 { 324 regulator-min-microvolt = <800000>; 325 regulator-max-microvolt = <1550000>; 326 }; 327 328 vgen3_reg: vgen3 { 329 regulator-min-microvolt = <1800000>; 330 regulator-max-microvolt = <3300000>; 331 }; 332 333 vgen4_reg: vgen4 { 334 regulator-min-microvolt = <1800000>; 335 regulator-max-microvolt = <3300000>; 336 regulator-always-on; 337 }; 338 339 vgen5_reg: vgen5 { 340 regulator-min-microvolt = <1800000>; 341 regulator-max-microvolt = <3300000>; 342 regulator-always-on; 343 }; 344 345 vgen6_reg: vgen6 { 346 regulator-min-microvolt = <1800000>; 347 regulator-max-microvolt = <3300000>; 348 regulator-always-on; 349 }; 350 }; 351 }; 352}; 353 354&ldb { 355 status = "okay"; 356 357 lvds0: lvds-channel@0 { 358 status = "okay"; 359 360 port@4 { 361 reg = <4>; 362 363 lvds0_out: endpoint { 364 remote-endpoint = <&panel_in_lvds0>; 365 }; 366 }; 367 }; 368}; 369 370&pwm2 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pinctrl_pwm2>; 373 status = "okay"; 374}; 375 376&ssi2 { 377 status = "okay"; 378}; 379 380&uart4 { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_uart4>; 383 uart-has-rtscts; 384 status = "okay"; 385}; 386 387&uart5 { 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_uart5>; 390 status = "okay"; 391}; 392 393&usbh1 { 394 vbus-supply = <®_usbh1_vbus>; 395 pinctrl-0 = <&pinctrl_usbh1>; 396 status = "okay"; 397}; 398 399&usdhc4 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_usdhc4>; 402 bus-width = <8>; 403 non-removable; 404 status = "okay"; 405}; 406 407&iomuxc { 408 pinctrl_audmux: audmuxgrp { 409 fsl,pins = < 410 /* I2S OUTPUT AUD6*/ 411 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 412 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 413 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 414 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 415 >; 416 }; 417 418 pinctrl_backlight: dispgrp { 419 fsl,pins = < 420 /* BLEN_OUT */ 421 MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 422 >; 423 }; 424 425 pinctrl_ecspi2: ecspi2grp { 426 fsl,pins = < 427 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 428 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 429 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 430 >; 431 }; 432 433 pinctrl_ecspi2_cs: ecspi2csgrp { 434 fsl,pins = < 435 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 436 >; 437 }; 438 439 pinctrl_ecspi2_flwp: ecspi2flwpgrp { 440 fsl,pins = < 441 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 442 >; 443 }; 444 445 pinctrl_ecspi3: ecspi3grp { 446 fsl,pins = < 447 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 448 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 449 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 450 >; 451 }; 452 453 pinctrl_ecspi3_cs: ecspi3csgrp { 454 fsl,pins = < 455 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 456 >; 457 }; 458 459 pinctrl_ecspi3_flwp: ecspi3flwpgrp { 460 fsl,pins = < 461 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 462 >; 463 }; 464 465 pinctrl_enet: enetgrp { 466 fsl,pins = < 467 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 468 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 469 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 470 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 471 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 472 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 473 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 474 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 475 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 476 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 477 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 478 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 479 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 480 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 481 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 482 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 483 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 484 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 485 >; 486 }; 487 488 pinctrl_i2c1: i2c1grp { 489 fsl,pins = < 490 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 491 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 492 >; 493 }; 494 495 pinctrl_i2c2: i2c2grp { 496 fsl,pins = < 497 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 498 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 499 >; 500 }; 501 502 pinctrl_i2c3: i2c3grp { 503 fsl,pins = < 504 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 505 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 506 >; 507 }; 508 509 pinctrl_pwm2: pwm2grp { 510 fsl,pins = < 511 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 512 >; 513 }; 514 515 pinctrl_reg_lvds: reqlvdsgrp { 516 fsl,pins = < 517 /* LVDS_PPEN_OUT */ 518 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 519 >; 520 }; 521 522 pinctrl_uart4: uart4grp { 523 fsl,pins = < 524 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 525 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 526 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 527 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 528 >; 529 }; 530 531 pinctrl_uart5: uart5grp { 532 fsl,pins = < 533 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 534 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 535 >; 536 }; 537 538 pinctrl_usbh1: usbh1grp { 539 fsl,pins = < 540 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 541 >; 542 }; 543 544 pinctrl_usbh1_vbus: usbh1_vbus_grp { 545 fsl,pins = < 546 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 547 >; 548 }; 549 550 pinctrl_usdhc4: usdhc4grp { 551 fsl,pins = < 552 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 553 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 554 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 555 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 556 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 557 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 558 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 559 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 560 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 561 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 562 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 563 >; 564 }; 565}; 566