xref: /linux/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1/*
2 * Copyright 2015 Timesys Corporation.
3 * Copyright 2015 General Electric Company
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This file is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License
12 *     version 2 as published by the Free Software Foundation.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "imx6q-ba16.dtsi"
44
45/ {
46	mclk: clock-mclk {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <22000000>;
50	};
51
52	gpio-poweroff {
53		compatible = "gpio-poweroff";
54		gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
55		status = "okay";
56	};
57
58	reg_wl18xx_vmmc: regulator-wl18xx {
59		compatible = "regulator-fixed";
60		regulator-name = "vwl1807";
61		regulator-min-microvolt = <3300000>;
62		regulator-max-microvolt = <3300000>;
63		gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
64		startup-delay-us = <70000>;
65		enable-active-high;
66	};
67
68	reg_wlan: regulator-wlan {
69		compatible = "regulator-fixed";
70		regulator-name = "3P3V_wlan";
71		regulator-min-microvolt = <3300000>;
72		regulator-max-microvolt = <3300000>;
73		regulator-always-on;
74		regulator-boot-on;
75		gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
76	};
77
78	sound {
79		compatible = "fsl,imx6q-ba16-sgtl5000",
80			     "fsl,imx-audio-sgtl5000";
81		model = "imx6q-ba16-sgtl5000";
82		ssi-controller = <&ssi1>;
83		audio-codec = <&sgtl5000>;
84		audio-routing =
85			"MIC_IN", "Mic Jack",
86			"Mic Jack", "Mic Bias",
87			"LINE_IN", "Line In Jack",
88			"Headphone Jack", "HP_OUT";
89		mux-int-port = <1>;
90		mux-ext-port = <4>;
91	};
92
93	aliases {
94		mdio-gpio0 = &mdio0;
95	};
96
97	mdio0: mdio-gpio {
98		compatible = "virtual,mdio-gpio";
99		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
100			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
101
102		#address-cells = <1>;
103		#size-cells = <0>;
104
105		switch: switch@0 {
106			compatible = "marvell,mv88e6085"; /* 88e6240*/
107			reg = <0>;
108
109			interrupt-parent = <&gpio2>;
110			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
111			interrupt-controller;
112			#interrupt-cells = <2>;
113
114			switch_ports: ports {
115				#address-cells = <1>;
116				#size-cells = <0>;
117			};
118
119			mdio {
120				#address-cells = <1>;
121				#size-cells = <0>;
122
123				switchphy0: switchphy@0 {
124					reg = <0>;
125					interrupt-parent = <&switch>;
126					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
127				};
128
129				switchphy1: switchphy@1 {
130					reg = <1>;
131					interrupt-parent = <&switch>;
132					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
133				};
134
135				switchphy2: switchphy@2 {
136					reg = <2>;
137					interrupt-parent = <&switch>;
138					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
139				};
140
141				switchphy3: switchphy@3 {
142					reg = <3>;
143					interrupt-parent = <&switch>;
144					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
145				};
146
147				switchphy4: switchphy@4 {
148					reg = <4>;
149					interrupt-parent = <&switch>;
150					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
151				};
152			};
153		};
154	};
155};
156
157&ecspi5 {
158	cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
159	pinctrl-names = "default";
160	pinctrl-0 = <&pinctrl_ecspi5>;
161	status = "okay";
162
163	m25_eeprom: flash@0 {
164		compatible = "atmel,at25";
165		spi-max-frequency = <10000000>;
166		size = <0x8000>;
167		pagesize = <64>;
168		reg = <0>;
169		address-width = <16>;
170	};
171};
172
173&i2c1 {
174	pinctrl-names = "default", "gpio";
175	pinctrl-1 = <&pinctrl_i2c1_gpio>;
176	sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177	scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178
179	pca9547: mux@70 {
180		compatible = "nxp,pca9547";
181		reg = <0x70>;
182		#address-cells = <1>;
183		#size-cells = <0>;
184
185		mux1_i2c1: i2c@0 {
186			#address-cells = <1>;
187			#size-cells = <0>;
188			reg = <0x0>;
189
190			ads7830: ads7830@48 {
191				compatible = "ti,ads7830";
192				reg = <0x48>;
193			};
194
195			mma8453: mma8453@1c {
196				compatible = "fsl,mma8453";
197				reg = <0x1c>;
198			};
199		};
200
201		mux1_i2c2: i2c@1 {
202			#address-cells = <1>;
203			#size-cells = <0>;
204			reg = <0x1>;
205
206			eeprom: eeprom@50 {
207				compatible = "atmel,24c08";
208				reg = <0x50>;
209			};
210
211			mpl3115: mpl3115@60 {
212				compatible = "fsl,mpl3115";
213				reg = <0x60>;
214			};
215		};
216
217		mux1_i2c3: i2c@2 {
218			#address-cells = <1>;
219			#size-cells = <0>;
220			reg = <0x2>;
221		};
222
223		mux1_i2c4: i2c@3 {
224			#address-cells = <1>;
225			#size-cells = <0>;
226			reg = <0x3>;
227
228			sgtl5000: codec@a {
229				compatible = "fsl,sgtl5000";
230				reg = <0x0a>;
231				clocks = <&mclk>;
232				VDDA-supply = <&reg_1p8v>;
233				VDDIO-supply = <&reg_3p3v>;
234			};
235		};
236
237		mux1_i2c5: i2c@4 {
238			#address-cells = <1>;
239			#size-cells = <0>;
240			reg = <0x4>;
241
242			pca9539: pca9539@74 {
243				compatible = "nxp,pca9539";
244				reg = <0x74>;
245				gpio-controller;
246				#gpio-cells = <2>;
247				interrupt-controller;
248				interrupt-parent = <&gpio2>;
249				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
250
251				P12-hog {
252					gpio-hog;
253					gpios = <10 0>;
254					output-low;
255					line-name = "PCA9539-P12";
256				};
257
258				P13-hog {
259					gpio-hog;
260					gpios = <11 0>;
261					output-low;
262					line-name = "PCA9539-P13";
263				};
264
265				P14-hog {
266					gpio-hog;
267					gpios = <12 0>;
268					output-low;
269					line-name = "PCA9539-P14";
270				};
271
272				P15-hog {
273					gpio-hog;
274					gpios = <13 0>;
275					output-low;
276					line-name = "PCA9539-P15";
277				};
278
279				P16-hog {
280					gpio-hog;
281					gpios = <14 0>;
282					output-low;
283					line-name = "PCA9539-P16";
284				};
285
286				P17-hog {
287					gpio-hog;
288					gpios = <15 0>;
289					output-low;
290					line-name = "PCA9539-P17";
291				};
292			};
293		};
294
295		mux1_i2c6: i2c@5 {
296			#address-cells = <1>;
297			#size-cells = <0>;
298			reg = <0x5>;
299		};
300
301		mux1_i2c7: i2c@6 {
302			#address-cells = <1>;
303			#size-cells = <0>;
304			reg = <0x6>;
305		};
306
307		mux1_i2c8: i2c@7 {
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x7>;
311		};
312	};
313};
314
315&i2c2 {
316	pinctrl-names = "default", "gpio";
317	pinctrl-1 = <&pinctrl_i2c2_gpio>;
318	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
319	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
320};
321
322&i2c3 {
323	pinctrl-names = "default", "gpio";
324	pinctrl-1 = <&pinctrl_i2c3_gpio>;
325	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
326	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
327};
328
329&iomuxc {
330	pinctrl_i2c1_gpio: i2c1gpiogrp {
331		fsl,pins = <
332			MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x1b0b0
333			MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x1b0b0
334		>;
335	};
336
337	pinctrl_i2c2_gpio: i2c2gpiogrp {
338		fsl,pins = <
339			MX6QDL_PAD_KEY_COL3__GPIO4_IO12	0x1b0b0
340			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13	0x1b0b0
341		>;
342	};
343
344	pinctrl_i2c3_gpio: i2c3gpiogrp {
345		fsl,pins = <
346			MX6QDL_PAD_GPIO_3__GPIO1_IO03	0x1b0b0
347			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x1b0b0
348		>;
349	};
350};
351
352&pmu {
353	secure-reg-access;
354};
355
356&usdhc2 {
357	status = "disabled";
358};
359
360&usdhc4 {
361	pinctrl-names = "default";
362	pinctrl-0 = <&pinctrl_usdhc4>;
363	bus-width = <4>;
364	vmmc-supply = <&reg_wl18xx_vmmc>;
365	no-1-8-v;
366	non-removable;
367	wakeup-source;
368	keep-power-in-suspend;
369	cap-power-off-card;
370	max-frequency = <25000000>;
371	#address-cells = <1>;
372	#size-cells = <0>;
373	status = "okay";
374
375	wlcore: wlcore@2 {
376		compatible = "ti,wl1837";
377		reg = <2>;
378		interrupt-parent = <&gpio2>;
379		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
380		tcxo-clock-frequency = <26000000>;
381	};
382};
383
384&pcie {
385	/* Synopsys, Inc. Device */
386	pci_root: root@0,0 {
387		compatible = "pci16c3,abcd";
388		reg = <0x00000000 0 0 0 0>;
389
390		#address-cells = <3>;
391		#size-cells = <2>;
392		#interrupt-cells = <1>;
393	};
394};
395
396&clks {
397	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
398			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
399			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
400			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
401			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
402			  <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
403	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
404				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
405				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
406				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
407				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
408				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
409};
410