1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2014 Iain Paton <ipaton0@gmail.com> 4 */ 5 6/dts-v1/; 7#include "imx6dl.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "RIoTboard i.MX6S"; 12 compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; 13 14 memory@10000000 { 15 device_type = "memory"; 16 reg = <0x10000000 0x40000000>; 17 }; 18 19 chosen { 20 stdout-path = "serial1:115200n8"; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_led>; 27 28 led0: led-user1 { 29 label = "user1"; 30 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 31 default-state = "on"; 32 linux,default-trigger = "heartbeat"; 33 }; 34 35 led1: led-user2 { 36 label = "user2"; 37 gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; 38 default-state = "off"; 39 }; 40 }; 41 42 sound { 43 compatible = "fsl,imx-audio-sgtl5000"; 44 model = "imx6-riotboard-sgtl5000"; 45 ssi-controller = <&ssi1>; 46 audio-codec = <&codec>; 47 audio-routing = 48 "MIC_IN", "Mic Jack", 49 "Mic Jack", "Mic Bias", 50 "Headphone Jack", "HP_OUT"; 51 mux-int-port = <1>; 52 mux-ext-port = <3>; 53 }; 54 55 reg_2p5v: regulator-2p5v { 56 compatible = "regulator-fixed"; 57 regulator-name = "2P5V"; 58 regulator-min-microvolt = <2500000>; 59 regulator-max-microvolt = <2500000>; 60 }; 61 62 reg_3p3v: regulator-3p3v { 63 compatible = "regulator-fixed"; 64 regulator-name = "3P3V"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 }; 68 69 reg_usb_otg_vbus: regulator-usbotgvbus { 70 compatible = "regulator-fixed"; 71 regulator-name = "usb_otg_vbus"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 75 }; 76}; 77 78&audmux { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_audmux>; 81 status = "okay"; 82}; 83 84&clks { 85 fsl,pmic-stby-poweroff; 86}; 87 88&fec { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_enet>; 91 phy-mode = "rgmii-id"; 92 phy-handle = <&rgmii_phy>; 93 /delete-property/ interrupts; 94 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 95 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 96 fsl,err006687-workaround-present; 97 status = "okay"; 98 99 mdio { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 /* Atheros AR8035 PHY */ 104 rgmii_phy: ethernet-phy@4 { 105 reg = <4>; 106 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 107 reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; 108 reset-assert-us = <10000>; 109 reset-deassert-us = <1000>; 110 qca,smarteee-tw-us-1g = <24>; 111 qca,clk-out-frequency = <125000000>; 112 }; 113 }; 114}; 115 116&gpio1 { 117 gpio-line-names = 118 "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", 119 "I2C3_SDA", "I2C4_SCL", 120 "I2C4_SDA", "", "", "", "", "", "", "", 121 "", "PWM3", "", "", "", "", "", "", 122 "", "", "", "", "", "", "", ""; 123}; 124 125&gpio3 { 126 gpio-line-names = 127 "", "", "", "", "", "", "", "", 128 "", "", "", "", "", "", "", "", 129 "", "", "", "", "", "", "USB_OTG_VBUS", "", 130 "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; 131}; 132 133&gpio4 { 134 gpio-line-names = 135 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", 136 "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", 137 "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", 138 "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", 139 "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", 140 "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; 141}; 142 143&gpio5 { 144 gpio-line-names = 145 "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", 146 "GPIO5_07", 147 "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", 148 "CSPI2_CS0", "CSPI2_CLK", "", "", 149 "", "", "", "", "", "", "", "", 150 "", "", "", "", "", "", "", ""; 151}; 152 153&gpio7 { 154 gpio-line-names = 155 "SD3_CD", "SD3_WP", "", "", "", "", "", "", 156 "", "", "", "", "", "", "", "", 157 "", "", "", "", "", "", "", "", 158 "", "", "", "", "", "", "", ""; 159}; 160 161&hdmi { 162 ddc-i2c-bus = <&i2c2>; 163 status = "okay"; 164}; 165 166&i2c1 { 167 clock-frequency = <100000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c1>; 170 status = "okay"; 171 172 codec: sgtl5000@a { 173 compatible = "fsl,sgtl5000"; 174 reg = <0x0a>; 175 #sound-dai-cells = <0>; 176 clocks = <&clks IMX6QDL_CLK_CKO>; 177 VDDA-supply = <®_2p5v>; 178 VDDIO-supply = <®_3p3v>; 179 }; 180 181 pmic: pmic@8 { 182 compatible = "fsl,pfuze100"; 183 reg = <0x08>; 184 interrupt-parent = <&gpio5>; 185 interrupts = <16 8>; 186 fsl,pmic-stby-poweroff; 187 188 regulators { 189 reg_vddcore: sw1ab { /* VDDARM_IN */ 190 regulator-min-microvolt = <300000>; 191 regulator-max-microvolt = <1875000>; 192 regulator-always-on; 193 }; 194 195 reg_vddsoc: sw1c { /* VDDSOC_IN */ 196 regulator-min-microvolt = <300000>; 197 regulator-max-microvolt = <1875000>; 198 regulator-always-on; 199 }; 200 201 reg_gen_3v3: sw2 { /* VDDHIGH_IN */ 202 regulator-min-microvolt = <800000>; 203 regulator-max-microvolt = <3300000>; 204 regulator-always-on; 205 }; 206 207 reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ 208 regulator-min-microvolt = <400000>; 209 regulator-max-microvolt = <1975000>; 210 regulator-always-on; 211 }; 212 213 reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ 214 regulator-min-microvolt = <400000>; 215 regulator-max-microvolt = <1975000>; 216 regulator-always-on; 217 }; 218 219 reg_ddr_vtt: sw4 { /* MIPI conn */ 220 regulator-min-microvolt = <400000>; 221 regulator-max-microvolt = <1975000>; 222 regulator-always-on; 223 }; 224 225 reg_5v_600mA: swbst { /* not used */ 226 regulator-min-microvolt = <5000000>; 227 regulator-max-microvolt = <5150000>; 228 }; 229 230 reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ 231 regulator-min-microvolt = <1500000>; 232 regulator-max-microvolt = <3000000>; 233 regulator-always-on; 234 }; 235 236 vref_reg: vrefddr { /* VREF_DDR */ 237 regulator-boot-on; 238 regulator-always-on; 239 }; 240 241 reg_vgen1_1v5: vgen1 { /* not used */ 242 regulator-min-microvolt = <800000>; 243 regulator-max-microvolt = <1550000>; 244 }; 245 246 reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ 247 regulator-min-microvolt = <800000>; 248 regulator-max-microvolt = <1550000>; 249 regulator-always-on; 250 }; 251 252 reg_vgen3_2v8: vgen3 { /* not used */ 253 regulator-min-microvolt = <1800000>; 254 regulator-max-microvolt = <3300000>; 255 }; 256 reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <3300000>; 259 regulator-always-on; 260 }; 261 262 reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ 263 regulator-min-microvolt = <1800000>; 264 regulator-max-microvolt = <3300000>; 265 regulator-always-on; 266 }; 267 268 reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ 269 regulator-min-microvolt = <1800000>; 270 regulator-max-microvolt = <3300000>; 271 regulator-always-on; 272 }; 273 }; 274 }; 275}; 276 277&i2c2 { 278 clock-frequency = <100000>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_i2c2>; 281 status = "okay"; 282}; 283 284&i2c4 { 285 clock-frequency = <100000>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_i2c4>; 288 clocks = <&clks 116>; 289 status = "okay"; 290}; 291 292&pwm1 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_pwm1>; 295 status = "okay"; 296}; 297 298&pwm2 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_pwm2>; 301 status = "okay"; 302}; 303 304&pwm3 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_pwm3>; 307 status = "okay"; 308}; 309 310&pwm4 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_pwm4>; 313 status = "okay"; 314}; 315 316&ssi1 { 317 status = "okay"; 318}; 319 320&uart1 { 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_uart1>; 323 status = "okay"; 324}; 325 326&uart2 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_uart2>; 329 status = "okay"; 330}; 331 332&uart3 { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_uart3>; 335 status = "okay"; 336}; 337 338&uart4 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_uart4>; 341 status = "okay"; 342}; 343 344&uart5 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_uart5>; 347 status = "okay"; 348}; 349 350&usbh1 { 351 dr_mode = "host"; 352 disable-over-current; 353 status = "okay"; 354}; 355 356&usbotg { 357 vbus-supply = <®_usb_otg_vbus>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_usbotg>; 360 disable-over-current; 361 dr_mode = "otg"; 362 status = "okay"; 363}; 364 365&usdhc2 { 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_usdhc2>; 368 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 369 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 370 vmmc-supply = <®_3p3v>; 371 status = "okay"; 372}; 373 374&usdhc3 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_usdhc3>; 377 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 378 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 379 vmmc-supply = <®_3p3v>; 380 status = "okay"; 381}; 382 383&usdhc4 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_usdhc4>; 386 vmmc-supply = <®_3p3v>; 387 non-removable; 388 status = "okay"; 389}; 390 391&iomuxc { 392 pinctrl-names = "default"; 393 394 pinctrl_audmux: audmuxgrp { 395 fsl,pins = < 396 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 397 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 398 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 399 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 400 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 401 >; 402 }; 403 404 pinctrl_ecspi1: ecspi1grp { 405 fsl,pins = < 406 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 407 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 408 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 409 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ 410 >; 411 }; 412 413 pinctrl_ecspi2: ecspi2grp { 414 fsl,pins = < 415 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ 416 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 417 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 418 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ 419 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 420 >; 421 }; 422 423 pinctrl_ecspi3: ecspi3grp { 424 fsl,pins = < 425 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 426 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 427 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 428 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ 429 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ 430 >; 431 }; 432 433 pinctrl_enet: enetgrp { 434 fsl,pins = < 435 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 436 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 437 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 438 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 439 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 440 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 441 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 442 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 443 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 444 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ 445 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ 446 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ 447 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ 448 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ 449 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 450 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ 451 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 452 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ 453 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 454 >; 455 }; 456 457 pinctrl_i2c1: i2c1grp { 458 fsl,pins = < 459 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 460 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 461 >; 462 }; 463 464 pinctrl_i2c2: i2c2grp { 465 fsl,pins = < 466 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 467 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 468 >; 469 }; 470 471 pinctrl_i2c3: i2c3grp { 472 fsl,pins = < 473 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 474 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 475 >; 476 }; 477 478 pinctrl_i2c4: i2c4grp { 479 fsl,pins = < 480 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 481 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 482 >; 483 }; 484 485 pinctrl_led: ledgrp { 486 fsl,pins = < 487 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ 488 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ 489 >; 490 }; 491 492 pinctrl_pwm1: pwm1grp { 493 fsl,pins = < 494 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 495 >; 496 }; 497 498 pinctrl_pwm2: pwm2grp { 499 fsl,pins = < 500 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 501 >; 502 }; 503 504 pinctrl_pwm3: pwm3grp { 505 fsl,pins = < 506 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 507 >; 508 }; 509 510 pinctrl_pwm4: pwm4grp { 511 fsl,pins = < 512 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 513 >; 514 }; 515 516 pinctrl_uart1: uart1grp { 517 fsl,pins = < 518 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 519 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 520 >; 521 }; 522 523 pinctrl_uart2: uart2grp { 524 fsl,pins = < 525 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 526 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 527 >; 528 }; 529 530 pinctrl_uart3: uart3grp { 531 fsl,pins = < 532 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 533 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 534 >; 535 }; 536 537 pinctrl_uart4: uart4grp { 538 fsl,pins = < 539 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 540 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 541 >; 542 }; 543 544 pinctrl_uart5: uart5grp { 545 fsl,pins = < 546 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 547 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 548 >; 549 }; 550 551 pinctrl_usbotg: usbotggrp { 552 fsl,pins = < 553 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 554 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 555 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 556 >; 557 }; 558 559 pinctrl_usdhc2: usdhc2grp { 560 fsl,pins = < 561 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 562 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 563 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 564 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 565 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 566 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 567 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ 568 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ 569 >; 570 }; 571 572 pinctrl_usdhc3: usdhc3grp { 573 fsl,pins = < 574 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 575 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 576 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 577 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 578 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 579 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 580 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ 581 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ 582 >; 583 }; 584 585 pinctrl_usdhc4: usdhc4grp { 586 fsl,pins = < 587 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 588 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 589 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 590 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 591 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 592 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 593 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ 594 >; 595 }; 596}; 597