1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * support for the imx6 based aristainetos2 board 4 * 5 * Copyright (C) 2015 Heiko Schocher <hs@denx.de> 6 */ 7/dts-v1/; 8#include "imx6dl.dtsi" 9#include "imx6qdl-aristainetos2.dtsi" 10 11/ { 12 model = "aristainetos2 i.MX6 Dual Lite Board 4"; 13 compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; 14 15 memory@10000000 { 16 device_type = "memory"; 17 reg = <0x10000000 0x40000000>; 18 }; 19 20 display0: disp0 { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 compatible = "fsl,imx-parallel-display"; 24 interface-pix-fmt = "rgb24"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_ipu_disp>; 27 28 port@0 { 29 reg = <0>; 30 display0_in: endpoint { 31 remote-endpoint = <&ipu1_di0_disp0>; 32 }; 33 }; 34 35 port@1 { 36 reg = <1>; 37 display_out: endpoint { 38 remote-endpoint = <&panel_in>; 39 }; 40 }; 41 }; 42}; 43 44&ecspi1 { 45 lcd_panel: display@0 { 46 compatible = "lg,lg4573"; 47 spi-max-frequency = <10000000>; 48 reg = <0>; 49 50 display-timings { 51 native-mode = <&timing0>; 52 timing0: timing-480x800p57 { 53 clock-frequency = <27000027>; 54 hactive = <480>; 55 vactive = <800>; 56 hfront-porch = <10>; 57 hback-porch = <59>; 58 hsync-len = <10>; 59 vback-porch = <15>; 60 vfront-porch = <15>; 61 vsync-len = <15>; 62 hsync-active = <1>; 63 vsync-active = <1>; 64 }; 65 }; 66 67 port { 68 panel_in: endpoint { 69 remote-endpoint = <&display_out>; 70 }; 71 }; 72 }; 73}; 74 75&i2c3 { 76 touch: touch@4b { 77 compatible = "atmel,maxtouch"; 78 reg = <0x4b>; 79 interrupt-parent = <&gpio2>; 80 interrupts = <9 8>; 81 }; 82}; 83 84&ipu1_di0_disp0 { 85 remote-endpoint = <&display0_in>; 86}; 87 88&iomuxc { 89 pinctrl_ipu_disp: ipudisp1grp { 90 fsl,pins = < 91 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 92 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 93 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 94 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 95 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 96 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 97 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 98 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 99 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 100 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 101 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 102 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 103 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 104 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 105 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 106 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 107 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 108 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 109 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 110 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 111 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 112 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 113 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 114 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 115 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 116 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 117 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 118 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 119 >; 120 }; 121}; 122