1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2012 Armadeus Systems - <support@armadeus.com> 4*724ba675SRob Herring * Copyright 2012 Laurent Cans <laurent.cans@gmail.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring * Based on mx51-babbage.dts 7*724ba675SRob Herring * Copyright 2011 Freescale Semiconductor, Inc. 8*724ba675SRob Herring * Copyright 2011 Linaro Ltd. 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring/dts-v1/; 12*724ba675SRob Herring#include "imx51.dtsi" 13*724ba675SRob Herring 14*724ba675SRob Herring/ { 15*724ba675SRob Herring model = "Armadeus Systems APF51 module"; 16*724ba675SRob Herring compatible = "armadeus,imx51-apf51", "fsl,imx51"; 17*724ba675SRob Herring 18*724ba675SRob Herring memory@90000000 { 19*724ba675SRob Herring device_type = "memory"; 20*724ba675SRob Herring reg = <0x90000000 0x20000000>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring clocks { 24*724ba675SRob Herring osc { 25*724ba675SRob Herring clock-frequency = <33554432>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring }; 28*724ba675SRob Herring}; 29*724ba675SRob Herring 30*724ba675SRob Herring&fec { 31*724ba675SRob Herring pinctrl-names = "default"; 32*724ba675SRob Herring pinctrl-0 = <&pinctrl_fec>; 33*724ba675SRob Herring phy-mode = "mii"; 34*724ba675SRob Herring phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 35*724ba675SRob Herring phy-reset-duration = <1>; 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring}; 38*724ba675SRob Herring 39*724ba675SRob Herring&iomuxc { 40*724ba675SRob Herring imx51-apf51 { 41*724ba675SRob Herring pinctrl_fec: fecgrp { 42*724ba675SRob Herring fsl,pins = < 43*724ba675SRob Herring MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 44*724ba675SRob Herring MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 45*724ba675SRob Herring MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 46*724ba675SRob Herring MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 47*724ba675SRob Herring MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 48*724ba675SRob Herring MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 49*724ba675SRob Herring MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 50*724ba675SRob Herring MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 51*724ba675SRob Herring MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 52*724ba675SRob Herring MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 53*724ba675SRob Herring MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 54*724ba675SRob Herring MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 55*724ba675SRob Herring MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 56*724ba675SRob Herring MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 57*724ba675SRob Herring MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 58*724ba675SRob Herring MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 59*724ba675SRob Herring MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 60*724ba675SRob Herring MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 61*724ba675SRob Herring >; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring pinctrl_uart3: uart3grp { 65*724ba675SRob Herring fsl,pins = < 66*724ba675SRob Herring MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 67*724ba675SRob Herring MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 68*724ba675SRob Herring >; 69*724ba675SRob Herring }; 70*724ba675SRob Herring }; 71*724ba675SRob Herring}; 72*724ba675SRob Herring 73*724ba675SRob Herring&nfc { 74*724ba675SRob Herring nand-bus-width = <8>; 75*724ba675SRob Herring nand-ecc-mode = "hw"; 76*724ba675SRob Herring nand-on-flash-bbt; 77*724ba675SRob Herring status = "okay"; 78*724ba675SRob Herring}; 79*724ba675SRob Herring 80*724ba675SRob Herring&uart3 { 81*724ba675SRob Herring pinctrl-names = "default"; 82*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart3>; 83*724ba675SRob Herring status = "okay"; 84*724ba675SRob Herring}; 85