1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-or-later 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include "imx35.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Eukrea CPUIMX35"; 10*724ba675SRob Herring compatible = "eukrea,cpuimx35", "fsl,imx35"; 11*724ba675SRob Herring 12*724ba675SRob Herring memory@80000000 { 13*724ba675SRob Herring device_type = "memory"; 14*724ba675SRob Herring reg = <0x80000000 0x8000000>; /* 128M */ 15*724ba675SRob Herring }; 16*724ba675SRob Herring}; 17*724ba675SRob Herring 18*724ba675SRob Herring&fec { 19*724ba675SRob Herring pinctrl-names = "default"; 20*724ba675SRob Herring pinctrl-0 = <&pinctrl_fec>; 21*724ba675SRob Herring status = "okay"; 22*724ba675SRob Herring}; 23*724ba675SRob Herring 24*724ba675SRob Herring&i2c1 { 25*724ba675SRob Herring pinctrl-names = "default"; 26*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c1>; 27*724ba675SRob Herring status = "okay"; 28*724ba675SRob Herring 29*724ba675SRob Herring pcf8563@51 { 30*724ba675SRob Herring compatible = "nxp,pcf8563"; 31*724ba675SRob Herring reg = <0x51>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring 34*724ba675SRob Herring tsc2007: tsc2007@48 { 35*724ba675SRob Herring compatible = "ti,tsc2007"; 36*724ba675SRob Herring gpios = <&gpio3 2 0>; 37*724ba675SRob Herring interrupt-parent = <&gpio3>; 38*724ba675SRob Herring interrupts = <0x2 0x8>; 39*724ba675SRob Herring pinctrl-names = "default"; 40*724ba675SRob Herring pinctrl-0 = <&pinctrl_tsc2007_1>; 41*724ba675SRob Herring reg = <0x48>; 42*724ba675SRob Herring ti,x-plate-ohms = <180>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&iomuxc { 47*724ba675SRob Herring imx35-eukrea { 48*724ba675SRob Herring pinctrl_fec: fecgrp { 49*724ba675SRob Herring fsl,pins = < 50*724ba675SRob Herring MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 51*724ba675SRob Herring MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 52*724ba675SRob Herring MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 53*724ba675SRob Herring MX35_PAD_FEC_COL__FEC_COL 0x80000000 54*724ba675SRob Herring MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 55*724ba675SRob Herring MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 56*724ba675SRob Herring MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 57*724ba675SRob Herring MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 58*724ba675SRob Herring MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 59*724ba675SRob Herring MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 60*724ba675SRob Herring MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 61*724ba675SRob Herring MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 62*724ba675SRob Herring MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 63*724ba675SRob Herring MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 64*724ba675SRob Herring MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 65*724ba675SRob Herring MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 66*724ba675SRob Herring MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 67*724ba675SRob Herring MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 68*724ba675SRob Herring >; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring pinctrl_i2c1: i2c1grp { 72*724ba675SRob Herring fsl,pins = < 73*724ba675SRob Herring MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 74*724ba675SRob Herring MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 75*724ba675SRob Herring >; 76*724ba675SRob Herring }; 77*724ba675SRob Herring 78*724ba675SRob Herring pinctrl_tsc2007_1: tsc2007grp-1 { 79*724ba675SRob Herring fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring }; 82*724ba675SRob Herring}; 83*724ba675SRob Herring 84*724ba675SRob Herring&nfc { 85*724ba675SRob Herring nand-bus-width = <8>; 86*724ba675SRob Herring nand-ecc-mode = "hw"; 87*724ba675SRob Herring nand-on-flash-bbt; 88*724ba675SRob Herring status = "okay"; 89*724ba675SRob Herring}; 90