1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> 4// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 /* 10 * The decompressor and also some bootloaders rely on a 11 * pre-existing /chosen node to be available to insert the 12 * command line and merge other ATAGS info. 13 */ 14 chosen {}; 15 16 aliases { 17 gpio0 = &gpio1; 18 gpio1 = &gpio2; 19 gpio2 = &gpio3; 20 i2c0 = &i2c1; 21 i2c1 = &i2c2; 22 i2c2 = &i2c3; 23 serial0 = &uart1; 24 serial1 = &uart2; 25 serial2 = &uart3; 26 serial3 = &uart4; 27 serial4 = &uart5; 28 spi0 = &spi1; 29 spi1 = &spi2; 30 spi2 = &spi3; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu@0 { 38 compatible = "arm,arm1136jf-s"; 39 device_type = "cpu"; 40 reg = <0>; 41 }; 42 }; 43 44 avic: interrupt-controller@68000000 { 45 compatible = "fsl,imx31-avic", "fsl,avic"; 46 interrupt-controller; 47 #interrupt-cells = <1>; 48 reg = <0x68000000 0x100000>; 49 }; 50 51 soc: soc { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 interrupt-parent = <&avic>; 56 ranges; 57 58 iram: sram@1fffc000 { 59 compatible = "mmio-sram"; 60 reg = <0x1fffc000 0x4000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges = <0 0x1fffc000 0x4000>; 64 }; 65 66 aips1: bus@43f00000 { /* AIPS1 */ 67 compatible = "fsl,aips-bus", "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 reg = <0x43f00000 0x100000>; 71 ranges; 72 73 i2c1: i2c@43f80000 { 74 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; 75 reg = <0x43f80000 0x4000>; 76 interrupts = <10>; 77 clocks = <&clks 33>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 status = "disabled"; 81 }; 82 83 i2c3: i2c@43f84000 { 84 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; 85 reg = <0x43f84000 0x4000>; 86 interrupts = <3>; 87 clocks = <&clks 35>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 status = "disabled"; 91 }; 92 93 ata: ata@43f8c000 { 94 compatible = "fsl,imx31-pata", "fsl,imx27-pata"; 95 reg = <0x43f8c000 0x4000>; 96 interrupts = <15>; 97 clocks = <&clks 26>; 98 status = "disabled"; 99 }; 100 101 uart1: serial@43f90000 { 102 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 103 reg = <0x43f90000 0x4000>; 104 interrupts = <45>; 105 clocks = <&clks 10>, <&clks 30>; 106 clock-names = "ipg", "per"; 107 status = "disabled"; 108 }; 109 110 uart2: serial@43f94000 { 111 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 112 reg = <0x43f94000 0x4000>; 113 interrupts = <32>; 114 clocks = <&clks 10>, <&clks 31>; 115 clock-names = "ipg", "per"; 116 status = "disabled"; 117 }; 118 119 i2c2: i2c@43f98000 { 120 compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; 121 reg = <0x43f98000 0x4000>; 122 interrupts = <4>; 123 clocks = <&clks 34>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 }; 128 129 spi1: spi@43fa4000 { 130 compatible = "fsl,imx31-cspi"; 131 reg = <0x43fa4000 0x4000>; 132 interrupts = <14>; 133 clocks = <&clks 10>, <&clks 53>; 134 clock-names = "ipg", "per"; 135 dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; 136 dma-names = "rx", "tx"; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 status = "disabled"; 140 }; 141 142 kpp: kpp@43fa8000 { 143 compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; 144 reg = <0x43fa8000 0x4000>; 145 interrupts = <24>; 146 clocks = <&clks 46>; 147 status = "disabled"; 148 }; 149 150 uart4: serial@43fb0000 { 151 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 152 reg = <0x43fb0000 0x4000>; 153 clocks = <&clks 10>, <&clks 49>; 154 clock-names = "ipg", "per"; 155 interrupts = <46>; 156 status = "disabled"; 157 }; 158 159 uart5: serial@43fb4000 { 160 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 161 reg = <0x43fb4000 0x4000>; 162 interrupts = <47>; 163 clocks = <&clks 10>, <&clks 50>; 164 clock-names = "ipg", "per"; 165 status = "disabled"; 166 }; 167 }; 168 169 spba-bus@50000000 { 170 compatible = "fsl,spba-bus", "simple-bus"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 reg = <0x50000000 0x100000>; 174 ranges; 175 176 sdhci1: mmc@50004000 { 177 compatible = "fsl,imx31-mmc"; 178 reg = <0x50004000 0x4000>; 179 interrupts = <9>; 180 clocks = <&clks 10>, <&clks 20>; 181 clock-names = "ipg", "per"; 182 dmas = <&sdma 20 3 0>; 183 dma-names = "rx-tx"; 184 status = "disabled"; 185 }; 186 187 sdhci2: mmc@50008000 { 188 compatible = "fsl,imx31-mmc"; 189 reg = <0x50008000 0x4000>; 190 interrupts = <8>; 191 clocks = <&clks 10>, <&clks 21>; 192 clock-names = "ipg", "per"; 193 dmas = <&sdma 21 3 0>; 194 dma-names = "rx-tx"; 195 status = "disabled"; 196 }; 197 198 uart3: serial@5000c000 { 199 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 200 reg = <0x5000c000 0x4000>; 201 interrupts = <18>; 202 clocks = <&clks 10>, <&clks 48>; 203 clock-names = "ipg", "per"; 204 status = "disabled"; 205 }; 206 207 spi2: spi@50010000 { 208 compatible = "fsl,imx31-cspi"; 209 reg = <0x50010000 0x4000>; 210 interrupts = <13>; 211 clocks = <&clks 10>, <&clks 54>; 212 clock-names = "ipg", "per"; 213 dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; 214 dma-names = "rx", "tx"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 status = "disabled"; 218 }; 219 220 iim: efuse@5001c000 { 221 compatible = "fsl,imx31-iim", "fsl,imx27-iim"; 222 reg = <0x5001c000 0x1000>; 223 interrupts = <19>; 224 clocks = <&clks 25>; 225 }; 226 }; 227 228 bus@53f00000 { /* AIPS2 */ 229 compatible = "fsl,aips-bus", "simple-bus"; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 reg = <0x53f00000 0x100000>; 233 ranges; 234 235 clks: ccm@53f80000 { 236 compatible = "fsl,imx31-ccm"; 237 reg = <0x53f80000 0x4000>; 238 interrupts = <31>, <53>; 239 #clock-cells = <1>; 240 }; 241 242 spi3: spi@53f84000 { 243 compatible = "fsl,imx31-cspi"; 244 reg = <0x53f84000 0x4000>; 245 interrupts = <17>; 246 clocks = <&clks 10>, <&clks 28>; 247 clock-names = "ipg", "per"; 248 dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; 249 dma-names = "rx", "tx"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 status = "disabled"; 253 }; 254 255 gpt: timer@53f90000 { 256 compatible = "fsl,imx31-gpt"; 257 reg = <0x53f90000 0x4000>; 258 interrupts = <29>; 259 clocks = <&clks 10>, <&clks 22>; 260 clock-names = "ipg", "per"; 261 }; 262 263 gpio3: gpio@53fa4000 { 264 compatible = "fsl,imx31-gpio"; 265 reg = <0x53fa4000 0x4000>; 266 interrupts = <56>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 interrupt-controller; 270 #interrupt-cells = <2>; 271 }; 272 273 rng@53fb0000 { 274 compatible = "fsl,imx31-rnga"; 275 reg = <0x53fb0000 0x4000>; 276 interrupts = <22>; 277 clocks = <&clks 29>; 278 }; 279 280 gpio1: gpio@53fcc000 { 281 compatible = "fsl,imx31-gpio"; 282 reg = <0x53fcc000 0x4000>; 283 interrupts = <52>; 284 gpio-controller; 285 #gpio-cells = <2>; 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 }; 289 290 gpio2: gpio@53fd0000 { 291 compatible = "fsl,imx31-gpio"; 292 reg = <0x53fd0000 0x4000>; 293 interrupts = <51>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 }; 299 300 sdma: dma-controller@53fd4000 { 301 compatible = "fsl,imx31-sdma"; 302 reg = <0x53fd4000 0x4000>; 303 interrupts = <34>; 304 clocks = <&clks 10>, <&clks 27>; 305 clock-names = "ipg", "ahb"; 306 #dma-cells = <3>; 307 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; 308 }; 309 310 rtc: rtc@53fd8000 { 311 compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; 312 reg = <0x53fd8000 0x4000>; 313 interrupts = <25>; 314 clocks = <&clks 2>, <&clks 40>; 315 clock-names = "ref", "ipg"; 316 }; 317 318 wdog: watchdog@53fdc000 { 319 compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; 320 reg = <0x53fdc000 0x4000>; 321 clocks = <&clks 41>; 322 interrupts = <55>; 323 }; 324 325 pwm: pwm@53fe0000 { 326 compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; 327 reg = <0x53fe0000 0x4000>; 328 interrupts = <26>; 329 clocks = <&clks 10>, <&clks 42>; 330 clock-names = "ipg", "per"; 331 #pwm-cells = <3>; 332 status = "disabled"; 333 }; 334 }; 335 336 emi@b8000000 { /* External Memory Interface */ 337 compatible = "simple-bus"; 338 reg = <0xb8000000 0x5000>; 339 ranges; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 343 nfc: nand@b8000000 { 344 compatible = "fsl,imx31-nand", "fsl,imx27-nand"; 345 reg = <0xb8000000 0x1000>; 346 interrupts = <33>; 347 clocks = <&clks 9>; 348 dmas = <&sdma 30 17 0>; 349 dma-names = "rx-tx"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 status = "disabled"; 353 }; 354 355 weim: memory-controller@b8002000 { 356 compatible = "fsl,imx31-weim", "fsl,imx27-weim"; 357 reg = <0xb8002000 0x1000>; 358 clocks = <&clks 56>; 359 #address-cells = <2>; 360 #size-cells = <1>; 361 ranges = <0 0 0xa0000000 0x08000000 362 1 0 0xa8000000 0x08000000 363 2 0 0xb0000000 0x02000000 364 3 0 0xb2000000 0x02000000 365 4 0 0xb4000000 0x02000000 366 5 0 0xb6000000 0x02000000>; 367 status = "disabled"; 368 }; 369 }; 370 }; 371}; 372