1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra30-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra30-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8#include <dt-bindings/thermal/thermal.h> 9 10#include "tegra30-peripherals-opp.dtsi" 11 12/ { 13 compatible = "nvidia,tegra30"; 14 interrupt-parent = <&lic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x80000000 0x0>; 21 }; 22 23 pcie@3000 { 24 compatible = "nvidia,tegra30-pcie"; 25 device_type = "pci"; 26 reg = <0x00003000 0x00000800>, /* PADS registers */ 27 <0x00003800 0x00000200>, /* AFI registers */ 28 <0x10000000 0x10000000>; /* configuration space */ 29 reg-names = "pads", "afi", "cs"; 30 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 31 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 32 interrupt-names = "intr", "msi"; 33 34 #interrupt-cells = <1>; 35 interrupt-map-mask = <0 0 0 0>; 36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 37 38 bus-range = <0x00 0xff>; 39 #address-cells = <3>; 40 #size-cells = <2>; 41 42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ 43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ 44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ 45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ 46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ 47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 48 49 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 50 <&tegra_car TEGRA30_CLK_AFI>, 51 <&tegra_car TEGRA30_CLK_PLL_E>, 52 <&tegra_car TEGRA30_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 power-domains = <&pd_core>; 59 operating-points-v2 = <&pcie_dvfs_opp_table>; 60 status = "disabled"; 61 62 pci@1,0 { 63 device_type = "pci"; 64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 65 reg = <0x000800 0 0 0 0>; 66 bus-range = <0x00 0xff>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <2>; 74 }; 75 76 pci@2,0 { 77 device_type = "pci"; 78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 79 reg = <0x001000 0 0 0 0>; 80 bus-range = <0x00 0xff>; 81 status = "disabled"; 82 83 #address-cells = <3>; 84 #size-cells = <2>; 85 ranges; 86 87 nvidia,num-lanes = <2>; 88 }; 89 90 pci@3,0 { 91 device_type = "pci"; 92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 93 reg = <0x001800 0 0 0 0>; 94 bus-range = <0x00 0xff>; 95 status = "disabled"; 96 97 #address-cells = <3>; 98 #size-cells = <2>; 99 ranges; 100 101 nvidia,num-lanes = <2>; 102 }; 103 }; 104 105 sram@40000000 { 106 compatible = "mmio-sram"; 107 reg = <0x40000000 0x40000>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0x40000000 0x40000>; 111 112 vde_pool: sram@400 { 113 reg = <0x400 0x3fc00>; 114 pool; 115 }; 116 }; 117 118 host1x@50000000 { 119 compatible = "nvidia,tegra30-host1x"; 120 reg = <0x50000000 0x00024000>; 121 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 122 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 123 interrupt-names = "syncpt", "host1x"; 124 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 125 clock-names = "host1x"; 126 resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; 127 reset-names = "host1x", "mc"; 128 iommus = <&mc TEGRA_SWGROUP_HC>; 129 power-domains = <&pd_heg>; 130 operating-points-v2 = <&host1x_dvfs_opp_table>; 131 132 #address-cells = <1>; 133 #size-cells = <1>; 134 135 ranges = <0x54000000 0x54000000 0x04000000>; 136 137 mpe@54040000 { 138 compatible = "nvidia,tegra30-mpe"; 139 reg = <0x54040000 0x00040000>; 140 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&tegra_car TEGRA30_CLK_MPE>; 142 resets = <&tegra_car 60>; 143 reset-names = "mpe"; 144 power-domains = <&pd_mpe>; 145 operating-points-v2 = <&mpe_dvfs_opp_table>; 146 147 iommus = <&mc TEGRA_SWGROUP_MPE>; 148 149 status = "disabled"; 150 }; 151 152 vi@54080000 { 153 compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi"; 154 reg = <0x54080000 0x00000800>; 155 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&tegra_car TEGRA30_CLK_VI>; 157 resets = <&tegra_car 20>; 158 reset-names = "vi"; 159 power-domains = <&pd_venc>; 160 operating-points-v2 = <&vi_dvfs_opp_table>; 161 162 iommus = <&mc TEGRA_SWGROUP_VI>; 163 164 status = "disabled"; 165 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 ranges = <0x0 0x54080000 0x4000>; 170 171 csi: csi@800 { 172 compatible = "nvidia,tegra30-csi"; 173 reg = <0x800 0x200>; 174 clocks = <&tegra_car TEGRA30_CLK_CSI>, 175 <&tegra_car TEGRA30_CLK_CSIA_PAD>, 176 <&tegra_car TEGRA30_CLK_CSIB_PAD>; 177 clock-names = "csi", "csia-pad", "csib-pad"; 178 power-domains = <&pd_venc>; 179 #nvidia,mipi-calibrate-cells = <1>; 180 status = "disabled"; 181 182 #address-cells = <1>; 183 #size-cells = <0>; 184 }; 185 }; 186 187 epp@540c0000 { 188 compatible = "nvidia,tegra30-epp"; 189 reg = <0x540c0000 0x00040000>; 190 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&tegra_car TEGRA30_CLK_EPP>; 192 resets = <&tegra_car 19>; 193 reset-names = "epp"; 194 power-domains = <&pd_heg>; 195 operating-points-v2 = <&epp_dvfs_opp_table>; 196 197 iommus = <&mc TEGRA_SWGROUP_EPP>; 198 199 status = "disabled"; 200 }; 201 202 isp@54100000 { 203 compatible = "nvidia,tegra30-isp"; 204 reg = <0x54100000 0x00040000>; 205 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&tegra_car TEGRA30_CLK_ISP>; 207 resets = <&tegra_car 23>; 208 reset-names = "isp"; 209 power-domains = <&pd_venc>; 210 211 iommus = <&mc TEGRA_SWGROUP_ISP>; 212 213 status = "disabled"; 214 }; 215 216 gr2d@54140000 { 217 compatible = "nvidia,tegra30-gr2d"; 218 reg = <0x54140000 0x00040000>; 219 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 221 resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; 222 reset-names = "2d", "mc"; 223 power-domains = <&pd_heg>; 224 operating-points-v2 = <&gr2d_dvfs_opp_table>; 225 226 iommus = <&mc TEGRA_SWGROUP_G2>; 227 }; 228 229 gr3d@54180000 { 230 compatible = "nvidia,tegra30-gr3d"; 231 reg = <0x54180000 0x00040000>; 232 clocks = <&tegra_car TEGRA30_CLK_GR3D>, 233 <&tegra_car TEGRA30_CLK_GR3D2>; 234 clock-names = "3d", "3d2"; 235 resets = <&tegra_car 24>, 236 <&tegra_car 98>, 237 <&mc TEGRA30_MC_RESET_3D>, 238 <&mc TEGRA30_MC_RESET_3D2>; 239 reset-names = "3d", "3d2", "mc", "mc2"; 240 power-domains = <&pd_3d0>, <&pd_3d1>; 241 power-domain-names = "3d0", "3d1"; 242 operating-points-v2 = <&gr3d_dvfs_opp_table>; 243 244 iommus = <&mc TEGRA_SWGROUP_NV>, 245 <&mc TEGRA_SWGROUP_NV2>; 246 }; 247 248 dc@54200000 { 249 compatible = "nvidia,tegra30-dc"; 250 reg = <0x54200000 0x00040000>; 251 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 253 <&tegra_car TEGRA30_CLK_PLL_P>; 254 clock-names = "dc", "parent"; 255 resets = <&tegra_car 27>; 256 reset-names = "dc"; 257 power-domains = <&pd_core>; 258 operating-points-v2 = <&disp1_dvfs_opp_table>; 259 260 iommus = <&mc TEGRA_SWGROUP_DC>; 261 262 nvidia,head = <0>; 263 264 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, 265 <&mc TEGRA30_MC_DISPLAY0B &emc>, 266 <&mc TEGRA30_MC_DISPLAY1B &emc>, 267 <&mc TEGRA30_MC_DISPLAY0C &emc>, 268 <&mc TEGRA30_MC_DISPLAYHC &emc>; 269 interconnect-names = "wina", 270 "winb", 271 "winb-vfilter", 272 "winc", 273 "cursor"; 274 275 rgb { 276 status = "disabled"; 277 }; 278 }; 279 280 dc@54240000 { 281 compatible = "nvidia,tegra30-dc"; 282 reg = <0x54240000 0x00040000>; 283 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 285 <&tegra_car TEGRA30_CLK_PLL_P>; 286 clock-names = "dc", "parent"; 287 resets = <&tegra_car 26>; 288 reset-names = "dc"; 289 power-domains = <&pd_core>; 290 operating-points-v2 = <&disp2_dvfs_opp_table>; 291 292 iommus = <&mc TEGRA_SWGROUP_DCB>; 293 294 nvidia,head = <1>; 295 296 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, 297 <&mc TEGRA30_MC_DISPLAY0BB &emc>, 298 <&mc TEGRA30_MC_DISPLAY1BB &emc>, 299 <&mc TEGRA30_MC_DISPLAY0CB &emc>, 300 <&mc TEGRA30_MC_DISPLAYHCB &emc>; 301 interconnect-names = "wina", 302 "winb", 303 "winb-vfilter", 304 "winc", 305 "cursor"; 306 307 rgb { 308 status = "disabled"; 309 }; 310 }; 311 312 hdmi@54280000 { 313 compatible = "nvidia,tegra30-hdmi"; 314 reg = <0x54280000 0x00040000>; 315 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 317 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 318 clock-names = "hdmi", "parent"; 319 resets = <&tegra_car 51>; 320 reset-names = "hdmi"; 321 power-domains = <&pd_core>; 322 operating-points-v2 = <&hdmi_dvfs_opp_table>; 323 status = "disabled"; 324 }; 325 326 tvo@542c0000 { 327 compatible = "nvidia,tegra30-tvo"; 328 reg = <0x542c0000 0x00040000>; 329 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&tegra_car TEGRA30_CLK_TVO>; 331 power-domains = <&pd_core>; 332 operating-points-v2 = <&tvo_dvfs_opp_table>; 333 status = "disabled"; 334 }; 335 336 dsi@54300000 { 337 compatible = "nvidia,tegra30-dsi"; 338 reg = <0x54300000 0x00040000>; 339 clocks = <&tegra_car TEGRA30_CLK_DSIA>, 340 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 341 clock-names = "dsi", "parent"; 342 resets = <&tegra_car 48>; 343 reset-names = "dsi"; 344 power-domains = <&pd_core>; 345 operating-points-v2 = <&dsia_dvfs_opp_table>; 346 nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */ 347 status = "disabled"; 348 349 #address-cells = <1>; 350 #size-cells = <0>; 351 }; 352 353 dsi@54400000 { 354 compatible = "nvidia,tegra30-dsi"; 355 reg = <0x54400000 0x00040000>; 356 clocks = <&tegra_car TEGRA30_CLK_DSIB>, 357 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 358 clock-names = "dsi", "parent"; 359 resets = <&tegra_car 84>; 360 reset-names = "dsi"; 361 power-domains = <&pd_core>; 362 operating-points-v2 = <&dsib_dvfs_opp_table>; 363 nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */ 364 status = "disabled"; 365 366 #address-cells = <1>; 367 #size-cells = <0>; 368 }; 369 }; 370 371 timer@50040600 { 372 compatible = "arm,cortex-a9-twd-timer"; 373 reg = <0x50040600 0x20>; 374 interrupt-parent = <&intc>; 375 interrupts = <GIC_PPI 13 376 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 377 clocks = <&tegra_car TEGRA30_CLK_TWD>; 378 }; 379 380 intc: interrupt-controller@50041000 { 381 compatible = "arm,cortex-a9-gic"; 382 reg = <0x50041000 0x1000>, 383 <0x50040100 0x0100>; 384 interrupt-controller; 385 #interrupt-cells = <3>; 386 interrupt-parent = <&intc>; 387 }; 388 389 cache-controller@50043000 { 390 compatible = "arm,pl310-cache"; 391 reg = <0x50043000 0x1000>; 392 arm,data-latency = <6 6 2>; 393 arm,tag-latency = <5 5 2>; 394 cache-unified; 395 cache-level = <2>; 396 }; 397 398 lic: interrupt-controller@60004000 { 399 compatible = "nvidia,tegra30-ictlr"; 400 reg = <0x60004000 0x100>, 401 <0x60004100 0x50>, 402 <0x60004200 0x50>, 403 <0x60004300 0x50>, 404 <0x60004400 0x50>; 405 interrupt-controller; 406 #interrupt-cells = <3>; 407 interrupt-parent = <&intc>; 408 }; 409 410 timer@60005000 { 411 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 412 reg = <0x60005000 0x400>; 413 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 420 }; 421 422 tegra_car: clock@60006000 { 423 compatible = "nvidia,tegra30-car"; 424 reg = <0x60006000 0x1000>; 425 #clock-cells = <1>; 426 #reset-cells = <1>; 427 428 pll-c { 429 compatible = "nvidia,tegra30-pllc"; 430 clocks = <&tegra_car TEGRA30_CLK_PLL_C>; 431 power-domains = <&pd_core>; 432 operating-points-v2 = <&pll_c_dvfs_opp_table>; 433 }; 434 435 pll-e { 436 compatible = "nvidia,tegra30-plle"; 437 clocks = <&tegra_car TEGRA30_CLK_PLL_E>; 438 power-domains = <&pd_core>; 439 operating-points-v2 = <&pll_e_dvfs_opp_table>; 440 }; 441 442 pll-m { 443 compatible = "nvidia,tegra30-pllm"; 444 clocks = <&tegra_car TEGRA30_CLK_PLL_M>; 445 power-domains = <&pd_core>; 446 operating-points-v2 = <&pll_m_dvfs_opp_table>; 447 }; 448 449 sclk { 450 compatible = "nvidia,tegra30-sclk"; 451 clocks = <&tegra_car TEGRA30_CLK_SCLK>; 452 power-domains = <&pd_core>; 453 operating-points-v2 = <&sclk_dvfs_opp_table>; 454 }; 455 }; 456 457 flow-controller@60007000 { 458 compatible = "nvidia,tegra30-flowctrl"; 459 reg = <0x60007000 0x1000>; 460 }; 461 462 apbdma: dma-controller@6000a000 { 463 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 464 reg = <0x6000a000 0x1400>; 465 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 498 resets = <&tegra_car 34>; 499 reset-names = "dma"; 500 #dma-cells = <1>; 501 }; 502 503 ahb: ahb@6000c000 { 504 compatible = "nvidia,tegra30-ahb"; 505 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 506 }; 507 508 actmon: actmon@6000c800 { 509 compatible = "nvidia,tegra30-actmon"; 510 reg = <0x6000c800 0x400>; 511 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&tegra_car TEGRA30_CLK_ACTMON>, 513 <&tegra_car TEGRA30_CLK_EMC>; 514 clock-names = "actmon", "emc"; 515 resets = <&tegra_car TEGRA30_CLK_ACTMON>; 516 reset-names = "actmon"; 517 operating-points-v2 = <&emc_bw_dfs_opp_table>; 518 interconnects = <&mc TEGRA30_MC_MPCORER &emc>; 519 interconnect-names = "cpu-read"; 520 #cooling-cells = <2>; 521 }; 522 523 gpio: gpio@6000d000 { 524 compatible = "nvidia,tegra30-gpio"; 525 reg = <0x6000d000 0x1000>; 526 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 534 #gpio-cells = <2>; 535 gpio-controller; 536 #interrupt-cells = <2>; 537 interrupt-controller; 538 gpio-ranges = <&pinmux 0 0 248>; 539 }; 540 541 vde@6001a000 { 542 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 543 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 544 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 545 <0x6001c000 0x100>, /* Macroblock Engine */ 546 <0x6001c200 0x100>, /* Post-processing Engine */ 547 <0x6001c400 0x100>, /* Motion Compensation Engine */ 548 <0x6001c600 0x100>, /* Transform Engine */ 549 <0x6001c800 0x100>, /* Pixel prediction block */ 550 <0x6001ca00 0x100>, /* Video DMA */ 551 <0x6001d800 0x400>; /* Video frame controls */ 552 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 553 "tfe", "ppb", "vdma", "frameid"; 554 iram = <&vde_pool>; /* IRAM region */ 555 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 556 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 557 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 558 interrupt-names = "sync-token", "bsev", "sxe"; 559 clocks = <&tegra_car TEGRA30_CLK_VDE>; 560 reset-names = "vde", "mc"; 561 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 562 iommus = <&mc TEGRA_SWGROUP_VDE>; 563 power-domains = <&pd_vde>; 564 operating-points-v2 = <&vde_dvfs_opp_table>; 565 }; 566 567 apbmisc@70000800 { 568 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 569 reg = <0x70000800 0x64>, /* Chip revision */ 570 <0x70000008 0x04>; /* Strapping options */ 571 }; 572 573 pinmux: pinmux@70000868 { 574 compatible = "nvidia,tegra30-pinmux"; 575 reg = <0x70000868 0x0d4>, /* Pad control registers */ 576 <0x70003000 0x3e4>; /* Mux registers */ 577 }; 578 579 /* 580 * There are two serial driver i.e. 8250 based simple serial 581 * driver and APB DMA based serial driver for higher baudrate 582 * and performace. To enable the 8250 based driver, the compatible 583 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 584 * the APB DMA based serial driver, the compatible is 585 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 586 */ 587 uarta: serial@70006000 { 588 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 589 reg = <0x70006000 0x40>; 590 reg-shift = <2>; 591 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 593 resets = <&tegra_car 6>; 594 dmas = <&apbdma 8>, <&apbdma 8>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 uartb: serial@70006040 { 600 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 601 reg = <0x70006040 0x40>; 602 reg-shift = <2>; 603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 605 resets = <&tegra_car 7>; 606 dmas = <&apbdma 9>, <&apbdma 9>; 607 dma-names = "rx", "tx"; 608 status = "disabled"; 609 }; 610 611 uartc: serial@70006200 { 612 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 613 reg = <0x70006200 0x100>; 614 reg-shift = <2>; 615 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 617 resets = <&tegra_car 55>; 618 dmas = <&apbdma 10>, <&apbdma 10>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 623 uartd: serial@70006300 { 624 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 625 reg = <0x70006300 0x100>; 626 reg-shift = <2>; 627 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 629 resets = <&tegra_car 65>; 630 dmas = <&apbdma 19>, <&apbdma 19>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 uarte: serial@70006400 { 636 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 637 reg = <0x70006400 0x100>; 638 reg-shift = <2>; 639 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 641 resets = <&tegra_car 66>; 642 dmas = <&apbdma 20>, <&apbdma 20>; 643 dma-names = "rx", "tx"; 644 status = "disabled"; 645 }; 646 647 gmi@70009000 { 648 compatible = "nvidia,tegra30-gmi"; 649 reg = <0x70009000 0x1000>; 650 #address-cells = <2>; 651 #size-cells = <1>; 652 ranges = <0 0 0x48000000 0x7ffffff>; 653 clocks = <&tegra_car TEGRA30_CLK_NOR>; 654 clock-names = "gmi"; 655 resets = <&tegra_car 42>; 656 reset-names = "gmi"; 657 power-domains = <&pd_core>; 658 operating-points-v2 = <&nor_dvfs_opp_table>; 659 status = "disabled"; 660 }; 661 662 pwm: pwm@7000a000 { 663 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 664 reg = <0x7000a000 0x100>; 665 #pwm-cells = <2>; 666 clocks = <&tegra_car TEGRA30_CLK_PWM>; 667 resets = <&tegra_car 17>; 668 reset-names = "pwm"; 669 power-domains = <&pd_core>; 670 operating-points-v2 = <&pwm_dvfs_opp_table>; 671 status = "disabled"; 672 }; 673 674 i2c@7000c000 { 675 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 676 reg = <0x7000c000 0x100>; 677 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 681 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 682 clock-names = "div-clk", "fast-clk"; 683 resets = <&tegra_car 12>; 684 reset-names = "i2c"; 685 dmas = <&apbdma 21>, <&apbdma 21>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 i2c@7000c400 { 691 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 692 reg = <0x7000c400 0x100>; 693 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 697 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 698 clock-names = "div-clk", "fast-clk"; 699 resets = <&tegra_car 54>; 700 reset-names = "i2c"; 701 dmas = <&apbdma 22>, <&apbdma 22>; 702 dma-names = "rx", "tx"; 703 status = "disabled"; 704 }; 705 706 i2c@7000c500 { 707 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 708 reg = <0x7000c500 0x100>; 709 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 713 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 714 clock-names = "div-clk", "fast-clk"; 715 resets = <&tegra_car 67>; 716 reset-names = "i2c"; 717 dmas = <&apbdma 23>, <&apbdma 23>; 718 dma-names = "rx", "tx"; 719 status = "disabled"; 720 }; 721 722 i2c@7000c700 { 723 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 724 reg = <0x7000c700 0x100>; 725 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 729 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 730 resets = <&tegra_car 103>; 731 reset-names = "i2c"; 732 clock-names = "div-clk", "fast-clk"; 733 dmas = <&apbdma 26>, <&apbdma 26>; 734 dma-names = "rx", "tx"; 735 status = "disabled"; 736 }; 737 738 i2c@7000d000 { 739 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 740 reg = <0x7000d000 0x100>; 741 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 745 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 746 clock-names = "div-clk", "fast-clk"; 747 resets = <&tegra_car 47>; 748 reset-names = "i2c"; 749 dmas = <&apbdma 24>, <&apbdma 24>; 750 dma-names = "rx", "tx"; 751 status = "disabled"; 752 }; 753 754 spi@7000d400 { 755 compatible = "nvidia,tegra30-slink"; 756 reg = <0x7000d400 0x200>; 757 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 761 resets = <&tegra_car 41>; 762 reset-names = "spi"; 763 dmas = <&apbdma 15>, <&apbdma 15>; 764 dma-names = "rx", "tx"; 765 power-domains = <&pd_core>; 766 operating-points-v2 = <&sbc1_dvfs_opp_table>; 767 status = "disabled"; 768 }; 769 770 spi@7000d600 { 771 compatible = "nvidia,tegra30-slink"; 772 reg = <0x7000d600 0x200>; 773 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 777 resets = <&tegra_car 44>; 778 reset-names = "spi"; 779 dmas = <&apbdma 16>, <&apbdma 16>; 780 dma-names = "rx", "tx"; 781 power-domains = <&pd_core>; 782 operating-points-v2 = <&sbc2_dvfs_opp_table>; 783 status = "disabled"; 784 }; 785 786 spi@7000d800 { 787 compatible = "nvidia,tegra30-slink"; 788 reg = <0x7000d800 0x200>; 789 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 793 resets = <&tegra_car 46>; 794 reset-names = "spi"; 795 dmas = <&apbdma 17>, <&apbdma 17>; 796 dma-names = "rx", "tx"; 797 power-domains = <&pd_core>; 798 operating-points-v2 = <&sbc3_dvfs_opp_table>; 799 status = "disabled"; 800 }; 801 802 spi@7000da00 { 803 compatible = "nvidia,tegra30-slink"; 804 reg = <0x7000da00 0x200>; 805 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 809 resets = <&tegra_car 68>; 810 reset-names = "spi"; 811 dmas = <&apbdma 18>, <&apbdma 18>; 812 dma-names = "rx", "tx"; 813 power-domains = <&pd_core>; 814 operating-points-v2 = <&sbc4_dvfs_opp_table>; 815 status = "disabled"; 816 }; 817 818 spi@7000dc00 { 819 compatible = "nvidia,tegra30-slink"; 820 reg = <0x7000dc00 0x200>; 821 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 825 resets = <&tegra_car 104>; 826 reset-names = "spi"; 827 dmas = <&apbdma 27>, <&apbdma 27>; 828 dma-names = "rx", "tx"; 829 power-domains = <&pd_core>; 830 operating-points-v2 = <&sbc5_dvfs_opp_table>; 831 status = "disabled"; 832 }; 833 834 spi@7000de00 { 835 compatible = "nvidia,tegra30-slink"; 836 reg = <0x7000de00 0x200>; 837 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 841 resets = <&tegra_car 106>; 842 reset-names = "spi"; 843 dmas = <&apbdma 28>, <&apbdma 28>; 844 dma-names = "rx", "tx"; 845 power-domains = <&pd_core>; 846 operating-points-v2 = <&sbc6_dvfs_opp_table>; 847 status = "disabled"; 848 }; 849 850 rtc@7000e000 { 851 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 852 reg = <0x7000e000 0x100>; 853 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&tegra_car TEGRA30_CLK_RTC>; 855 }; 856 857 kbc@7000e200 { 858 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 859 reg = <0x7000e200 0x100>; 860 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&tegra_car TEGRA30_CLK_KBC>; 862 resets = <&tegra_car 36>; 863 reset-names = "kbc"; 864 status = "disabled"; 865 }; 866 867 tegra_pmc: pmc@7000e400 { 868 compatible = "nvidia,tegra30-pmc"; 869 reg = <0x7000e400 0x400>; 870 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 871 clock-names = "pclk", "clk32k_in"; 872 #clock-cells = <1>; 873 874 pd_core: core-domain { 875 #power-domain-cells = <0>; 876 operating-points-v2 = <&core_opp_table>; 877 }; 878 879 powergates { 880 pd_heg: heg { 881 clocks = <&tegra_car TEGRA30_CLK_GR2D>, 882 <&tegra_car TEGRA30_CLK_EPP>, 883 <&tegra_car TEGRA30_CLK_HOST1X>; 884 resets = <&mc TEGRA30_MC_RESET_2D>, 885 <&mc TEGRA30_MC_RESET_EPP>, 886 <&mc TEGRA30_MC_RESET_HC>, 887 <&tegra_car TEGRA30_CLK_GR2D>, 888 <&tegra_car TEGRA30_CLK_EPP>, 889 <&tegra_car TEGRA30_CLK_HOST1X>; 890 power-domains = <&pd_core>; 891 #power-domain-cells = <0>; 892 }; 893 894 pd_mpe: mpe { 895 clocks = <&tegra_car TEGRA30_CLK_MPE>; 896 resets = <&mc TEGRA30_MC_RESET_MPE>, 897 <&tegra_car TEGRA30_CLK_MPE>; 898 power-domains = <&pd_core>; 899 #power-domain-cells = <0>; 900 }; 901 902 pd_3d0: td { 903 clocks = <&tegra_car TEGRA30_CLK_GR3D>; 904 resets = <&mc TEGRA30_MC_RESET_3D>, 905 <&tegra_car TEGRA30_CLK_GR3D>; 906 power-domains = <&pd_core>; 907 #power-domain-cells = <0>; 908 }; 909 910 pd_3d1: td2 { 911 clocks = <&tegra_car TEGRA30_CLK_GR3D2>; 912 resets = <&mc TEGRA30_MC_RESET_3D2>, 913 <&tegra_car TEGRA30_CLK_GR3D2>; 914 power-domains = <&pd_core>; 915 #power-domain-cells = <0>; 916 }; 917 918 pd_vde: vdec { 919 clocks = <&tegra_car TEGRA30_CLK_VDE>; 920 resets = <&mc TEGRA30_MC_RESET_VDE>, 921 <&tegra_car TEGRA30_CLK_VDE>; 922 power-domains = <&pd_core>; 923 #power-domain-cells = <0>; 924 }; 925 926 pd_venc: venc { 927 clocks = <&tegra_car TEGRA30_CLK_ISP>, 928 <&tegra_car TEGRA30_CLK_VI>, 929 <&tegra_car TEGRA30_CLK_CSI>; 930 resets = <&mc TEGRA30_MC_RESET_ISP>, 931 <&mc TEGRA30_MC_RESET_VI>, 932 <&tegra_car TEGRA30_CLK_ISP>, 933 <&tegra_car 20 /* VI */>, 934 <&tegra_car TEGRA30_CLK_CSI>; 935 power-domains = <&pd_core>; 936 #power-domain-cells = <0>; 937 }; 938 }; 939 }; 940 941 mc: memory-controller@7000f000 { 942 compatible = "nvidia,tegra30-mc"; 943 reg = <0x7000f000 0x400>; 944 clocks = <&tegra_car TEGRA30_CLK_MC>; 945 clock-names = "mc"; 946 947 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 948 949 #iommu-cells = <1>; 950 #reset-cells = <1>; 951 #interconnect-cells = <1>; 952 }; 953 954 emc: memory-controller@7000f400 { 955 compatible = "nvidia,tegra30-emc"; 956 reg = <0x7000f400 0x400>; 957 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&tegra_car TEGRA30_CLK_EMC>; 959 power-domains = <&pd_core>; 960 961 nvidia,memory-controller = <&mc>; 962 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 963 964 #interconnect-cells = <0>; 965 }; 966 967 fuse@7000f800 { 968 compatible = "nvidia,tegra30-efuse"; 969 reg = <0x7000f800 0x400>; 970 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 971 clock-names = "fuse"; 972 resets = <&tegra_car 39>; 973 reset-names = "fuse"; 974 power-domains = <&pd_core>; 975 operating-points-v2 = <&fuse_burn_dvfs_opp_table>; 976 }; 977 978 tsensor: tsensor@70014000 { 979 compatible = "nvidia,tegra30-tsensor"; 980 reg = <0x70014000 0x500>; 981 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 983 resets = <&tegra_car TEGRA30_CLK_TSENSOR>; 984 985 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 986 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; 987 assigned-clock-rates = <500000>; 988 989 #thermal-sensor-cells = <1>; 990 }; 991 992 hda@70030000 { 993 compatible = "nvidia,tegra30-hda"; 994 reg = <0x70030000 0x10000>; 995 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&tegra_car TEGRA30_CLK_HDA>, 997 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 998 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 999 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1000 resets = <&tegra_car 125>, /* hda */ 1001 <&tegra_car 128>, /* hda2hdmi */ 1002 <&tegra_car 111>; /* hda2codec_2x */ 1003 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1004 status = "disabled"; 1005 }; 1006 1007 ahub@70080000 { 1008 compatible = "nvidia,tegra30-ahub"; 1009 reg = <0x70080000 0x200>, 1010 <0x70080200 0x100>; 1011 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 1013 <&tegra_car TEGRA30_CLK_APBIF>; 1014 clock-names = "d_audio", "apbif"; 1015 resets = <&tegra_car 106>, /* d_audio */ 1016 <&tegra_car 107>, /* apbif */ 1017 <&tegra_car 30>, /* i2s0 */ 1018 <&tegra_car 11>, /* i2s1 */ 1019 <&tegra_car 18>, /* i2s2 */ 1020 <&tegra_car 101>, /* i2s3 */ 1021 <&tegra_car 102>, /* i2s4 */ 1022 <&tegra_car 108>, /* dam0 */ 1023 <&tegra_car 109>, /* dam1 */ 1024 <&tegra_car 110>, /* dam2 */ 1025 <&tegra_car 10>; /* spdif */ 1026 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1027 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1028 "spdif"; 1029 dmas = <&apbdma 1>, <&apbdma 1>, 1030 <&apbdma 2>, <&apbdma 2>, 1031 <&apbdma 3>, <&apbdma 3>, 1032 <&apbdma 4>, <&apbdma 4>; 1033 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1034 "rx3", "tx3"; 1035 ranges; 1036 #address-cells = <1>; 1037 #size-cells = <1>; 1038 1039 tegra_i2s0: i2s@70080300 { 1040 compatible = "nvidia,tegra30-i2s"; 1041 reg = <0x70080300 0x100>; 1042 nvidia,ahub-cif-ids = <4 4>; 1043 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 1044 resets = <&tegra_car 30>; 1045 reset-names = "i2s"; 1046 status = "disabled"; 1047 }; 1048 1049 tegra_i2s1: i2s@70080400 { 1050 compatible = "nvidia,tegra30-i2s"; 1051 reg = <0x70080400 0x100>; 1052 nvidia,ahub-cif-ids = <5 5>; 1053 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 1054 resets = <&tegra_car 11>; 1055 reset-names = "i2s"; 1056 status = "disabled"; 1057 }; 1058 1059 tegra_i2s2: i2s@70080500 { 1060 compatible = "nvidia,tegra30-i2s"; 1061 reg = <0x70080500 0x100>; 1062 nvidia,ahub-cif-ids = <6 6>; 1063 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 1064 resets = <&tegra_car 18>; 1065 reset-names = "i2s"; 1066 status = "disabled"; 1067 }; 1068 1069 tegra_i2s3: i2s@70080600 { 1070 compatible = "nvidia,tegra30-i2s"; 1071 reg = <0x70080600 0x100>; 1072 nvidia,ahub-cif-ids = <7 7>; 1073 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 1074 resets = <&tegra_car 101>; 1075 reset-names = "i2s"; 1076 status = "disabled"; 1077 }; 1078 1079 tegra_i2s4: i2s@70080700 { 1080 compatible = "nvidia,tegra30-i2s"; 1081 reg = <0x70080700 0x100>; 1082 nvidia,ahub-cif-ids = <8 8>; 1083 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 1084 resets = <&tegra_car 102>; 1085 reset-names = "i2s"; 1086 status = "disabled"; 1087 }; 1088 }; 1089 1090 mmc@78000000 { 1091 compatible = "nvidia,tegra30-sdhci"; 1092 reg = <0x78000000 0x200>; 1093 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 1095 clock-names = "sdhci"; 1096 resets = <&tegra_car 14>; 1097 reset-names = "sdhci"; 1098 power-domains = <&pd_core>; 1099 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 1100 status = "disabled"; 1101 }; 1102 1103 mmc@78000200 { 1104 compatible = "nvidia,tegra30-sdhci"; 1105 reg = <0x78000200 0x200>; 1106 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 1108 clock-names = "sdhci"; 1109 resets = <&tegra_car 9>; 1110 reset-names = "sdhci"; 1111 status = "disabled"; 1112 }; 1113 1114 mmc@78000400 { 1115 compatible = "nvidia,tegra30-sdhci"; 1116 reg = <0x78000400 0x200>; 1117 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 1119 clock-names = "sdhci"; 1120 resets = <&tegra_car 69>; 1121 reset-names = "sdhci"; 1122 power-domains = <&pd_core>; 1123 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1124 status = "disabled"; 1125 }; 1126 1127 mmc@78000600 { 1128 compatible = "nvidia,tegra30-sdhci"; 1129 reg = <0x78000600 0x200>; 1130 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 1132 clock-names = "sdhci"; 1133 resets = <&tegra_car 15>; 1134 reset-names = "sdhci"; 1135 status = "disabled"; 1136 }; 1137 1138 usb@7d000000 { 1139 compatible = "nvidia,tegra30-ehci"; 1140 reg = <0x7d000000 0x4000>; 1141 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1142 phy_type = "utmi"; 1143 clocks = <&tegra_car TEGRA30_CLK_USBD>; 1144 resets = <&tegra_car 22>; 1145 reset-names = "usb"; 1146 nvidia,needs-double-reset; 1147 nvidia,phy = <&phy1>; 1148 power-domains = <&pd_core>; 1149 operating-points-v2 = <&usbd_dvfs_opp_table>; 1150 status = "disabled"; 1151 }; 1152 1153 phy1: usb-phy@7d000000 { 1154 compatible = "nvidia,tegra30-usb-phy"; 1155 reg = <0x7d000000 0x4000>, 1156 <0x7d000000 0x4000>; 1157 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1158 phy_type = "utmi"; 1159 clocks = <&tegra_car TEGRA30_CLK_USBD>, 1160 <&tegra_car TEGRA30_CLK_PLL_U>, 1161 <&tegra_car TEGRA30_CLK_USBD>; 1162 clock-names = "reg", "pll_u", "utmi-pads"; 1163 resets = <&tegra_car 22>, <&tegra_car 22>; 1164 reset-names = "usb", "utmi-pads"; 1165 #phy-cells = <0>; 1166 nvidia,hssync-start-delay = <9>; 1167 nvidia,idle-wait-delay = <17>; 1168 nvidia,elastic-limit = <16>; 1169 nvidia,term-range-adj = <6>; 1170 nvidia,xcvr-setup = <51>; 1171 nvidia,xcvr-setup-use-fuses; 1172 nvidia,xcvr-lsfslew = <1>; 1173 nvidia,xcvr-lsrslew = <1>; 1174 nvidia,xcvr-hsslew = <32>; 1175 nvidia,hssquelch-level = <2>; 1176 nvidia,hsdiscon-level = <5>; 1177 nvidia,has-utmi-pad-registers; 1178 nvidia,pmc = <&tegra_pmc 0>; 1179 status = "disabled"; 1180 }; 1181 1182 usb@7d004000 { 1183 compatible = "nvidia,tegra30-ehci"; 1184 reg = <0x7d004000 0x4000>; 1185 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1186 phy_type = "utmi"; 1187 clocks = <&tegra_car TEGRA30_CLK_USB2>; 1188 resets = <&tegra_car 58>; 1189 reset-names = "usb"; 1190 nvidia,phy = <&phy2>; 1191 power-domains = <&pd_core>; 1192 operating-points-v2 = <&usb2_dvfs_opp_table>; 1193 status = "disabled"; 1194 }; 1195 1196 phy2: usb-phy@7d004000 { 1197 compatible = "nvidia,tegra30-usb-phy"; 1198 reg = <0x7d004000 0x4000>, 1199 <0x7d000000 0x4000>; 1200 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1201 phy_type = "utmi"; 1202 clocks = <&tegra_car TEGRA30_CLK_USB2>, 1203 <&tegra_car TEGRA30_CLK_PLL_U>, 1204 <&tegra_car TEGRA30_CLK_USBD>; 1205 clock-names = "reg", "pll_u", "utmi-pads"; 1206 resets = <&tegra_car 58>, <&tegra_car 22>; 1207 reset-names = "usb", "utmi-pads"; 1208 #phy-cells = <0>; 1209 nvidia,hssync-start-delay = <9>; 1210 nvidia,idle-wait-delay = <17>; 1211 nvidia,elastic-limit = <16>; 1212 nvidia,term-range-adj = <6>; 1213 nvidia,xcvr-setup = <51>; 1214 nvidia,xcvr-setup-use-fuses; 1215 nvidia,xcvr-lsfslew = <2>; 1216 nvidia,xcvr-lsrslew = <2>; 1217 nvidia,xcvr-hsslew = <32>; 1218 nvidia,hssquelch-level = <2>; 1219 nvidia,hsdiscon-level = <5>; 1220 nvidia,pmc = <&tegra_pmc 2>; 1221 status = "disabled"; 1222 }; 1223 1224 usb@7d008000 { 1225 compatible = "nvidia,tegra30-ehci"; 1226 reg = <0x7d008000 0x4000>; 1227 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1228 phy_type = "utmi"; 1229 clocks = <&tegra_car TEGRA30_CLK_USB3>; 1230 resets = <&tegra_car 59>; 1231 reset-names = "usb"; 1232 nvidia,phy = <&phy3>; 1233 power-domains = <&pd_core>; 1234 operating-points-v2 = <&usb3_dvfs_opp_table>; 1235 status = "disabled"; 1236 }; 1237 1238 phy3: usb-phy@7d008000 { 1239 compatible = "nvidia,tegra30-usb-phy"; 1240 reg = <0x7d008000 0x4000>, 1241 <0x7d000000 0x4000>; 1242 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1243 phy_type = "utmi"; 1244 clocks = <&tegra_car TEGRA30_CLK_USB3>, 1245 <&tegra_car TEGRA30_CLK_PLL_U>, 1246 <&tegra_car TEGRA30_CLK_USBD>; 1247 clock-names = "reg", "pll_u", "utmi-pads"; 1248 resets = <&tegra_car 59>, <&tegra_car 22>; 1249 reset-names = "usb", "utmi-pads"; 1250 #phy-cells = <0>; 1251 nvidia,hssync-start-delay = <0>; 1252 nvidia,idle-wait-delay = <17>; 1253 nvidia,elastic-limit = <16>; 1254 nvidia,term-range-adj = <6>; 1255 nvidia,xcvr-setup = <51>; 1256 nvidia,xcvr-setup-use-fuses; 1257 nvidia,xcvr-lsfslew = <2>; 1258 nvidia,xcvr-lsrslew = <2>; 1259 nvidia,xcvr-hsslew = <32>; 1260 nvidia,hssquelch-level = <2>; 1261 nvidia,hsdiscon-level = <5>; 1262 nvidia,pmc = <&tegra_pmc 1>; 1263 status = "disabled"; 1264 }; 1265 1266 cpus { 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 cpu0: cpu@0 { 1271 device_type = "cpu"; 1272 compatible = "arm,cortex-a9"; 1273 reg = <0>; 1274 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1275 #cooling-cells = <2>; 1276 }; 1277 1278 cpu1: cpu@1 { 1279 device_type = "cpu"; 1280 compatible = "arm,cortex-a9"; 1281 reg = <1>; 1282 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1283 #cooling-cells = <2>; 1284 }; 1285 1286 cpu2: cpu@2 { 1287 device_type = "cpu"; 1288 compatible = "arm,cortex-a9"; 1289 reg = <2>; 1290 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1291 #cooling-cells = <2>; 1292 }; 1293 1294 cpu3: cpu@3 { 1295 device_type = "cpu"; 1296 compatible = "arm,cortex-a9"; 1297 reg = <3>; 1298 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1299 #cooling-cells = <2>; 1300 }; 1301 }; 1302 1303 pmu { 1304 compatible = "arm,cortex-a9-pmu"; 1305 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1309 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1310 }; 1311 1312 thermal-zones { 1313 tsensor0-thermal { 1314 polling-delay-passive = <1000>; /* milliseconds */ 1315 polling-delay = <5000>; /* milliseconds */ 1316 1317 thermal-sensors = <&tsensor 0>; 1318 1319 trips { 1320 level1_trip: dvfs-alert { 1321 /* throttle at 80C until temperature drops to 79.8C */ 1322 temperature = <80000>; 1323 hysteresis = <200>; 1324 type = "passive"; 1325 }; 1326 1327 level2_trip: cpu-div2-throttle { 1328 /* hardware CPU x2 freq throttle at 85C */ 1329 temperature = <85000>; 1330 hysteresis = <200>; 1331 type = "hot"; 1332 }; 1333 1334 level3_trip: soc-critical { 1335 /* hardware shut down at 90C */ 1336 temperature = <90000>; 1337 hysteresis = <2000>; 1338 type = "critical"; 1339 }; 1340 }; 1341 1342 cooling-maps { 1343 map0 { 1344 trip = <&level1_trip>; 1345 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1346 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1347 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1348 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1349 <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1350 }; 1351 }; 1352 }; 1353 1354 tsensor1-thermal { 1355 status = "disabled"; 1356 1357 polling-delay-passive = <1000>; /* milliseconds */ 1358 polling-delay = <0>; /* milliseconds */ 1359 1360 thermal-sensors = <&tsensor 1>; 1361 1362 trips { 1363 dvfs-alert { 1364 temperature = <80000>; 1365 hysteresis = <200>; 1366 type = "passive"; 1367 }; 1368 }; 1369 }; 1370 }; 1371}; 1372