1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h> 5*724ba675SRob Herring#include <dt-bindings/input/input.h> 6*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 7*724ba675SRob Herring 8*724ba675SRob Herring#include "tegra30.dtsi" 9*724ba675SRob Herring#include "tegra30-cpu-opp.dtsi" 10*724ba675SRob Herring#include "tegra30-cpu-opp-microvolt.dtsi" 11*724ba675SRob Herring#include "tegra30-asus-lvds-display.dtsi" 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "Pegatron Chagall"; 15*724ba675SRob Herring compatible = "pegatron,chagall", "nvidia,tegra30"; 16*724ba675SRob Herring chassis-type = "tablet"; 17*724ba675SRob Herring 18*724ba675SRob Herring aliases { 19*724ba675SRob Herring mmc0 = &sdmmc4; /* eMMC */ 20*724ba675SRob Herring mmc1 = &sdmmc1; /* uSD slot */ 21*724ba675SRob Herring mmc2 = &sdmmc3; /* WiFi */ 22*724ba675SRob Herring 23*724ba675SRob Herring rtc0 = &pmic; 24*724ba675SRob Herring rtc1 = "/rtc@7000e000"; 25*724ba675SRob Herring 26*724ba675SRob Herring display0 = &lcd; 27*724ba675SRob Herring display1 = &hdmi; 28*724ba675SRob Herring 29*724ba675SRob Herring serial1 = &uartc; /* Bluetooth */ 30*724ba675SRob Herring serial2 = &uartb; /* GPS */ 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring /* 34*724ba675SRob Herring * The decompressor and also some bootloaders rely on a 35*724ba675SRob Herring * pre-existing /chosen node to be available to insert the 36*724ba675SRob Herring * command line and merge other ATAGS info. 37*724ba675SRob Herring */ 38*724ba675SRob Herring chosen {}; 39*724ba675SRob Herring 40*724ba675SRob Herring firmware { 41*724ba675SRob Herring trusted-foundations { 42*724ba675SRob Herring compatible = "tlm,trusted-foundations"; 43*724ba675SRob Herring tlm,version-major = <2>; 44*724ba675SRob Herring tlm,version-minor = <8>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring }; 47*724ba675SRob Herring 48*724ba675SRob Herring memory@80000000 { 49*724ba675SRob Herring reg = <0x80000000 0x40000000>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring reserved-memory { 53*724ba675SRob Herring #address-cells = <1>; 54*724ba675SRob Herring #size-cells = <1>; 55*724ba675SRob Herring ranges; 56*724ba675SRob Herring 57*724ba675SRob Herring linux,cma@80000000 { 58*724ba675SRob Herring compatible = "shared-dma-pool"; 59*724ba675SRob Herring alloc-ranges = <0x80000000 0x30000000>; 60*724ba675SRob Herring size = <0x10000000>; /* 256MiB */ 61*724ba675SRob Herring linux,cma-default; 62*724ba675SRob Herring reusable; 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring ramoops@beb00000 { 66*724ba675SRob Herring compatible = "ramoops"; 67*724ba675SRob Herring reg = <0xbeb00000 0x10000>; /* 64kB */ 68*724ba675SRob Herring console-size = <0x8000>; /* 32kB */ 69*724ba675SRob Herring record-size = <0x400>; /* 1kB */ 70*724ba675SRob Herring ecc-size = <16>; 71*724ba675SRob Herring }; 72*724ba675SRob Herring 73*724ba675SRob Herring trustzone@bfe00000 { 74*724ba675SRob Herring reg = <0xbfe00000 0x200000>; /* 2MB */ 75*724ba675SRob Herring no-map; 76*724ba675SRob Herring }; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring host1x@50000000 { 80*724ba675SRob Herring hdmi: hdmi@54280000 { 81*724ba675SRob Herring status = "okay"; 82*724ba675SRob Herring 83*724ba675SRob Herring hdmi-supply = <&hdmi_5v0_sys>; 84*724ba675SRob Herring pll-supply = <&vdd_1v8_vio>; 85*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 86*724ba675SRob Herring 87*724ba675SRob Herring nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 88*724ba675SRob Herring nvidia,ddc-i2c-bus = <&hdmi_ddc>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring }; 91*724ba675SRob Herring 92*724ba675SRob Herring vde@6001a000 { 93*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; 94*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; 95*724ba675SRob Herring assigned-clock-rates = <408000000>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring pinmux@70000868 { 99*724ba675SRob Herring pinctrl-names = "default"; 100*724ba675SRob Herring pinctrl-0 = <&state_default>; 101*724ba675SRob Herring 102*724ba675SRob Herring state_default: pinmux { 103*724ba675SRob Herring /* SDMMC1 pinmux */ 104*724ba675SRob Herring sdmmc1_clk_pz0 { 105*724ba675SRob Herring nvidia,pins = "sdmmc1_clk_pz0"; 106*724ba675SRob Herring nvidia,function = "sdmmc1"; 107*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 108*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 109*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring sdmmc1_dat3_py4 { 113*724ba675SRob Herring nvidia,pins = "sdmmc1_dat3_py4", 114*724ba675SRob Herring "sdmmc1_dat2_py5", 115*724ba675SRob Herring "sdmmc1_dat1_py6", 116*724ba675SRob Herring "sdmmc1_dat0_py7", 117*724ba675SRob Herring "sdmmc1_cmd_pz1"; 118*724ba675SRob Herring nvidia,function = "sdmmc1"; 119*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 120*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 121*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122*724ba675SRob Herring }; 123*724ba675SRob Herring 124*724ba675SRob Herring /* SDMMC2 pinmux */ 125*724ba675SRob Herring vi_d1_pd5 { 126*724ba675SRob Herring nvidia,pins = "vi_d1_pd5", 127*724ba675SRob Herring "vi_d2_pl0", 128*724ba675SRob Herring "vi_d3_pl1", 129*724ba675SRob Herring "vi_d5_pl3", 130*724ba675SRob Herring "vi_d7_pl5"; 131*724ba675SRob Herring nvidia,function = "sdmmc2"; 132*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 134*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 135*724ba675SRob Herring }; 136*724ba675SRob Herring 137*724ba675SRob Herring vi_d8_pl6 { 138*724ba675SRob Herring nvidia,pins = "vi_d8_pl6", 139*724ba675SRob Herring "vi_d9_pl7"; 140*724ba675SRob Herring nvidia,function = "sdmmc2"; 141*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 142*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 143*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 144*724ba675SRob Herring nvidia,lock = <0>; 145*724ba675SRob Herring nvidia,io-reset = <0>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring 148*724ba675SRob Herring /* SDMMC3 pinmux */ 149*724ba675SRob Herring sdmmc3_clk_pa6 { 150*724ba675SRob Herring nvidia,pins = "sdmmc3_clk_pa6"; 151*724ba675SRob Herring nvidia,function = "sdmmc3"; 152*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 153*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 154*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring sdmmc3_cmd_pa7 { 158*724ba675SRob Herring nvidia,pins = "sdmmc3_cmd_pa7", 159*724ba675SRob Herring "sdmmc3_dat3_pb4", 160*724ba675SRob Herring "sdmmc3_dat2_pb5", 161*724ba675SRob Herring "sdmmc3_dat1_pb6", 162*724ba675SRob Herring "sdmmc3_dat0_pb7", 163*724ba675SRob Herring "sdmmc3_dat5_pd0", 164*724ba675SRob Herring "sdmmc3_dat4_pd1", 165*724ba675SRob Herring "sdmmc3_dat6_pd3", 166*724ba675SRob Herring "sdmmc3_dat7_pd4"; 167*724ba675SRob Herring nvidia,function = "sdmmc3"; 168*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 169*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 170*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring /* SDMMC4 pinmux */ 174*724ba675SRob Herring sdmmc4_clk_pcc4 { 175*724ba675SRob Herring nvidia,pins = "sdmmc4_clk_pcc4"; 176*724ba675SRob Herring nvidia,function = "sdmmc4"; 177*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 178*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 179*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 180*724ba675SRob Herring }; 181*724ba675SRob Herring 182*724ba675SRob Herring sdmmc4_cmd_pt7 { 183*724ba675SRob Herring nvidia,pins = "sdmmc4_cmd_pt7", 184*724ba675SRob Herring "sdmmc4_dat0_paa0", 185*724ba675SRob Herring "sdmmc4_dat1_paa1", 186*724ba675SRob Herring "sdmmc4_dat2_paa2", 187*724ba675SRob Herring "sdmmc4_dat3_paa3", 188*724ba675SRob Herring "sdmmc4_dat4_paa4", 189*724ba675SRob Herring "sdmmc4_dat5_paa5", 190*724ba675SRob Herring "sdmmc4_dat6_paa6", 191*724ba675SRob Herring "sdmmc4_dat7_paa7"; 192*724ba675SRob Herring nvidia,function = "sdmmc4"; 193*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 194*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 195*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 196*724ba675SRob Herring }; 197*724ba675SRob Herring 198*724ba675SRob Herring /* I2C pinmux */ 199*724ba675SRob Herring gen1_i2c_scl_pc4 { 200*724ba675SRob Herring nvidia,pins = "gen1_i2c_scl_pc4", 201*724ba675SRob Herring "gen1_i2c_sda_pc5"; 202*724ba675SRob Herring nvidia,function = "i2c1"; 203*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 204*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 205*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 206*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 207*724ba675SRob Herring nvidia,lock = <0>; 208*724ba675SRob Herring }; 209*724ba675SRob Herring 210*724ba675SRob Herring gen2_i2c_scl_pt5 { 211*724ba675SRob Herring nvidia,pins = "gen2_i2c_scl_pt5", 212*724ba675SRob Herring "gen2_i2c_sda_pt6"; 213*724ba675SRob Herring nvidia,function = "i2c2"; 214*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 216*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 217*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 218*724ba675SRob Herring nvidia,lock = <0>; 219*724ba675SRob Herring }; 220*724ba675SRob Herring 221*724ba675SRob Herring cam_i2c_scl_pbb1 { 222*724ba675SRob Herring nvidia,pins = "cam_i2c_scl_pbb1", 223*724ba675SRob Herring "cam_i2c_sda_pbb2"; 224*724ba675SRob Herring nvidia,function = "i2c3"; 225*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 226*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 227*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 228*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 229*724ba675SRob Herring nvidia,lock = <0>; 230*724ba675SRob Herring }; 231*724ba675SRob Herring 232*724ba675SRob Herring ddc_scl_pv4 { 233*724ba675SRob Herring nvidia,pins = "ddc_scl_pv4", 234*724ba675SRob Herring "ddc_sda_pv5"; 235*724ba675SRob Herring nvidia,function = "i2c4"; 236*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 238*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239*724ba675SRob Herring nvidia,lock = <0>; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring pwr_i2c_scl_pz6 { 243*724ba675SRob Herring nvidia,pins = "pwr_i2c_scl_pz6", 244*724ba675SRob Herring "pwr_i2c_sda_pz7"; 245*724ba675SRob Herring nvidia,function = "i2cpwr"; 246*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 248*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 249*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 250*724ba675SRob Herring nvidia,lock = <0>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring /* HDMI-CEC pinmux */ 254*724ba675SRob Herring hdmi_cec_pee3 { 255*724ba675SRob Herring nvidia,pins = "hdmi_cec_pee3"; 256*724ba675SRob Herring nvidia,function = "cec"; 257*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 259*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 260*724ba675SRob Herring nvidia,open-drain = <TEGRA_PIN_ENABLE>; 261*724ba675SRob Herring nvidia,lock = <0>; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring /* UART-A */ 265*724ba675SRob Herring ulpi_data0_po1 { 266*724ba675SRob Herring nvidia,pins = "ulpi_data0_po1"; 267*724ba675SRob Herring nvidia,function = "uarta"; 268*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 269*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring ulpi_data1_po2 { 274*724ba675SRob Herring nvidia,pins = "ulpi_data1_po2", 275*724ba675SRob Herring "ulpi_data2_po3", 276*724ba675SRob Herring "ulpi_data3_po4", 277*724ba675SRob Herring "ulpi_data4_po5", 278*724ba675SRob Herring "ulpi_data5_po6", 279*724ba675SRob Herring "ulpi_data6_po7"; 280*724ba675SRob Herring nvidia,function = "uarta"; 281*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 282*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 283*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring ulpi_data7_po0 { 287*724ba675SRob Herring nvidia,pins = "ulpi_data7_po0"; 288*724ba675SRob Herring nvidia,function = "uarta"; 289*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 290*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 291*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring 294*724ba675SRob Herring /* UART-B */ 295*724ba675SRob Herring uart2_txd_pc2 { 296*724ba675SRob Herring nvidia,pins = "uart2_txd_pc2", 297*724ba675SRob Herring "uart2_rts_n_pj6"; 298*724ba675SRob Herring nvidia,function = "uartb"; 299*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 300*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 301*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 302*724ba675SRob Herring }; 303*724ba675SRob Herring 304*724ba675SRob Herring uart2_rxd_pc3 { 305*724ba675SRob Herring nvidia,pins = "uart2_rxd_pc3", 306*724ba675SRob Herring "uart2_cts_n_pj5"; 307*724ba675SRob Herring nvidia,function = "uartb"; 308*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 309*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 310*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 311*724ba675SRob Herring }; 312*724ba675SRob Herring 313*724ba675SRob Herring /* UART-C */ 314*724ba675SRob Herring uart3_cts_n_pa1 { 315*724ba675SRob Herring nvidia,pins = "uart3_cts_n_pa1", 316*724ba675SRob Herring "uart3_rxd_pw7"; 317*724ba675SRob Herring nvidia,function = "uartc"; 318*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 319*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 320*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 321*724ba675SRob Herring }; 322*724ba675SRob Herring 323*724ba675SRob Herring uart3_rts_n_pc0 { 324*724ba675SRob Herring nvidia,pins = "uart3_rts_n_pc0", 325*724ba675SRob Herring "uart3_txd_pw6"; 326*724ba675SRob Herring nvidia,function = "uartc"; 327*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 328*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 329*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 330*724ba675SRob Herring }; 331*724ba675SRob Herring 332*724ba675SRob Herring /* UART-D */ 333*724ba675SRob Herring ulpi_clk_py0 { 334*724ba675SRob Herring nvidia,pins = "ulpi_clk_py0", 335*724ba675SRob Herring "ulpi_stp_py3"; 336*724ba675SRob Herring nvidia,function = "uartd"; 337*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 338*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 339*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring ulpi_dir_py1 { 343*724ba675SRob Herring nvidia,pins = "ulpi_dir_py1", 344*724ba675SRob Herring "ulpi_nxt_py2"; 345*724ba675SRob Herring nvidia,function = "uartd"; 346*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 347*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 348*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring /* I2S pinmux */ 352*724ba675SRob Herring dap1_fs_pn0 { 353*724ba675SRob Herring nvidia,pins = "dap1_fs_pn0", 354*724ba675SRob Herring "dap1_din_pn1", 355*724ba675SRob Herring "dap1_dout_pn2", 356*724ba675SRob Herring "dap1_sclk_pn3"; 357*724ba675SRob Herring nvidia,function = "i2s0"; 358*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 359*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 360*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 361*724ba675SRob Herring }; 362*724ba675SRob Herring 363*724ba675SRob Herring dap2_fs_pa2 { 364*724ba675SRob Herring nvidia,pins = "dap2_fs_pa2", 365*724ba675SRob Herring "dap2_sclk_pa3", 366*724ba675SRob Herring "dap2_din_pa4", 367*724ba675SRob Herring "dap2_dout_pa5"; 368*724ba675SRob Herring nvidia,function = "i2s1"; 369*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 370*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 371*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring dap3_fs_pp0 { 375*724ba675SRob Herring nvidia,pins = "dap3_fs_pp0", 376*724ba675SRob Herring "dap3_din_pp1", 377*724ba675SRob Herring "dap3_dout_pp2", 378*724ba675SRob Herring "dap3_sclk_pp3"; 379*724ba675SRob Herring nvidia,function = "i2s2"; 380*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 381*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 382*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 383*724ba675SRob Herring }; 384*724ba675SRob Herring 385*724ba675SRob Herring dap4_fs_pp4 { 386*724ba675SRob Herring nvidia,pins = "dap4_fs_pp4", 387*724ba675SRob Herring "dap4_din_pp5", 388*724ba675SRob Herring "dap4_dout_pp6", 389*724ba675SRob Herring "dap4_sclk_pp7"; 390*724ba675SRob Herring nvidia,function = "i2s3"; 391*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 392*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 393*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring pcc2 { 397*724ba675SRob Herring nvidia,pins = "pcc2"; 398*724ba675SRob Herring nvidia,function = "i2s4"; 399*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 400*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 401*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 402*724ba675SRob Herring }; 403*724ba675SRob Herring 404*724ba675SRob Herring /* PCI-e pinmux */ 405*724ba675SRob Herring pex_l2_rst_n_pcc6 { 406*724ba675SRob Herring nvidia,pins = "pex_l2_rst_n_pcc6", 407*724ba675SRob Herring "pex_l0_rst_n_pdd1", 408*724ba675SRob Herring "pex_l1_rst_n_pdd5"; 409*724ba675SRob Herring nvidia,function = "pcie"; 410*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 411*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 412*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 413*724ba675SRob Herring }; 414*724ba675SRob Herring 415*724ba675SRob Herring pex_l2_clkreq_n_pcc7 { 416*724ba675SRob Herring nvidia,pins = "pex_l2_clkreq_n_pcc7", 417*724ba675SRob Herring "pex_l0_prsnt_n_pdd0", 418*724ba675SRob Herring "pex_l0_clkreq_n_pdd2", 419*724ba675SRob Herring "pex_l2_prsnt_n_pdd7"; 420*724ba675SRob Herring nvidia,function = "pcie"; 421*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 423*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 424*724ba675SRob Herring }; 425*724ba675SRob Herring 426*724ba675SRob Herring pex_wake_n_pdd3 { 427*724ba675SRob Herring nvidia,pins = "pex_wake_n_pdd3"; 428*724ba675SRob Herring nvidia,function = "pcie"; 429*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 430*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 431*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 432*724ba675SRob Herring }; 433*724ba675SRob Herring 434*724ba675SRob Herring /* SPI pinmux */ 435*724ba675SRob Herring spi1_mosi_px4 { 436*724ba675SRob Herring nvidia,pins = "spi1_mosi_px4", 437*724ba675SRob Herring "spi1_sck_px5", 438*724ba675SRob Herring "spi1_cs0_n_px6", 439*724ba675SRob Herring "spi1_miso_px7"; 440*724ba675SRob Herring nvidia,function = "spi1"; 441*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 442*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 443*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 444*724ba675SRob Herring }; 445*724ba675SRob Herring 446*724ba675SRob Herring spi2_cs1_n_pw2 { 447*724ba675SRob Herring nvidia,pins = "spi2_cs1_n_pw2", 448*724ba675SRob Herring "spi2_cs2_n_pw3"; 449*724ba675SRob Herring nvidia,function = "spi2"; 450*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 451*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 452*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 453*724ba675SRob Herring }; 454*724ba675SRob Herring 455*724ba675SRob Herring spi2_sck_px2 { 456*724ba675SRob Herring nvidia,pins = "spi2_sck_px2"; 457*724ba675SRob Herring nvidia,function = "gmi"; 458*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 459*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 460*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring gmi_a16_pj7 { 464*724ba675SRob Herring nvidia,pins = "gmi_a16_pj7", 465*724ba675SRob Herring "gmi_a19_pk7"; 466*724ba675SRob Herring nvidia,function = "spi4"; 467*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 468*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 469*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 470*724ba675SRob Herring }; 471*724ba675SRob Herring 472*724ba675SRob Herring gmi_a17_pb0 { 473*724ba675SRob Herring nvidia,pins = "gmi_a17_pb0", 474*724ba675SRob Herring "gmi_a18_pb1"; 475*724ba675SRob Herring nvidia,function = "spi4"; 476*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 477*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 478*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 479*724ba675SRob Herring }; 480*724ba675SRob Herring 481*724ba675SRob Herring spi2_mosi_px0 { 482*724ba675SRob Herring nvidia,pins = "spi2_mosi_px0"; 483*724ba675SRob Herring nvidia,function = "spi6"; 484*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 485*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 486*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 487*724ba675SRob Herring }; 488*724ba675SRob Herring 489*724ba675SRob Herring spdif_out_pk5 { 490*724ba675SRob Herring nvidia,pins = "spdif_out_pk5"; 491*724ba675SRob Herring nvidia,function = "spdif"; 492*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 493*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 494*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 495*724ba675SRob Herring }; 496*724ba675SRob Herring 497*724ba675SRob Herring spdif_in_pk6 { 498*724ba675SRob Herring nvidia,pins = "spdif_in_pk6"; 499*724ba675SRob Herring nvidia,function = "spdif"; 500*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 501*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 502*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 503*724ba675SRob Herring }; 504*724ba675SRob Herring 505*724ba675SRob Herring /* Display A pinmux */ 506*724ba675SRob Herring lcd_pwr0_pb2 { 507*724ba675SRob Herring nvidia,pins = "lcd_pwr0_pb2", 508*724ba675SRob Herring "lcd_pclk_pb3", 509*724ba675SRob Herring "lcd_pwr1_pc1", 510*724ba675SRob Herring "lcd_pwr2_pc6", 511*724ba675SRob Herring "lcd_d0_pe0", 512*724ba675SRob Herring "lcd_d1_pe1", 513*724ba675SRob Herring "lcd_d2_pe2", 514*724ba675SRob Herring "lcd_d3_pe3", 515*724ba675SRob Herring "lcd_d4_pe4", 516*724ba675SRob Herring "lcd_d5_pe5", 517*724ba675SRob Herring "lcd_d6_pe6", 518*724ba675SRob Herring "lcd_d7_pe7", 519*724ba675SRob Herring "lcd_d8_pf0", 520*724ba675SRob Herring "lcd_d9_pf1", 521*724ba675SRob Herring "lcd_d10_pf2", 522*724ba675SRob Herring "lcd_d11_pf3", 523*724ba675SRob Herring "lcd_d12_pf4", 524*724ba675SRob Herring "lcd_d13_pf5", 525*724ba675SRob Herring "lcd_d14_pf6", 526*724ba675SRob Herring "lcd_d15_pf7", 527*724ba675SRob Herring "lcd_de_pj1", 528*724ba675SRob Herring "lcd_hsync_pj3", 529*724ba675SRob Herring "lcd_vsync_pj4", 530*724ba675SRob Herring "lcd_d16_pm0", 531*724ba675SRob Herring "lcd_d17_pm1", 532*724ba675SRob Herring "lcd_d18_pm2", 533*724ba675SRob Herring "lcd_d19_pm3", 534*724ba675SRob Herring "lcd_d20_pm4", 535*724ba675SRob Herring "lcd_d21_pm5", 536*724ba675SRob Herring "lcd_d22_pm6", 537*724ba675SRob Herring "lcd_d23_pm7", 538*724ba675SRob Herring "lcd_cs0_n_pn4", 539*724ba675SRob Herring "lcd_sdout_pn5", 540*724ba675SRob Herring "lcd_dc0_pn6", 541*724ba675SRob Herring "lcd_sdin_pz2", 542*724ba675SRob Herring "lcd_wr_n_pz3", 543*724ba675SRob Herring "lcd_sck_pz4", 544*724ba675SRob Herring "lcd_cs1_n_pw0", 545*724ba675SRob Herring "lcd_m1_pw1"; 546*724ba675SRob Herring nvidia,function = "displaya"; 547*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 548*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 549*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 550*724ba675SRob Herring }; 551*724ba675SRob Herring 552*724ba675SRob Herring lcd_dc1_pd2 { 553*724ba675SRob Herring nvidia,pins = "lcd_dc1_pd2"; 554*724ba675SRob Herring nvidia,function = "displaya"; 555*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 556*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 557*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 558*724ba675SRob Herring }; 559*724ba675SRob Herring 560*724ba675SRob Herring clk_32k_out_pa0 { 561*724ba675SRob Herring nvidia,pins = "clk_32k_out_pa0"; 562*724ba675SRob Herring nvidia,function = "blink"; 563*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 564*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 565*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 566*724ba675SRob Herring }; 567*724ba675SRob Herring 568*724ba675SRob Herring /* KBC keys */ 569*724ba675SRob Herring kb_row0_pr0 { 570*724ba675SRob Herring nvidia,pins = "kb_row0_pr0", 571*724ba675SRob Herring "kb_row1_pr1", 572*724ba675SRob Herring "kb_row2_pr2", 573*724ba675SRob Herring "kb_row3_pr3", 574*724ba675SRob Herring "kb_row8_ps0", 575*724ba675SRob Herring "kb_col0_pq0", 576*724ba675SRob Herring "kb_col1_pq1", 577*724ba675SRob Herring "kb_col2_pq2", 578*724ba675SRob Herring "kb_col3_pq3", 579*724ba675SRob Herring "kb_col4_pq4", 580*724ba675SRob Herring "kb_col5_pq5", 581*724ba675SRob Herring "kb_col7_pq7"; 582*724ba675SRob Herring nvidia,function = "kbc"; 583*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 584*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 585*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 586*724ba675SRob Herring }; 587*724ba675SRob Herring 588*724ba675SRob Herring kb_row4_pr4 { 589*724ba675SRob Herring nvidia,pins = "kb_row4_pr4", 590*724ba675SRob Herring "kb_row7_pr7", 591*724ba675SRob Herring "kb_row10_ps2", 592*724ba675SRob Herring "kb_row13_ps5"; 593*724ba675SRob Herring nvidia,function = "kbc"; 594*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 595*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 596*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 597*724ba675SRob Herring }; 598*724ba675SRob Herring 599*724ba675SRob Herring kb_row11_ps3 { 600*724ba675SRob Herring nvidia,pins = "kb_row11_ps3", 601*724ba675SRob Herring "kb_row12_ps4", 602*724ba675SRob Herring "kb_row15_ps7"; 603*724ba675SRob Herring nvidia,function = "kbc"; 604*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 605*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 606*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 607*724ba675SRob Herring }; 608*724ba675SRob Herring 609*724ba675SRob Herring kb_row14_ps6 { 610*724ba675SRob Herring nvidia,pins = "kb_row14_ps6"; 611*724ba675SRob Herring nvidia,function = "kbc"; 612*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 614*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 615*724ba675SRob Herring }; 616*724ba675SRob Herring 617*724ba675SRob Herring gmi_iordy_pi5 { 618*724ba675SRob Herring nvidia,pins = "gmi_iordy_pi5"; 619*724ba675SRob Herring nvidia,function = "rsvd1"; 620*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 621*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 622*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 623*724ba675SRob Herring }; 624*724ba675SRob Herring 625*724ba675SRob Herring vi_pclk_pt0 { 626*724ba675SRob Herring nvidia,pins = "vi_pclk_pt0"; 627*724ba675SRob Herring nvidia,function = "rsvd1"; 628*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 629*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 630*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 631*724ba675SRob Herring nvidia,lock = <0>; 632*724ba675SRob Herring nvidia,io-reset = <0>; 633*724ba675SRob Herring }; 634*724ba675SRob Herring 635*724ba675SRob Herring pu1 { 636*724ba675SRob Herring nvidia,pins = "pu1"; 637*724ba675SRob Herring nvidia,function = "rsvd1"; 638*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 639*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 640*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 641*724ba675SRob Herring }; 642*724ba675SRob Herring 643*724ba675SRob Herring pu2 { 644*724ba675SRob Herring nvidia,pins = "pu2"; 645*724ba675SRob Herring nvidia,function = "rsvd1"; 646*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 647*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 648*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 649*724ba675SRob Herring }; 650*724ba675SRob Herring 651*724ba675SRob Herring pv0 { 652*724ba675SRob Herring nvidia,pins = "pv0"; 653*724ba675SRob Herring nvidia,function = "rsvd1"; 654*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 655*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 656*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 657*724ba675SRob Herring }; 658*724ba675SRob Herring 659*724ba675SRob Herring pv1 { 660*724ba675SRob Herring nvidia,pins = "pv1"; 661*724ba675SRob Herring nvidia,function = "rsvd1"; 662*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 663*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 664*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring pcc1 { 668*724ba675SRob Herring nvidia,pins = "pcc1"; 669*724ba675SRob Herring nvidia,function = "rsvd2"; 670*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 671*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 672*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 673*724ba675SRob Herring }; 674*724ba675SRob Herring 675*724ba675SRob Herring sdmmc4_rst_n_pcc3 { 676*724ba675SRob Herring nvidia,pins = "sdmmc4_rst_n_pcc3"; 677*724ba675SRob Herring nvidia,function = "rsvd2"; 678*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 679*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 680*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 681*724ba675SRob Herring }; 682*724ba675SRob Herring 683*724ba675SRob Herring pv3 { 684*724ba675SRob Herring nvidia,pins = "pv3"; 685*724ba675SRob Herring nvidia,function = "rsvd2"; 686*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 687*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 688*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 689*724ba675SRob Herring }; 690*724ba675SRob Herring 691*724ba675SRob Herring vi_vsync_pd6 { 692*724ba675SRob Herring nvidia,pins = "vi_vsync_pd6", 693*724ba675SRob Herring "vi_hsync_pd7"; 694*724ba675SRob Herring nvidia,function = "rsvd2"; 695*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 696*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 697*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 698*724ba675SRob Herring nvidia,lock = <0>; 699*724ba675SRob Herring nvidia,io-reset = <0>; 700*724ba675SRob Herring }; 701*724ba675SRob Herring 702*724ba675SRob Herring vi_d10_pt2 { 703*724ba675SRob Herring nvidia,pins = "vi_d10_pt2", 704*724ba675SRob Herring "vi_d0_pt4", "pbb0"; 705*724ba675SRob Herring nvidia,function = "rsvd2"; 706*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 707*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 708*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 709*724ba675SRob Herring }; 710*724ba675SRob Herring 711*724ba675SRob Herring vi_d11_pt3 { 712*724ba675SRob Herring nvidia,pins = "vi_d11_pt3"; 713*724ba675SRob Herring nvidia,function = "rsvd2"; 714*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 715*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 716*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 717*724ba675SRob Herring }; 718*724ba675SRob Herring 719*724ba675SRob Herring pu0 { 720*724ba675SRob Herring nvidia,pins = "pu0"; 721*724ba675SRob Herring nvidia,function = "rsvd4"; 722*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 723*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 724*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 725*724ba675SRob Herring }; 726*724ba675SRob Herring 727*724ba675SRob Herring pu3 { 728*724ba675SRob Herring nvidia,pins = "pu3"; 729*724ba675SRob Herring nvidia,function = "rsvd4"; 730*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 731*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 732*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring pu6 { 736*724ba675SRob Herring nvidia,pins = "pu6"; 737*724ba675SRob Herring nvidia,function = "rsvd4"; 738*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 739*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 740*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 741*724ba675SRob Herring }; 742*724ba675SRob Herring 743*724ba675SRob Herring pex_l1_prsnt_n_pdd4 { 744*724ba675SRob Herring nvidia,pins = "pex_l1_prsnt_n_pdd4", 745*724ba675SRob Herring "pex_l1_clkreq_n_pdd6"; 746*724ba675SRob Herring nvidia,function = "rsvd4"; 747*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 748*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 749*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 750*724ba675SRob Herring }; 751*724ba675SRob Herring 752*724ba675SRob Herring gmi_wait_pi7 { 753*724ba675SRob Herring nvidia,pins = "gmi_wait_pi7", 754*724ba675SRob Herring "gmi_cs0_n_pj0", 755*724ba675SRob Herring "gmi_cs1_n_pj2", 756*724ba675SRob Herring "gmi_cs4_n_pk2"; 757*724ba675SRob Herring nvidia,function = "nand"; 758*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 759*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 760*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 761*724ba675SRob Herring }; 762*724ba675SRob Herring 763*724ba675SRob Herring gmi_ad0_pg0 { 764*724ba675SRob Herring nvidia,pins = "gmi_ad0_pg0", 765*724ba675SRob Herring "gmi_ad1_pg1", 766*724ba675SRob Herring "gmi_ad2_pg2", 767*724ba675SRob Herring "gmi_ad3_pg3", 768*724ba675SRob Herring "gmi_ad4_pg4", 769*724ba675SRob Herring "gmi_ad5_pg5", 770*724ba675SRob Herring "gmi_ad6_pg6", 771*724ba675SRob Herring "gmi_ad7_pg7", 772*724ba675SRob Herring "gmi_wr_n_pi0", 773*724ba675SRob Herring "gmi_oe_n_pi1", 774*724ba675SRob Herring "gmi_dqs_pi2", 775*724ba675SRob Herring "gmi_adv_n_pk0", 776*724ba675SRob Herring "gmi_clk_pk1"; 777*724ba675SRob Herring nvidia,function = "nand"; 778*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 779*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 780*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 781*724ba675SRob Herring }; 782*724ba675SRob Herring 783*724ba675SRob Herring gmi_cs2_n_pk3 { 784*724ba675SRob Herring nvidia,pins = "gmi_cs2_n_pk3"; 785*724ba675SRob Herring nvidia,function = "rsvd1"; 786*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 787*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 788*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 789*724ba675SRob Herring }; 790*724ba675SRob Herring 791*724ba675SRob Herring gmi_cs3_n_pk4 { 792*724ba675SRob Herring nvidia,pins = "gmi_cs3_n_pk4"; 793*724ba675SRob Herring nvidia,function = "nand"; 794*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 795*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 796*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring gmi_ad10_ph2 { 800*724ba675SRob Herring nvidia,pins = "gmi_ad10_ph2", 801*724ba675SRob Herring "gmi_ad11_ph3", 802*724ba675SRob Herring "gmi_ad14_ph6"; 803*724ba675SRob Herring nvidia,function = "nand"; 804*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 805*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 806*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 807*724ba675SRob Herring }; 808*724ba675SRob Herring 809*724ba675SRob Herring gmi_ad13_ph5 { 810*724ba675SRob Herring nvidia,pins = "gmi_ad13_ph5", 811*724ba675SRob Herring "gmi_ad12_ph4", 812*724ba675SRob Herring "gmi_cs7_n_pi6"; 813*724ba675SRob Herring nvidia,function = "nand"; 814*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 815*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 816*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 817*724ba675SRob Herring }; 818*724ba675SRob Herring 819*724ba675SRob Herring gmi_rst_n_pi4 { 820*724ba675SRob Herring nvidia,pins = "gmi_rst_n_pi4"; 821*724ba675SRob Herring nvidia,function = "gmi"; 822*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 823*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 824*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 825*724ba675SRob Herring }; 826*724ba675SRob Herring 827*724ba675SRob Herring gmi_ad8_ph0 { 828*724ba675SRob Herring nvidia,pins = "gmi_ad8_ph0"; 829*724ba675SRob Herring nvidia,function = "pwm0"; 830*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 831*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 832*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 833*724ba675SRob Herring }; 834*724ba675SRob Herring 835*724ba675SRob Herring gmi_ad9_ph1 { 836*724ba675SRob Herring nvidia,pins = "gmi_ad9_ph1"; 837*724ba675SRob Herring nvidia,function = "pwm1"; 838*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 839*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 840*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 841*724ba675SRob Herring }; 842*724ba675SRob Herring 843*724ba675SRob Herring gmi_wp_n_pc7 { 844*724ba675SRob Herring nvidia,pins = "gmi_wp_n_pc7"; 845*724ba675SRob Herring nvidia,function = "gmi"; 846*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 847*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 848*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 849*724ba675SRob Herring }; 850*724ba675SRob Herring 851*724ba675SRob Herring gmi_cs6_n_pi3 { 852*724ba675SRob Herring nvidia,pins = "gmi_cs6_n_pi3"; 853*724ba675SRob Herring nvidia,function = "sata"; 854*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 855*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 856*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 857*724ba675SRob Herring }; 858*724ba675SRob Herring 859*724ba675SRob Herring vi_d4_pl2 { 860*724ba675SRob Herring nvidia,pins = "vi_d4_pl2"; 861*724ba675SRob Herring nvidia,function = "vi"; 862*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 863*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 864*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 865*724ba675SRob Herring }; 866*724ba675SRob Herring 867*724ba675SRob Herring vi_d6_pl4 { 868*724ba675SRob Herring nvidia,pins = "vi_d6_pl4"; 869*724ba675SRob Herring nvidia,function = "vi"; 870*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 871*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 872*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 873*724ba675SRob Herring nvidia,lock = <0>; 874*724ba675SRob Herring nvidia,io-reset = <0>; 875*724ba675SRob Herring }; 876*724ba675SRob Herring 877*724ba675SRob Herring vi_mclk_pt1 { 878*724ba675SRob Herring nvidia,pins = "vi_mclk_pt1"; 879*724ba675SRob Herring nvidia,function = "vi"; 880*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 881*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 882*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 883*724ba675SRob Herring }; 884*724ba675SRob Herring 885*724ba675SRob Herring /* HDMI hot-plug-detect */ 886*724ba675SRob Herring hdmi_int_pn7 { 887*724ba675SRob Herring nvidia,pins = "hdmi_int_pn7"; 888*724ba675SRob Herring nvidia,function = "hdmi"; 889*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 890*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 891*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 892*724ba675SRob Herring }; 893*724ba675SRob Herring 894*724ba675SRob Herring pu4 { 895*724ba675SRob Herring nvidia,pins = "pu4"; 896*724ba675SRob Herring nvidia,function = "pwm1"; 897*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 898*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 899*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 900*724ba675SRob Herring }; 901*724ba675SRob Herring 902*724ba675SRob Herring pu5 { 903*724ba675SRob Herring nvidia,pins = "pu5"; 904*724ba675SRob Herring nvidia,function = "pwm2"; 905*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 906*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 907*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 908*724ba675SRob Herring }; 909*724ba675SRob Herring 910*724ba675SRob Herring jtag_rtck_pu7 { 911*724ba675SRob Herring nvidia,pins = "jtag_rtck_pu7"; 912*724ba675SRob Herring nvidia,function = "rtck"; 913*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 914*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 915*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 916*724ba675SRob Herring }; 917*724ba675SRob Herring 918*724ba675SRob Herring crt_hsync_pv6 { 919*724ba675SRob Herring nvidia,pins = "crt_hsync_pv6", 920*724ba675SRob Herring "crt_vsync_pv7"; 921*724ba675SRob Herring nvidia,function = "crt"; 922*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 923*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 924*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 925*724ba675SRob Herring }; 926*724ba675SRob Herring 927*724ba675SRob Herring clk1_out_pw4 { 928*724ba675SRob Herring nvidia,pins = "clk1_out_pw4"; 929*724ba675SRob Herring nvidia,function = "extperiph1"; 930*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 931*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 932*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 933*724ba675SRob Herring }; 934*724ba675SRob Herring 935*724ba675SRob Herring clk2_out_pw5 { 936*724ba675SRob Herring nvidia,pins = "clk2_out_pw5"; 937*724ba675SRob Herring nvidia,function = "extperiph2"; 938*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 939*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 940*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 941*724ba675SRob Herring }; 942*724ba675SRob Herring 943*724ba675SRob Herring clk3_out_pee0 { 944*724ba675SRob Herring nvidia,pins = "clk3_out_pee0"; 945*724ba675SRob Herring nvidia,function = "extperiph3"; 946*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 947*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 948*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 949*724ba675SRob Herring }; 950*724ba675SRob Herring 951*724ba675SRob Herring sys_clk_req_pz5 { 952*724ba675SRob Herring nvidia,pins = "sys_clk_req_pz5"; 953*724ba675SRob Herring nvidia,function = "sysclk"; 954*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 955*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 956*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 957*724ba675SRob Herring }; 958*724ba675SRob Herring 959*724ba675SRob Herring pbb4 { 960*724ba675SRob Herring nvidia,pins = "pbb4"; 961*724ba675SRob Herring nvidia,function = "vgp4"; 962*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 963*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 964*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 965*724ba675SRob Herring }; 966*724ba675SRob Herring 967*724ba675SRob Herring pbb5 { 968*724ba675SRob Herring nvidia,pins = "pbb5"; 969*724ba675SRob Herring nvidia,function = "vgp5"; 970*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 971*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 972*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 973*724ba675SRob Herring }; 974*724ba675SRob Herring 975*724ba675SRob Herring pbb6 { 976*724ba675SRob Herring nvidia,pins = "pbb6"; 977*724ba675SRob Herring nvidia,function = "vgp6"; 978*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 979*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 980*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 981*724ba675SRob Herring }; 982*724ba675SRob Herring 983*724ba675SRob Herring clk1_req_pee2 { 984*724ba675SRob Herring nvidia,pins = "clk1_req_pee2"; 985*724ba675SRob Herring nvidia,function = "dap"; 986*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 987*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 988*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 989*724ba675SRob Herring }; 990*724ba675SRob Herring 991*724ba675SRob Herring clk2_req_pcc5 { 992*724ba675SRob Herring nvidia,pins = "clk2_req_pcc5"; 993*724ba675SRob Herring nvidia,function = "dap"; 994*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 995*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 996*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 997*724ba675SRob Herring }; 998*724ba675SRob Herring 999*724ba675SRob Herring clk3_req_pee1 { 1000*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 1001*724ba675SRob Herring nvidia,function = "dev3"; 1002*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1003*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1004*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1005*724ba675SRob Herring }; 1006*724ba675SRob Herring 1007*724ba675SRob Herring owr { 1008*724ba675SRob Herring nvidia,pins = "owr"; 1009*724ba675SRob Herring nvidia,function = "owr"; 1010*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1011*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1012*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1013*724ba675SRob Herring }; 1014*724ba675SRob Herring 1015*724ba675SRob Herring pv2 { 1016*724ba675SRob Herring nvidia,pins = "pv2", 1017*724ba675SRob Herring "kb_row5_pr5"; 1018*724ba675SRob Herring nvidia,function = "owr"; 1019*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1020*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1021*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1022*724ba675SRob Herring }; 1023*724ba675SRob Herring 1024*724ba675SRob Herring pbb3 { 1025*724ba675SRob Herring nvidia,pins = "pbb3"; 1026*724ba675SRob Herring nvidia,function = "vgp3"; 1027*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1028*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1029*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1030*724ba675SRob Herring }; 1031*724ba675SRob Herring 1032*724ba675SRob Herring pbb7 { 1033*724ba675SRob Herring nvidia,pins = "pbb7"; 1034*724ba675SRob Herring nvidia,function = "i2s4"; 1035*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1036*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1037*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1038*724ba675SRob Herring }; 1039*724ba675SRob Herring 1040*724ba675SRob Herring cam_mclk_pcc0 { 1041*724ba675SRob Herring nvidia,pins = "cam_mclk_pcc0"; 1042*724ba675SRob Herring nvidia,function = "vi_alt3"; 1043*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 1044*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 1045*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1046*724ba675SRob Herring }; 1047*724ba675SRob Herring 1048*724ba675SRob Herring /* GPIO power/drive control */ 1049*724ba675SRob Herring drive_dap1 { 1050*724ba675SRob Herring nvidia,pins = "drive_dap1", 1051*724ba675SRob Herring "drive_dap2", 1052*724ba675SRob Herring "drive_dbg", 1053*724ba675SRob Herring "drive_at5", 1054*724ba675SRob Herring "drive_gme", 1055*724ba675SRob Herring "drive_ddc", 1056*724ba675SRob Herring "drive_ao1", 1057*724ba675SRob Herring "drive_uart3"; 1058*724ba675SRob Herring nvidia,high-speed-mode = <0>; 1059*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_ENABLE>; 1060*724ba675SRob Herring nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 1061*724ba675SRob Herring nvidia,pull-down-strength = <31>; 1062*724ba675SRob Herring nvidia,pull-up-strength = <31>; 1063*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1064*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring 1067*724ba675SRob Herring drive_sdio1 { 1068*724ba675SRob Herring nvidia,pins = "drive_sdio1"; 1069*724ba675SRob Herring nvidia,high-speed-mode = <0>; 1070*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1071*724ba675SRob Herring nvidia,pull-down-strength = <5>; 1072*724ba675SRob Herring nvidia,pull-up-strength = <5>; 1073*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 1074*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 1075*724ba675SRob Herring }; 1076*724ba675SRob Herring 1077*724ba675SRob Herring drive_sdio3 { 1078*724ba675SRob Herring nvidia,pins = "drive_sdio3"; 1079*724ba675SRob Herring nvidia,high-speed-mode = <0>; 1080*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1081*724ba675SRob Herring nvidia,pull-down-strength = <46>; 1082*724ba675SRob Herring nvidia,pull-up-strength = <42>; 1083*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 1084*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 1085*724ba675SRob Herring }; 1086*724ba675SRob Herring 1087*724ba675SRob Herring drive_gma { 1088*724ba675SRob Herring nvidia,pins = "drive_gma", 1089*724ba675SRob Herring "drive_gmb", 1090*724ba675SRob Herring "drive_gmc", 1091*724ba675SRob Herring "drive_gmd"; 1092*724ba675SRob Herring nvidia,pull-down-strength = <9>; 1093*724ba675SRob Herring nvidia,pull-up-strength = <9>; 1094*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 1095*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 1096*724ba675SRob Herring }; 1097*724ba675SRob Herring 1098*724ba675SRob Herring drive_lcd2 { 1099*724ba675SRob Herring nvidia,pins = "drive_lcd2"; 1100*724ba675SRob Herring nvidia,high-speed-mode = <0>; 1101*724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_ENABLE>; 1102*724ba675SRob Herring nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; 1103*724ba675SRob Herring nvidia,pull-down-strength = <20>; 1104*724ba675SRob Herring nvidia,pull-up-strength = <20>; 1105*724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1106*724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1107*724ba675SRob Herring }; 1108*724ba675SRob Herring }; 1109*724ba675SRob Herring }; 1110*724ba675SRob Herring 1111*724ba675SRob Herring uartb: serial@70006040 { 1112*724ba675SRob Herring compatible = "nvidia,tegra30-hsuart"; 1113*724ba675SRob Herring /delete-property/ reg-shift; 1114*724ba675SRob Herring status = "okay"; 1115*724ba675SRob Herring 1116*724ba675SRob Herring /* Broadcom GPS BCM47511 */ 1117*724ba675SRob Herring }; 1118*724ba675SRob Herring 1119*724ba675SRob Herring uartc: serial@70006200 { 1120*724ba675SRob Herring compatible = "nvidia,tegra30-hsuart"; 1121*724ba675SRob Herring /delete-property/ reg-shift; 1122*724ba675SRob Herring status = "okay"; 1123*724ba675SRob Herring 1124*724ba675SRob Herring nvidia,adjust-baud-rates = <0 9600 100>, 1125*724ba675SRob Herring <9600 115200 200>, 1126*724ba675SRob Herring <1000000 4000000 136>; 1127*724ba675SRob Herring 1128*724ba675SRob Herring /* Azurewave AW-AH663 BCM4330B1 */ 1129*724ba675SRob Herring bluetooth { 1130*724ba675SRob Herring compatible = "brcm,bcm4330-bt"; 1131*724ba675SRob Herring max-speed = <4000000>; 1132*724ba675SRob Herring 1133*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1134*724ba675SRob Herring clock-names = "txco"; 1135*724ba675SRob Herring 1136*724ba675SRob Herring interrupt-parent = <&gpio>; 1137*724ba675SRob Herring interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 1138*724ba675SRob Herring interrupt-names = "host-wakeup"; 1139*724ba675SRob Herring 1140*724ba675SRob Herring device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 1141*724ba675SRob Herring shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 1142*724ba675SRob Herring 1143*724ba675SRob Herring vbat-supply = <&vdd_3v3_sys>; 1144*724ba675SRob Herring vddio-supply = <&vdd_1v8_vio>; 1145*724ba675SRob Herring }; 1146*724ba675SRob Herring }; 1147*724ba675SRob Herring 1148*724ba675SRob Herring pwm: pwm@7000a000 { 1149*724ba675SRob Herring status = "okay"; 1150*724ba675SRob Herring }; 1151*724ba675SRob Herring 1152*724ba675SRob Herring lcd_ddc: i2c@7000c000 { 1153*724ba675SRob Herring status = "okay"; 1154*724ba675SRob Herring clock-frequency = <400000>; 1155*724ba675SRob Herring 1156*724ba675SRob Herring /* Wolfson Microelectronics WM8903 audio codec */ 1157*724ba675SRob Herring wm8903: audio-codec@1a { 1158*724ba675SRob Herring compatible = "wlf,wm8903"; 1159*724ba675SRob Herring reg = <0x1a>; 1160*724ba675SRob Herring 1161*724ba675SRob Herring interrupt-parent = <&gpio>; 1162*724ba675SRob Herring interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_BOTH>; 1163*724ba675SRob Herring 1164*724ba675SRob Herring gpio-controller; 1165*724ba675SRob Herring #gpio-cells = <2>; 1166*724ba675SRob Herring 1167*724ba675SRob Herring micdet-cfg = <0>; 1168*724ba675SRob Herring micdet-delay = <100>; 1169*724ba675SRob Herring 1170*724ba675SRob Herring gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 1171*724ba675SRob Herring 1172*724ba675SRob Herring AVDD-supply = <&vdd_1v8_vio>; 1173*724ba675SRob Herring CPVDD-supply = <&vdd_1v8_vio>; 1174*724ba675SRob Herring DBVDD-supply = <&vdd_1v8_vio>; 1175*724ba675SRob Herring DCVDD-supply = <&vdd_1v8_vio>; 1176*724ba675SRob Herring }; 1177*724ba675SRob Herring }; 1178*724ba675SRob Herring 1179*724ba675SRob Herring i2c2: i2c@7000c400 { 1180*724ba675SRob Herring status = "okay"; 1181*724ba675SRob Herring clock-frequency = <400000>; 1182*724ba675SRob Herring 1183*724ba675SRob Herring /* Atmel touchscreen */ 1184*724ba675SRob Herring touchscreen@4d { 1185*724ba675SRob Herring compatible = "atmel,maxtouch"; 1186*724ba675SRob Herring reg = <0x4d>; 1187*724ba675SRob Herring 1188*724ba675SRob Herring interrupt-parent = <&gpio>; 1189*724ba675SRob Herring interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; 1190*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 1191*724ba675SRob Herring 1192*724ba675SRob Herring vdda-supply = <&vdd_3v3_sys>; 1193*724ba675SRob Herring vdd-supply = <&vdd_3v3_sys>; 1194*724ba675SRob Herring }; 1195*724ba675SRob Herring }; 1196*724ba675SRob Herring 1197*724ba675SRob Herring i2c3: i2c@7000c500 { 1198*724ba675SRob Herring status = "okay"; 1199*724ba675SRob Herring clock-frequency = <400000>; 1200*724ba675SRob Herring 1201*724ba675SRob Herring /* AsahiKASEI AK8975 magnetometer sensor */ 1202*724ba675SRob Herring magnetometer@c { 1203*724ba675SRob Herring compatible = "asahi-kasei,ak8975"; 1204*724ba675SRob Herring reg = <0x0c>; 1205*724ba675SRob Herring 1206*724ba675SRob Herring vdd-supply = <&vdd_3v3_sen>; 1207*724ba675SRob Herring vid-supply = <&vdd_1v8_vio>; 1208*724ba675SRob Herring 1209*724ba675SRob Herring mount-matrix = "0", "1", "0", 1210*724ba675SRob Herring "1", "0", "0", 1211*724ba675SRob Herring "0", "0", "-1"; 1212*724ba675SRob Herring }; 1213*724ba675SRob Herring 1214*724ba675SRob Herring light-sensor@44 { 1215*724ba675SRob Herring compatible = "isil,isl29023"; 1216*724ba675SRob Herring reg = <0x44>; 1217*724ba675SRob Herring 1218*724ba675SRob Herring interrupt-parent = <&gpio>; 1219*724ba675SRob Herring interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>; 1220*724ba675SRob Herring 1221*724ba675SRob Herring vcc-supply = <&vdd_3v3_sen>; 1222*724ba675SRob Herring }; 1223*724ba675SRob Herring 1224*724ba675SRob Herring gyroscope@68 { 1225*724ba675SRob Herring compatible = "invensense,mpu3050"; 1226*724ba675SRob Herring reg = <0x68>; 1227*724ba675SRob Herring 1228*724ba675SRob Herring interrupt-parent = <&gpio>; 1229*724ba675SRob Herring interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 1230*724ba675SRob Herring 1231*724ba675SRob Herring vdd-supply = <&vdd_3v3_sen>; 1232*724ba675SRob Herring vlogic-supply = <&vdd_1v8_vio>; 1233*724ba675SRob Herring 1234*724ba675SRob Herring mount-matrix = "0", "1", "0", 1235*724ba675SRob Herring "1", "0", "0", 1236*724ba675SRob Herring "0", "0", "-1"; 1237*724ba675SRob Herring 1238*724ba675SRob Herring /* External I2C interface */ 1239*724ba675SRob Herring i2c-gate { 1240*724ba675SRob Herring #address-cells = <1>; 1241*724ba675SRob Herring #size-cells = <0>; 1242*724ba675SRob Herring 1243*724ba675SRob Herring accelerometer@f { 1244*724ba675SRob Herring compatible = "kionix,kxtf9"; 1245*724ba675SRob Herring reg = <0x0f>; 1246*724ba675SRob Herring 1247*724ba675SRob Herring interrupt-parent = <&gpio>; 1248*724ba675SRob Herring interrupts = <TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_RISING>; 1249*724ba675SRob Herring 1250*724ba675SRob Herring vdd-supply = <&vdd_1v8_vio>; 1251*724ba675SRob Herring vddio-supply = <&vdd_1v8_vio>; 1252*724ba675SRob Herring 1253*724ba675SRob Herring mount-matrix = "-1", "0", "0", 1254*724ba675SRob Herring "0", "1", "0", 1255*724ba675SRob Herring "0", "0", "1"; 1256*724ba675SRob Herring }; 1257*724ba675SRob Herring }; 1258*724ba675SRob Herring }; 1259*724ba675SRob Herring }; 1260*724ba675SRob Herring 1261*724ba675SRob Herring hdmi_ddc: i2c@7000c700 { 1262*724ba675SRob Herring status = "okay"; 1263*724ba675SRob Herring clock-frequency = <93750>; 1264*724ba675SRob Herring }; 1265*724ba675SRob Herring 1266*724ba675SRob Herring i2c5: i2c@7000d000 { 1267*724ba675SRob Herring status = "okay"; 1268*724ba675SRob Herring clock-frequency = <400000>; 1269*724ba675SRob Herring 1270*724ba675SRob Herring /* Texas Instruments TPS659110 PMIC */ 1271*724ba675SRob Herring pmic: pmic@2d { 1272*724ba675SRob Herring compatible = "ti,tps65911"; 1273*724ba675SRob Herring reg = <0x2d>; 1274*724ba675SRob Herring 1275*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1276*724ba675SRob Herring #interrupt-cells = <2>; 1277*724ba675SRob Herring interrupt-controller; 1278*724ba675SRob Herring wakeup-source; 1279*724ba675SRob Herring 1280*724ba675SRob Herring ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; 1281*724ba675SRob Herring ti,system-power-controller; 1282*724ba675SRob Herring ti,sleep-keep-ck32k; 1283*724ba675SRob Herring ti,sleep-enable; 1284*724ba675SRob Herring 1285*724ba675SRob Herring #gpio-cells = <2>; 1286*724ba675SRob Herring gpio-controller; 1287*724ba675SRob Herring 1288*724ba675SRob Herring vcc1-supply = <&vdd_5v0_sys>; 1289*724ba675SRob Herring vcc2-supply = <&vdd_5v0_sys>; 1290*724ba675SRob Herring vcc3-supply = <&vdd_1v8_vio>; 1291*724ba675SRob Herring vcc4-supply = <&vdd_1v8_vio>; 1292*724ba675SRob Herring vcc5-supply = <&vdd_5v0_sys>; 1293*724ba675SRob Herring vcc6-supply = <&vddio_1v2_ddr>; 1294*724ba675SRob Herring vcc7-supply = <&vdd_5v0_sys>; 1295*724ba675SRob Herring vccio-supply = <&vdd_5v0_sys>; 1296*724ba675SRob Herring 1297*724ba675SRob Herring pmic-sleep-hog { 1298*724ba675SRob Herring gpio-hog; 1299*724ba675SRob Herring gpios = <0 GPIO_ACTIVE_HIGH>, 1300*724ba675SRob Herring <2 GPIO_ACTIVE_HIGH>, 1301*724ba675SRob Herring <6 GPIO_ACTIVE_HIGH>, 1302*724ba675SRob Herring <8 GPIO_ACTIVE_HIGH>; 1303*724ba675SRob Herring output-high; 1304*724ba675SRob Herring }; 1305*724ba675SRob Herring 1306*724ba675SRob Herring regulators { 1307*724ba675SRob Herring /* VDD1 is not used by Chagall */ 1308*724ba675SRob Herring 1309*724ba675SRob Herring vddio_1v2_ddr: vdd2 { 1310*724ba675SRob Herring regulator-name = "vddio_1v2_ddr"; 1311*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1312*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1313*724ba675SRob Herring regulator-always-on; 1314*724ba675SRob Herring regulator-boot-on; 1315*724ba675SRob Herring }; 1316*724ba675SRob Herring 1317*724ba675SRob Herring vdd_cpu: vddctrl { 1318*724ba675SRob Herring regulator-name = "vdd_cpu,vdd_sys"; 1319*724ba675SRob Herring regulator-min-microvolt = <600000>; 1320*724ba675SRob Herring regulator-max-microvolt = <1400000>; 1321*724ba675SRob Herring regulator-coupled-with = <&vdd_core>; 1322*724ba675SRob Herring regulator-coupled-max-spread = <300000>; 1323*724ba675SRob Herring regulator-max-step-microvolt = <100000>; 1324*724ba675SRob Herring regulator-always-on; 1325*724ba675SRob Herring regulator-boot-on; 1326*724ba675SRob Herring ti,regulator-ext-sleep-control = <1>; 1327*724ba675SRob Herring 1328*724ba675SRob Herring nvidia,tegra-cpu-regulator; 1329*724ba675SRob Herring }; 1330*724ba675SRob Herring 1331*724ba675SRob Herring vdd_1v8_vio: vio { 1332*724ba675SRob Herring regulator-name = "vdd_1v8_gen"; 1333*724ba675SRob Herring /* FIXME: eMMC won't work, if set to 1.8 V */ 1334*724ba675SRob Herring regulator-min-microvolt = <1500000>; 1335*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1336*724ba675SRob Herring regulator-always-on; 1337*724ba675SRob Herring regulator-boot-on; 1338*724ba675SRob Herring }; 1339*724ba675SRob Herring 1340*724ba675SRob Herring /* eMMC VDD */ 1341*724ba675SRob Herring vcore_emmc: ldo1 { 1342*724ba675SRob Herring regulator-name = "vdd_emmc_core"; 1343*724ba675SRob Herring regulator-min-microvolt = <1000000>; 1344*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1345*724ba675SRob Herring regulator-always-on; 1346*724ba675SRob Herring }; 1347*724ba675SRob Herring 1348*724ba675SRob Herring /* uSD slot VDD */ 1349*724ba675SRob Herring vdd_usd: ldo2 { 1350*724ba675SRob Herring regulator-name = "vdd_usd"; 1351*724ba675SRob Herring regulator-min-microvolt = <3200000>; 1352*724ba675SRob Herring regulator-max-microvolt = <3200000>; 1353*724ba675SRob Herring }; 1354*724ba675SRob Herring 1355*724ba675SRob Herring /* uSD slot VDDIO */ 1356*724ba675SRob Herring vddio_usd: ldo3 { 1357*724ba675SRob Herring regulator-name = "vddio_usd"; 1358*724ba675SRob Herring regulator-min-microvolt = <1900000>; 1359*724ba675SRob Herring regulator-max-microvolt = <3200000>; 1360*724ba675SRob Herring }; 1361*724ba675SRob Herring 1362*724ba675SRob Herring ldo4 { 1363*724ba675SRob Herring regulator-name = "vdd_rtc"; 1364*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1365*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1366*724ba675SRob Herring regulator-always-on; 1367*724ba675SRob Herring }; 1368*724ba675SRob Herring 1369*724ba675SRob Herring ldo5 { 1370*724ba675SRob Herring regulator-name = "vdd_1v3_cam_isp"; 1371*724ba675SRob Herring regulator-min-microvolt = <1300000>; 1372*724ba675SRob Herring regulator-max-microvolt = <1300000>; 1373*724ba675SRob Herring }; 1374*724ba675SRob Herring 1375*724ba675SRob Herring ldo6 { 1376*724ba675SRob Herring regulator-name = "avdd_dsi_csi,pwrdet_mipi"; 1377*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1378*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1379*724ba675SRob Herring }; 1380*724ba675SRob Herring 1381*724ba675SRob Herring ldo7 { 1382*724ba675SRob Herring regulator-name = "vdd_pllm,x,u,a_p_c_s"; 1383*724ba675SRob Herring regulator-min-microvolt = <1200000>; 1384*724ba675SRob Herring regulator-max-microvolt = <1200000>; 1385*724ba675SRob Herring regulator-always-on; 1386*724ba675SRob Herring regulator-boot-on; 1387*724ba675SRob Herring ti,regulator-ext-sleep-control = <8>; 1388*724ba675SRob Herring }; 1389*724ba675SRob Herring 1390*724ba675SRob Herring ldo8 { 1391*724ba675SRob Herring regulator-name = "vdd_ddr_hs"; 1392*724ba675SRob Herring regulator-min-microvolt = <1000000>; 1393*724ba675SRob Herring regulator-max-microvolt = <1000000>; 1394*724ba675SRob Herring regulator-always-on; 1395*724ba675SRob Herring ti,regulator-ext-sleep-control = <8>; 1396*724ba675SRob Herring }; 1397*724ba675SRob Herring }; 1398*724ba675SRob Herring }; 1399*724ba675SRob Herring 1400*724ba675SRob Herring nct72: temperature-sensor@4c { 1401*724ba675SRob Herring compatible = "onnn,nct1008"; 1402*724ba675SRob Herring reg = <0x4c>; 1403*724ba675SRob Herring 1404*724ba675SRob Herring interrupt-parent = <&gpio>; 1405*724ba675SRob Herring interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>; 1406*724ba675SRob Herring 1407*724ba675SRob Herring vcc-supply = <&vdd_3v3_sys>; 1408*724ba675SRob Herring #thermal-sensor-cells = <1>; 1409*724ba675SRob Herring }; 1410*724ba675SRob Herring 1411*724ba675SRob Herring vdd_core: core-regulator@60 { 1412*724ba675SRob Herring compatible = "ti,tps62361"; 1413*724ba675SRob Herring reg = <0x60>; 1414*724ba675SRob Herring 1415*724ba675SRob Herring regulator-name = "tps62361-vout"; 1416*724ba675SRob Herring regulator-min-microvolt = <500000>; 1417*724ba675SRob Herring regulator-max-microvolt = <1770000>; 1418*724ba675SRob Herring regulator-coupled-with = <&vdd_cpu>; 1419*724ba675SRob Herring regulator-coupled-max-spread = <300000>; 1420*724ba675SRob Herring regulator-max-step-microvolt = <100000>; 1421*724ba675SRob Herring regulator-boot-on; 1422*724ba675SRob Herring regulator-always-on; 1423*724ba675SRob Herring ti,enable-vout-discharge; 1424*724ba675SRob Herring ti,vsel0-state-high; 1425*724ba675SRob Herring ti,vsel1-state-high; 1426*724ba675SRob Herring 1427*724ba675SRob Herring nvidia,tegra-core-regulator; 1428*724ba675SRob Herring }; 1429*724ba675SRob Herring }; 1430*724ba675SRob Herring 1431*724ba675SRob Herring vdd_5v0_sys: regulator-5v { 1432*724ba675SRob Herring compatible = "regulator-fixed"; 1433*724ba675SRob Herring regulator-name = "vdd_5v0_sys"; 1434*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1435*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1436*724ba675SRob Herring regulator-always-on; 1437*724ba675SRob Herring regulator-boot-on; 1438*724ba675SRob Herring }; 1439*724ba675SRob Herring 1440*724ba675SRob Herring vdd_3v3_sys: regulator-3v { 1441*724ba675SRob Herring compatible = "regulator-fixed"; 1442*724ba675SRob Herring regulator-name = "vdd_3v3_sys"; 1443*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1444*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1445*724ba675SRob Herring regulator-always-on; 1446*724ba675SRob Herring regulator-boot-on; 1447*724ba675SRob Herring }; 1448*724ba675SRob Herring 1449*724ba675SRob Herring vdd_pnl: regulator-panel { 1450*724ba675SRob Herring compatible = "regulator-fixed"; 1451*724ba675SRob Herring regulator-name = "vdd_panel"; 1452*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1453*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1454*724ba675SRob Herring regulator-enable-ramp-delay = <300000>; 1455*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1456*724ba675SRob Herring enable-active-high; 1457*724ba675SRob Herring vin-supply = <&vdd_3v3_sys>; 1458*724ba675SRob Herring }; 1459*724ba675SRob Herring 1460*724ba675SRob Herring vdd_3v3_sen: regulator-sensors { 1461*724ba675SRob Herring compatible = "regulator-fixed"; 1462*724ba675SRob Herring regulator-name = "sen_3v3_en"; 1463*724ba675SRob Herring regulator-min-microvolt = <3300000>; 1464*724ba675SRob Herring regulator-max-microvolt = <3300000>; 1465*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; 1466*724ba675SRob Herring enable-active-high; 1467*724ba675SRob Herring vin-supply = <&vdd_3v3_sys>; 1468*724ba675SRob Herring }; 1469*724ba675SRob Herring 1470*724ba675SRob Herring vdd_5v0_bl: regulator-bl { 1471*724ba675SRob Herring compatible = "regulator-fixed"; 1472*724ba675SRob Herring regulator-name = "vdd_5v0_bl"; 1473*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1474*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1475*724ba675SRob Herring regulator-boot-on; 1476*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 1477*724ba675SRob Herring enable-active-high; 1478*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1479*724ba675SRob Herring }; 1480*724ba675SRob Herring 1481*724ba675SRob Herring hdmi_5v0_sys: regulator-hdmi { 1482*724ba675SRob Herring compatible = "regulator-fixed"; 1483*724ba675SRob Herring regulator-name = "hdmi_5v0_sys"; 1484*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1485*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1486*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 1487*724ba675SRob Herring enable-active-high; 1488*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1489*724ba675SRob Herring }; 1490*724ba675SRob Herring 1491*724ba675SRob Herring vdd_vbus_usb1: regulator-usb1 { 1492*724ba675SRob Herring compatible = "regulator-fixed"; 1493*724ba675SRob Herring regulator-name = "vdd_vbus_micro_usb"; 1494*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1495*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1496*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; 1497*724ba675SRob Herring enable-active-high; 1498*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1499*724ba675SRob Herring }; 1500*724ba675SRob Herring 1501*724ba675SRob Herring vdd_vbus_usb3: regulator-usb3 { 1502*724ba675SRob Herring compatible = "regulator-fixed"; 1503*724ba675SRob Herring regulator-name = "vdd_vbus_typea_usb"; 1504*724ba675SRob Herring regulator-min-microvolt = <5000000>; 1505*724ba675SRob Herring regulator-max-microvolt = <5000000>; 1506*724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; 1507*724ba675SRob Herring enable-active-high; 1508*724ba675SRob Herring vin-supply = <&vdd_5v0_sys>; 1509*724ba675SRob Herring }; 1510*724ba675SRob Herring 1511*724ba675SRob Herring pmc@7000e400 { 1512*724ba675SRob Herring status = "okay"; 1513*724ba675SRob Herring nvidia,invert-interrupt; 1514*724ba675SRob Herring nvidia,suspend-mode = <2>; 1515*724ba675SRob Herring nvidia,cpu-pwr-good-time = <2000>; 1516*724ba675SRob Herring nvidia,cpu-pwr-off-time = <200>; 1517*724ba675SRob Herring nvidia,core-pwr-good-time = <3845 3845>; 1518*724ba675SRob Herring nvidia,core-pwr-off-time = <0>; 1519*724ba675SRob Herring nvidia,core-power-req-active-high; 1520*724ba675SRob Herring nvidia,sys-clock-req-active-high; 1521*724ba675SRob Herring core-supply = <&vdd_core>; 1522*724ba675SRob Herring 1523*724ba675SRob Herring /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ 1524*724ba675SRob Herring i2c-thermtrip { 1525*724ba675SRob Herring nvidia,i2c-controller-id = <4>; 1526*724ba675SRob Herring nvidia,bus-addr = <0x2d>; 1527*724ba675SRob Herring nvidia,reg-addr = <0x3f>; 1528*724ba675SRob Herring nvidia,reg-data = <0x81>; 1529*724ba675SRob Herring }; 1530*724ba675SRob Herring }; 1531*724ba675SRob Herring 1532*724ba675SRob Herring memory-controller@7000f000 { 1533*724ba675SRob Herring emc-timings-0 { 1534*724ba675SRob Herring /* SAMSUNG K4P8G304EB FGC1 */ 1535*724ba675SRob Herring nvidia,ram-code = <0>; 1536*724ba675SRob Herring 1537*724ba675SRob Herring timing-25500000 { 1538*724ba675SRob Herring clock-frequency = <25500000>; 1539*724ba675SRob Herring 1540*724ba675SRob Herring nvidia,emem-configuration = < 0x00020001 0xc0000010 1541*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1542*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1543*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1544*724ba675SRob Herring 0x02020001 0x00060402 0x73e30303 0x001f0000 >; 1545*724ba675SRob Herring }; 1546*724ba675SRob Herring 1547*724ba675SRob Herring timing-51000000 { 1548*724ba675SRob Herring clock-frequency = <51000000>; 1549*724ba675SRob Herring 1550*724ba675SRob Herring nvidia,emem-configuration = < 0x00010001 0xc0000010 1551*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1552*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1553*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1554*724ba675SRob Herring 0x02020001 0x00060402 0x72c30303 0x001f0000 >; 1555*724ba675SRob Herring }; 1556*724ba675SRob Herring 1557*724ba675SRob Herring timing-102000000 { 1558*724ba675SRob Herring clock-frequency = <102000000>; 1559*724ba675SRob Herring 1560*724ba675SRob Herring nvidia,emem-configuration = < 0x00000001 0xc0000018 1561*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000001 1562*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1563*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1564*724ba675SRob Herring 0x02020001 0x00060403 0x72430504 0x001f0000 >; 1565*724ba675SRob Herring }; 1566*724ba675SRob Herring 1567*724ba675SRob Herring timing-204000000 { 1568*724ba675SRob Herring clock-frequency = <204000000>; 1569*724ba675SRob Herring 1570*724ba675SRob Herring nvidia,emem-configuration = < 0x00000003 0xc0000025 1571*724ba675SRob Herring 0x00000001 0x00000001 0x00000006 0x00000003 1572*724ba675SRob Herring 0x00000005 0x00000001 0x00000002 0x00000004 1573*724ba675SRob Herring 0x00000001 0x00000000 0x00000003 0x00000002 1574*724ba675SRob Herring 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; 1575*724ba675SRob Herring }; 1576*724ba675SRob Herring 1577*724ba675SRob Herring timing-400000000 { 1578*724ba675SRob Herring clock-frequency = <400000000>; 1579*724ba675SRob Herring 1580*724ba675SRob Herring nvidia,emem-configuration = < 0x00000006 0xc0000048 1581*724ba675SRob Herring 0x00000002 0x00000003 0x0000000c 0x00000007 1582*724ba675SRob Herring 0x00000009 0x00000001 0x00000002 0x00000006 1583*724ba675SRob Herring 0x00000001 0x00000000 0x00000004 0x00000004 1584*724ba675SRob Herring 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; 1585*724ba675SRob Herring }; 1586*724ba675SRob Herring }; 1587*724ba675SRob Herring 1588*724ba675SRob Herring emc-timings-1 { 1589*724ba675SRob Herring /* ELPIDA EDB8132B2MA 8D_F */ 1590*724ba675SRob Herring nvidia,ram-code = <1>; 1591*724ba675SRob Herring 1592*724ba675SRob Herring timing-25500000 { 1593*724ba675SRob Herring clock-frequency = <25500000>; 1594*724ba675SRob Herring 1595*724ba675SRob Herring nvidia,emem-configuration = < 0x00020001 0xc0000010 1596*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1597*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1598*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1599*724ba675SRob Herring 0x02020001 0x00060402 0x73e30303 0x001f0000 >; 1600*724ba675SRob Herring }; 1601*724ba675SRob Herring 1602*724ba675SRob Herring timing-51000000 { 1603*724ba675SRob Herring clock-frequency = <51000000>; 1604*724ba675SRob Herring 1605*724ba675SRob Herring nvidia,emem-configuration = < 0x00010001 0xc0000010 1606*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1607*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1608*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1609*724ba675SRob Herring 0x02020001 0x00060402 0x72c30303 0x001f0000 >; 1610*724ba675SRob Herring }; 1611*724ba675SRob Herring 1612*724ba675SRob Herring timing-102000000 { 1613*724ba675SRob Herring clock-frequency = <102000000>; 1614*724ba675SRob Herring 1615*724ba675SRob Herring nvidia,emem-configuration = < 0x00000001 0xc0000018 1616*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000001 1617*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1618*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1619*724ba675SRob Herring 0x02020001 0x00060403 0x72430504 0x001f0000 >; 1620*724ba675SRob Herring }; 1621*724ba675SRob Herring 1622*724ba675SRob Herring timing-204000000 { 1623*724ba675SRob Herring clock-frequency = <204000000>; 1624*724ba675SRob Herring 1625*724ba675SRob Herring nvidia,emem-configuration = < 0x00000003 0xc0000025 1626*724ba675SRob Herring 0x00000001 0x00000001 0x00000006 0x00000003 1627*724ba675SRob Herring 0x00000005 0x00000001 0x00000002 0x00000004 1628*724ba675SRob Herring 0x00000001 0x00000000 0x00000003 0x00000002 1629*724ba675SRob Herring 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; 1630*724ba675SRob Herring }; 1631*724ba675SRob Herring 1632*724ba675SRob Herring timing-400000000 { 1633*724ba675SRob Herring clock-frequency = <400000000>; 1634*724ba675SRob Herring 1635*724ba675SRob Herring nvidia,emem-configuration = < 0x00000006 0xc0000048 1636*724ba675SRob Herring 0x00000002 0x00000003 0x0000000c 0x00000007 1637*724ba675SRob Herring 0x00000009 0x00000001 0x00000002 0x00000006 1638*724ba675SRob Herring 0x00000001 0x00000000 0x00000004 0x00000004 1639*724ba675SRob Herring 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; 1640*724ba675SRob Herring }; 1641*724ba675SRob Herring }; 1642*724ba675SRob Herring 1643*724ba675SRob Herring emc-timings-2 { 1644*724ba675SRob Herring /* SAMSUNG K4P8G304EB FGC2 */ 1645*724ba675SRob Herring nvidia,ram-code = <2>; 1646*724ba675SRob Herring 1647*724ba675SRob Herring timing-25500000 { 1648*724ba675SRob Herring clock-frequency = <25500000>; 1649*724ba675SRob Herring 1650*724ba675SRob Herring nvidia,emem-configuration = < 0x00020001 0xc0000010 1651*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1652*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1653*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1654*724ba675SRob Herring 0x02020001 0x00060402 0x73e30303 0x001f0000 >; 1655*724ba675SRob Herring }; 1656*724ba675SRob Herring 1657*724ba675SRob Herring timing-51000000 { 1658*724ba675SRob Herring clock-frequency = <51000000>; 1659*724ba675SRob Herring 1660*724ba675SRob Herring nvidia,emem-configuration = < 0x00010001 0xc0000010 1661*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1662*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1663*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1664*724ba675SRob Herring 0x02020001 0x00060402 0x72c30303 0x001f0000 >; 1665*724ba675SRob Herring }; 1666*724ba675SRob Herring 1667*724ba675SRob Herring timing-102000000 { 1668*724ba675SRob Herring clock-frequency = <102000000>; 1669*724ba675SRob Herring 1670*724ba675SRob Herring nvidia,emem-configuration = < 0x00000001 0xc0000018 1671*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000001 1672*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1673*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1674*724ba675SRob Herring 0x02020001 0x00060403 0x72430504 0x001f0000 >; 1675*724ba675SRob Herring }; 1676*724ba675SRob Herring 1677*724ba675SRob Herring timing-204000000 { 1678*724ba675SRob Herring clock-frequency = <204000000>; 1679*724ba675SRob Herring 1680*724ba675SRob Herring nvidia,emem-configuration = < 0x00000003 0xc0000025 1681*724ba675SRob Herring 0x00000001 0x00000001 0x00000006 0x00000003 1682*724ba675SRob Herring 0x00000005 0x00000001 0x00000002 0x00000004 1683*724ba675SRob Herring 0x00000001 0x00000000 0x00000003 0x00000002 1684*724ba675SRob Herring 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; 1685*724ba675SRob Herring }; 1686*724ba675SRob Herring 1687*724ba675SRob Herring timing-533000000 { 1688*724ba675SRob Herring clock-frequency = <533000000>; 1689*724ba675SRob Herring 1690*724ba675SRob Herring nvidia,emem-configuration = < 0x00000008 0xc0000060 1691*724ba675SRob Herring 0x00000003 0x00000004 0x00000010 0x0000000a 1692*724ba675SRob Herring 0x0000000d 0x00000002 0x00000002 0x00000008 1693*724ba675SRob Herring 0x00000002 0x00000000 0x00000004 0x00000005 1694*724ba675SRob Herring 0x05040002 0x00110b10 0x70281811 0x001f0000 >; 1695*724ba675SRob Herring }; 1696*724ba675SRob Herring }; 1697*724ba675SRob Herring 1698*724ba675SRob Herring emc-timings-3 { 1699*724ba675SRob Herring /* HYNIX H9TCNNN8JDMMPR NGM */ 1700*724ba675SRob Herring nvidia,ram-code = <3>; 1701*724ba675SRob Herring 1702*724ba675SRob Herring timing-25500000 { 1703*724ba675SRob Herring clock-frequency = <25500000>; 1704*724ba675SRob Herring 1705*724ba675SRob Herring nvidia,emem-configuration = < 0x00020001 0xc0000010 1706*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1707*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1708*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1709*724ba675SRob Herring 0x02020001 0x00060402 0x73e30303 0x001f0000 >; 1710*724ba675SRob Herring }; 1711*724ba675SRob Herring 1712*724ba675SRob Herring timing-51000000 { 1713*724ba675SRob Herring clock-frequency = <51000000>; 1714*724ba675SRob Herring 1715*724ba675SRob Herring nvidia,emem-configuration = < 0x00010001 0xc0000010 1716*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1717*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1718*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1719*724ba675SRob Herring 0x02020001 0x00060402 0x72c30303 0x001f0000 >; 1720*724ba675SRob Herring }; 1721*724ba675SRob Herring 1722*724ba675SRob Herring timing-102000000 { 1723*724ba675SRob Herring clock-frequency = <102000000>; 1724*724ba675SRob Herring 1725*724ba675SRob Herring nvidia,emem-configuration = < 0x00000001 0xc0000018 1726*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000001 1727*724ba675SRob Herring 0x00000003 0x00000001 0x00000002 0x00000004 1728*724ba675SRob Herring 0x00000001 0x00000000 0x00000002 0x00000002 1729*724ba675SRob Herring 0x02020001 0x00060403 0x72430504 0x001f0000 >; 1730*724ba675SRob Herring }; 1731*724ba675SRob Herring 1732*724ba675SRob Herring timing-204000000 { 1733*724ba675SRob Herring clock-frequency = <204000000>; 1734*724ba675SRob Herring 1735*724ba675SRob Herring nvidia,emem-configuration = < 0x00000003 0xc0000025 1736*724ba675SRob Herring 0x00000001 0x00000001 0x00000006 0x00000003 1737*724ba675SRob Herring 0x00000005 0x00000001 0x00000002 0x00000004 1738*724ba675SRob Herring 0x00000001 0x00000000 0x00000003 0x00000002 1739*724ba675SRob Herring 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; 1740*724ba675SRob Herring }; 1741*724ba675SRob Herring 1742*724ba675SRob Herring timing-533000000 { 1743*724ba675SRob Herring clock-frequency = <533000000>; 1744*724ba675SRob Herring 1745*724ba675SRob Herring nvidia,emem-configuration = < 0x00000008 0xc0000060 1746*724ba675SRob Herring 0x00000003 0x00000004 0x00000010 0x0000000a 1747*724ba675SRob Herring 0x0000000d 0x00000002 0x00000002 0x00000008 1748*724ba675SRob Herring 0x00000002 0x00000000 0x00000004 0x00000005 1749*724ba675SRob Herring 0x05040002 0x00110b10 0x70281811 0x001f0000 >; 1750*724ba675SRob Herring }; 1751*724ba675SRob Herring }; 1752*724ba675SRob Herring }; 1753*724ba675SRob Herring 1754*724ba675SRob Herring memory-controller@7000f400 { 1755*724ba675SRob Herring emc-timings-0 { 1756*724ba675SRob Herring /* SAMSUNG K4P8G304EB FGC1 */ 1757*724ba675SRob Herring nvidia,ram-code = <0>; 1758*724ba675SRob Herring 1759*724ba675SRob Herring timing-25500000 { 1760*724ba675SRob Herring clock-frequency = <25500000>; 1761*724ba675SRob Herring 1762*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1763*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 1764*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1765*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1766*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 1767*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1768*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1769*724ba675SRob Herring 1770*724ba675SRob Herring nvidia,emc-configuration = < 0x00000001 1771*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000004 1772*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 1773*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 1774*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 1775*724ba675SRob Herring 0x00000009 0x00000060 0x00000000 0x00000018 1776*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1777*724ba675SRob Herring 0x00000001 0x00000007 0x00000004 0x00000004 1778*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 1779*724ba675SRob Herring 0x00000002 0x0000006b 0x00000004 0x00000004 1780*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 1781*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 1782*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 1783*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 1784*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1785*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1786*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1787*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 1788*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 1789*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 1790*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1791*724ba675SRob Herring 0x0000000a 0x00090009 0xa0f10000 0x00000000 1792*724ba675SRob Herring 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; 1793*724ba675SRob Herring }; 1794*724ba675SRob Herring 1795*724ba675SRob Herring timing-51000000 { 1796*724ba675SRob Herring clock-frequency = <51000000>; 1797*724ba675SRob Herring 1798*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1799*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 1800*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1801*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1802*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 1803*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1804*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1805*724ba675SRob Herring 1806*724ba675SRob Herring nvidia,emc-configuration = < 0x00000003 1807*724ba675SRob Herring 0x00000006 0x00000002 0x00000002 0x00000004 1808*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 1809*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 1810*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 1811*724ba675SRob Herring 0x00000009 0x000000c0 0x00000000 0x00000030 1812*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1813*724ba675SRob Herring 0x00000001 0x00000007 0x00000008 0x00000008 1814*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 1815*724ba675SRob Herring 0x00000002 0x000000d5 0x00000004 0x00000004 1816*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 1817*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 1818*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 1819*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 1820*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1821*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1822*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1823*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 1824*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 1825*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 1826*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1827*724ba675SRob Herring 0x00000013 0x00090009 0xa0f10000 0x00000000 1828*724ba675SRob Herring 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; 1829*724ba675SRob Herring }; 1830*724ba675SRob Herring 1831*724ba675SRob Herring timing-102000000 { 1832*724ba675SRob Herring clock-frequency = <102000000>; 1833*724ba675SRob Herring 1834*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1835*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 1836*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1837*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1838*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x0000000a>; 1839*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1840*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1841*724ba675SRob Herring 1842*724ba675SRob Herring nvidia,emc-configuration = < 0x00000006 1843*724ba675SRob Herring 0x0000000d 0x00000004 0x00000002 0x00000004 1844*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 1845*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 1846*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 1847*724ba675SRob Herring 0x00000009 0x00000181 0x00000000 0x00000060 1848*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1849*724ba675SRob Herring 0x00000001 0x00000007 0x0000000f 0x0000000f 1850*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 1851*724ba675SRob Herring 0x00000002 0x000001a9 0x00000004 0x00000004 1852*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 1853*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 1854*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 1855*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 1856*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1857*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1858*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1859*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 1860*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 1861*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 1862*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1863*724ba675SRob Herring 0x00000025 0x00090009 0xa0f10000 0x00000000 1864*724ba675SRob Herring 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; 1865*724ba675SRob Herring }; 1866*724ba675SRob Herring 1867*724ba675SRob Herring timing-204000000 { 1868*724ba675SRob Herring clock-frequency = <204000000>; 1869*724ba675SRob Herring 1870*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1871*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010042>; 1872*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1873*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1874*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000013>; 1875*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1876*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1877*724ba675SRob Herring 1878*724ba675SRob Herring nvidia,emc-configuration = < 0x0000000c 1879*724ba675SRob Herring 0x0000001a 0x00000008 0x00000003 0x00000005 1880*724ba675SRob Herring 0x00000004 0x00000001 0x00000006 0x00000003 1881*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000000 1882*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000c 1883*724ba675SRob Herring 0x0000000a 0x00000303 0x00000000 0x000000c0 1884*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000000 1885*724ba675SRob Herring 0x00000001 0x00000007 0x0000001d 0x0000001d 1886*724ba675SRob Herring 0x00000004 0x0000000b 0x00000005 0x00000004 1887*724ba675SRob Herring 0x00000002 0x00000351 0x00000004 0x00000006 1888*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x004400a4 1889*724ba675SRob Herring 0x00008000 0x00080000 0x00080000 0x00080000 1890*724ba675SRob Herring 0x00080000 0x00080000 0x00080000 0x00080000 1891*724ba675SRob Herring 0x00080000 0x00000000 0x00000000 0x00000000 1892*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1893*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1894*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1895*724ba675SRob Herring 0x00000000 0x00080000 0x00080000 0x00080000 1896*724ba675SRob Herring 0x00080000 0x000e0220 0x0800201c 0x00000000 1897*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 1898*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1899*724ba675SRob Herring 0x0000004a 0x00090009 0xa0f10000 0x00000000 1900*724ba675SRob Herring 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; 1901*724ba675SRob Herring }; 1902*724ba675SRob Herring 1903*724ba675SRob Herring timing-400000000 { 1904*724ba675SRob Herring clock-frequency = <400000000>; 1905*724ba675SRob Herring 1906*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1907*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010082>; 1908*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020004>; 1909*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1910*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000024>; 1911*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1912*724ba675SRob Herring 1913*724ba675SRob Herring nvidia,emc-configuration = < 0x00000017 1914*724ba675SRob Herring 0x00000033 0x00000010 0x00000007 0x00000007 1915*724ba675SRob Herring 0x00000007 0x00000002 0x0000000a 0x00000007 1916*724ba675SRob Herring 0x00000007 0x00000003 0x00000002 0x00000000 1917*724ba675SRob Herring 0x00000003 0x00000007 0x00000004 0x0000000d 1918*724ba675SRob Herring 0x0000000e 0x000005e9 0x00000000 0x0000017a 1919*724ba675SRob Herring 0x00000002 0x00000002 0x00000007 0x00000000 1920*724ba675SRob Herring 0x00000001 0x0000000c 0x00000038 0x00000038 1921*724ba675SRob Herring 0x00000006 0x00000014 0x00000009 0x00000004 1922*724ba675SRob Herring 0x00000002 0x00000680 0x00000000 0x00000006 1923*724ba675SRob Herring 0x00000000 0x00000000 0x00006282 0x001d0084 1924*724ba675SRob Herring 0x00008000 0x00034000 0x00034000 0x00034000 1925*724ba675SRob Herring 0x00034000 0x00034000 0x00034000 0x00034000 1926*724ba675SRob Herring 0x00034000 0x00000000 0x00000000 0x00000000 1927*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1928*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1929*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1930*724ba675SRob Herring 0x00000000 0x00038000 0x00038000 0x00038000 1931*724ba675SRob Herring 0x00038000 0x00080220 0x0800003d 0x00000000 1932*724ba675SRob Herring 0x77ffc004 0x01f1f408 0x00000000 0x00000007 1933*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1934*724ba675SRob Herring 0x00000090 0x000c000c 0xa0f10404 0x00000000 1935*724ba675SRob Herring 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; 1936*724ba675SRob Herring }; 1937*724ba675SRob Herring }; 1938*724ba675SRob Herring 1939*724ba675SRob Herring emc-timings-1 { 1940*724ba675SRob Herring /* ELPIDA EDB8132B2MA 8D_F */ 1941*724ba675SRob Herring nvidia,ram-code = <1>; 1942*724ba675SRob Herring 1943*724ba675SRob Herring timing-25500000 { 1944*724ba675SRob Herring clock-frequency = <25500000>; 1945*724ba675SRob Herring 1946*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1947*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 1948*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1949*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1950*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 1951*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1952*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1953*724ba675SRob Herring 1954*724ba675SRob Herring nvidia,emc-configuration = < 0x00000001 1955*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000004 1956*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 1957*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 1958*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 1959*724ba675SRob Herring 0x0000000a 0x00000060 0x00000000 0x00000018 1960*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1961*724ba675SRob Herring 0x00000001 0x00000007 0x00000004 0x00000004 1962*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 1963*724ba675SRob Herring 0x00000002 0x0000006b 0x00000004 0x00000004 1964*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 1965*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 1966*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 1967*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 1968*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1969*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1970*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 1971*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 1972*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 1973*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 1974*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 1975*724ba675SRob Herring 0x0000000a 0x00090009 0xa0f10000 0x00000000 1976*724ba675SRob Herring 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; 1977*724ba675SRob Herring }; 1978*724ba675SRob Herring 1979*724ba675SRob Herring timing-51000000 { 1980*724ba675SRob Herring clock-frequency = <51000000>; 1981*724ba675SRob Herring 1982*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 1983*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 1984*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 1985*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 1986*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 1987*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 1988*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 1989*724ba675SRob Herring 1990*724ba675SRob Herring nvidia,emc-configuration = < 0x00000003 1991*724ba675SRob Herring 0x00000006 0x00000002 0x00000002 0x00000004 1992*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 1993*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 1994*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 1995*724ba675SRob Herring 0x0000000a 0x000000c0 0x00000000 0x00000030 1996*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 1997*724ba675SRob Herring 0x00000001 0x00000007 0x00000008 0x00000008 1998*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 1999*724ba675SRob Herring 0x00000002 0x000000d5 0x00000004 0x00000004 2000*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2001*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2002*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2003*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2004*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2005*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2006*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2007*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2008*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2009*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2010*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2011*724ba675SRob Herring 0x00000013 0x00090009 0xa0f10000 0x00000000 2012*724ba675SRob Herring 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; 2013*724ba675SRob Herring }; 2014*724ba675SRob Herring 2015*724ba675SRob Herring timing-102000000 { 2016*724ba675SRob Herring clock-frequency = <102000000>; 2017*724ba675SRob Herring 2018*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2019*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2020*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2021*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2022*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x0000000a>; 2023*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2024*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2025*724ba675SRob Herring 2026*724ba675SRob Herring nvidia,emc-configuration = < 0x00000006 2027*724ba675SRob Herring 0x0000000d 0x00000004 0x00000002 0x00000004 2028*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2029*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2030*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2031*724ba675SRob Herring 0x0000000a 0x00000181 0x00000000 0x00000060 2032*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2033*724ba675SRob Herring 0x00000001 0x00000007 0x0000000f 0x0000000f 2034*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2035*724ba675SRob Herring 0x00000002 0x000001a9 0x00000004 0x00000004 2036*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2037*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2038*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2039*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2040*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2041*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2042*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2043*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2044*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2045*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2046*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2047*724ba675SRob Herring 0x00000025 0x00090009 0xa0f10000 0x00000000 2048*724ba675SRob Herring 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; 2049*724ba675SRob Herring }; 2050*724ba675SRob Herring 2051*724ba675SRob Herring timing-204000000 { 2052*724ba675SRob Herring clock-frequency = <204000000>; 2053*724ba675SRob Herring 2054*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2055*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010042>; 2056*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2057*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2058*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000013>; 2059*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2060*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2061*724ba675SRob Herring 2062*724ba675SRob Herring nvidia,emc-configuration = < 0x0000000c 2063*724ba675SRob Herring 0x0000001a 0x00000008 0x00000003 0x00000005 2064*724ba675SRob Herring 0x00000004 0x00000001 0x00000006 0x00000003 2065*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000000 2066*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000c 2067*724ba675SRob Herring 0x0000000a 0x00000303 0x00000000 0x000000c0 2068*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000000 2069*724ba675SRob Herring 0x00000001 0x00000007 0x0000001d 0x0000001d 2070*724ba675SRob Herring 0x00000004 0x0000000b 0x00000005 0x00000004 2071*724ba675SRob Herring 0x00000002 0x00000351 0x00000004 0x00000006 2072*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x004400a4 2073*724ba675SRob Herring 0x00008000 0x00070000 0x00070000 0x00070000 2074*724ba675SRob Herring 0x00070000 0x00070000 0x00070000 0x00070000 2075*724ba675SRob Herring 0x00070000 0x00000000 0x00000000 0x00000000 2076*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2077*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2078*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2079*724ba675SRob Herring 0x00000000 0x00080000 0x00080000 0x00080000 2080*724ba675SRob Herring 0x00080000 0x000e0220 0x0800201c 0x00000000 2081*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2082*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2083*724ba675SRob Herring 0x0000004a 0x00090009 0xa0f10000 0x00000000 2084*724ba675SRob Herring 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; 2085*724ba675SRob Herring }; 2086*724ba675SRob Herring 2087*724ba675SRob Herring timing-400000000 { 2088*724ba675SRob Herring clock-frequency = <400000000>; 2089*724ba675SRob Herring 2090*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2091*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010082>; 2092*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020004>; 2093*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2094*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000024>; 2095*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2096*724ba675SRob Herring 2097*724ba675SRob Herring nvidia,emc-configuration = < 0x00000017 2098*724ba675SRob Herring 0x00000033 0x00000010 0x00000007 0x00000007 2099*724ba675SRob Herring 0x00000007 0x00000002 0x0000000a 0x00000007 2100*724ba675SRob Herring 0x00000007 0x00000003 0x00000002 0x00000000 2101*724ba675SRob Herring 0x00000003 0x00000007 0x00000004 0x0000000d 2102*724ba675SRob Herring 0x0000000e 0x000005e9 0x00000000 0x0000017a 2103*724ba675SRob Herring 0x00000002 0x00000002 0x00000007 0x00000000 2104*724ba675SRob Herring 0x00000001 0x0000000c 0x00000038 0x00000038 2105*724ba675SRob Herring 0x00000006 0x00000014 0x00000009 0x00000004 2106*724ba675SRob Herring 0x00000002 0x00000680 0x00000000 0x00000004 2107*724ba675SRob Herring 0x00000000 0x00000000 0x00006282 0x001d0084 2108*724ba675SRob Herring 0x00008000 0x00034000 0x00034000 0x00034000 2109*724ba675SRob Herring 0x00034000 0x00034000 0x00034000 0x00034000 2110*724ba675SRob Herring 0x00034000 0x00000000 0x00000000 0x00000000 2111*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2112*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2113*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2114*724ba675SRob Herring 0x00000000 0x00048000 0x00048000 0x00048000 2115*724ba675SRob Herring 0x00048000 0x00060220 0x0800003d 0x00000000 2116*724ba675SRob Herring 0x77ffc004 0x01f1f408 0x00000000 0x00000007 2117*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2118*724ba675SRob Herring 0x00000090 0x000c000c 0xa0f10000 0x00000000 2119*724ba675SRob Herring 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; 2120*724ba675SRob Herring }; 2121*724ba675SRob Herring }; 2122*724ba675SRob Herring 2123*724ba675SRob Herring emc-timings-2 { 2124*724ba675SRob Herring /* SAMSUNG K4P8G304EB FGC2 */ 2125*724ba675SRob Herring nvidia,ram-code = <2>; 2126*724ba675SRob Herring 2127*724ba675SRob Herring timing-25500000 { 2128*724ba675SRob Herring clock-frequency = <25500000>; 2129*724ba675SRob Herring 2130*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2131*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2132*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2133*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2134*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 2135*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2136*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2137*724ba675SRob Herring 2138*724ba675SRob Herring nvidia,emc-configuration = < 0x00000001 2139*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000004 2140*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2141*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2142*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2143*724ba675SRob Herring 0x0000000a 0x00000060 0x00000000 0x00000018 2144*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2145*724ba675SRob Herring 0x00000001 0x00000007 0x00000004 0x00000004 2146*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2147*724ba675SRob Herring 0x00000002 0x0000006b 0x00000004 0x00000004 2148*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2149*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2150*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2151*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2152*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2153*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2154*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2155*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2156*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2157*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2158*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2159*724ba675SRob Herring 0x0000000a 0x00090009 0xa0f10000 0x00000000 2160*724ba675SRob Herring 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; 2161*724ba675SRob Herring }; 2162*724ba675SRob Herring 2163*724ba675SRob Herring timing-51000000 { 2164*724ba675SRob Herring clock-frequency = <51000000>; 2165*724ba675SRob Herring 2166*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2167*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2168*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2169*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2170*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 2171*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2172*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2173*724ba675SRob Herring 2174*724ba675SRob Herring nvidia,emc-configuration = < 0x00000003 2175*724ba675SRob Herring 0x00000006 0x00000002 0x00000002 0x00000004 2176*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2177*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2178*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2179*724ba675SRob Herring 0x0000000a 0x000000c0 0x00000000 0x00000030 2180*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2181*724ba675SRob Herring 0x00000001 0x00000007 0x00000008 0x00000008 2182*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2183*724ba675SRob Herring 0x00000002 0x000000d5 0x00000004 0x00000004 2184*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2185*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2186*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2187*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2188*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2189*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2190*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2191*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2192*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2193*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2194*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2195*724ba675SRob Herring 0x00000013 0x00090009 0xa0f10000 0x00000000 2196*724ba675SRob Herring 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; 2197*724ba675SRob Herring }; 2198*724ba675SRob Herring 2199*724ba675SRob Herring timing-102000000 { 2200*724ba675SRob Herring clock-frequency = <102000000>; 2201*724ba675SRob Herring 2202*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2203*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2204*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2205*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2206*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x0000000a>; 2207*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2208*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2209*724ba675SRob Herring 2210*724ba675SRob Herring nvidia,emc-configuration = < 0x00000006 2211*724ba675SRob Herring 0x0000000d 0x00000004 0x00000002 0x00000004 2212*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2213*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2214*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2215*724ba675SRob Herring 0x00000009 0x00000181 0x00000000 0x00000060 2216*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2217*724ba675SRob Herring 0x00000001 0x00000007 0x0000000f 0x0000000f 2218*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2219*724ba675SRob Herring 0x00000002 0x000001a9 0x00000004 0x00000004 2220*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2221*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2222*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2223*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2224*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2225*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2226*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2227*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2228*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2229*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2230*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2231*724ba675SRob Herring 0x00000025 0x00090009 0xa0f10000 0x00000000 2232*724ba675SRob Herring 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; 2233*724ba675SRob Herring }; 2234*724ba675SRob Herring 2235*724ba675SRob Herring timing-204000000 { 2236*724ba675SRob Herring clock-frequency = <204000000>; 2237*724ba675SRob Herring 2238*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2239*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010042>; 2240*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2241*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2242*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000013>; 2243*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2244*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2245*724ba675SRob Herring 2246*724ba675SRob Herring nvidia,emc-configuration = < 0x0000000c 2247*724ba675SRob Herring 0x0000001a 0x00000008 0x00000003 0x00000005 2248*724ba675SRob Herring 0x00000004 0x00000001 0x00000006 0x00000003 2249*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000000 2250*724ba675SRob Herring 0x00000001 0x00000004 0x00000001 0x0000000c 2251*724ba675SRob Herring 0x0000000a 0x00000303 0x00000000 0x000000c0 2252*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000000 2253*724ba675SRob Herring 0x00000001 0x00000007 0x0000001d 0x0000001d 2254*724ba675SRob Herring 0x00000004 0x0000000b 0x00000005 0x00000004 2255*724ba675SRob Herring 0x00000002 0x00000351 0x00000005 0x00000004 2256*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x004400a4 2257*724ba675SRob Herring 0x00008000 0x00080000 0x00080000 0x00080000 2258*724ba675SRob Herring 0x00080000 0x00080000 0x00080000 0x00080000 2259*724ba675SRob Herring 0x00080000 0x00000000 0x00000000 0x00000000 2260*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2261*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2262*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2263*724ba675SRob Herring 0x00000000 0x00080000 0x00080000 0x00080000 2264*724ba675SRob Herring 0x00080000 0x000e0220 0x0800201c 0x00000000 2265*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2266*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2267*724ba675SRob Herring 0x0000004a 0x00090009 0xa0f10000 0x00000000 2268*724ba675SRob Herring 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; 2269*724ba675SRob Herring }; 2270*724ba675SRob Herring 2271*724ba675SRob Herring timing-533000000 { 2272*724ba675SRob Herring clock-frequency = <533000000>; 2273*724ba675SRob Herring 2274*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2275*724ba675SRob Herring nvidia,emc-mode-1 = <0x000100c2>; 2276*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020006>; 2277*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2278*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000030>; 2279*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2280*724ba675SRob Herring 2281*724ba675SRob Herring nvidia,emc-configuration = < 0x0000001f 2282*724ba675SRob Herring 0x00000045 0x00000016 0x00000009 0x00000008 2283*724ba675SRob Herring 0x00000009 0x00000003 0x0000000d 0x00000009 2284*724ba675SRob Herring 0x00000009 0x00000005 0x00000003 0x00000000 2285*724ba675SRob Herring 0x00000004 0x0000000a 0x00000006 0x0000000d 2286*724ba675SRob Herring 0x00000010 0x000007df 0x00000000 0x000001f7 2287*724ba675SRob Herring 0x00000003 0x00000003 0x00000009 0x00000000 2288*724ba675SRob Herring 0x00000001 0x0000000f 0x0000004b 0x0000004b 2289*724ba675SRob Herring 0x00000008 0x0000001b 0x0000000c 0x00000004 2290*724ba675SRob Herring 0x00000002 0x000008aa 0x00000000 0x00000004 2291*724ba675SRob Herring 0x00000000 0x00000000 0x00006282 0xf0120091 2292*724ba675SRob Herring 0x00008000 0x007f8008 0x007f8008 0x007f8008 2293*724ba675SRob Herring 0x007f8008 0x007f8008 0x007f8008 0x007f8008 2294*724ba675SRob Herring 0x007f8008 0x00000000 0x00000000 0x00000000 2295*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2296*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2297*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2298*724ba675SRob Herring 0x00000000 0x0000000c 0x0000000c 0x0000000c 2299*724ba675SRob Herring 0x0000000c 0x00080220 0x0200003d 0x00000000 2300*724ba675SRob Herring 0x77ffc004 0x01f1f408 0x00000000 0x00000007 2301*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2302*724ba675SRob Herring 0x000000c0 0x000e000e 0xa0f10000 0x00000000 2303*724ba675SRob Herring 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; 2304*724ba675SRob Herring }; 2305*724ba675SRob Herring }; 2306*724ba675SRob Herring 2307*724ba675SRob Herring emc-timings-3 { 2308*724ba675SRob Herring /* HYNIX H9TCNNN8JDMMPR NGM */ 2309*724ba675SRob Herring nvidia,ram-code = <3>; 2310*724ba675SRob Herring 2311*724ba675SRob Herring timing-25500000 { 2312*724ba675SRob Herring clock-frequency = <25500000>; 2313*724ba675SRob Herring 2314*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2315*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2316*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2317*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2318*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 2319*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2320*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2321*724ba675SRob Herring 2322*724ba675SRob Herring nvidia,emc-configuration = < 0x00000001 2323*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000004 2324*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2325*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2326*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2327*724ba675SRob Herring 0x0000000a 0x00000060 0x00000000 0x00000018 2328*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2329*724ba675SRob Herring 0x00000001 0x00000007 0x00000004 0x00000004 2330*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2331*724ba675SRob Herring 0x00000002 0x0000006b 0x00000004 0x00000004 2332*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2333*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2334*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2335*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2336*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2337*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2338*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2339*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2340*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2341*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2342*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2343*724ba675SRob Herring 0x0000000a 0x00090009 0xa0f10000 0x00000000 2344*724ba675SRob Herring 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; 2345*724ba675SRob Herring }; 2346*724ba675SRob Herring 2347*724ba675SRob Herring timing-51000000 { 2348*724ba675SRob Herring clock-frequency = <51000000>; 2349*724ba675SRob Herring 2350*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2351*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2352*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2353*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2354*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000009>; 2355*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2356*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2357*724ba675SRob Herring 2358*724ba675SRob Herring nvidia,emc-configuration = < 0x00000003 2359*724ba675SRob Herring 0x00000006 0x00000002 0x00000002 0x00000004 2360*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2361*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2362*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2363*724ba675SRob Herring 0x0000000a 0x000000c0 0x00000000 0x00000030 2364*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2365*724ba675SRob Herring 0x00000001 0x00000007 0x00000008 0x00000008 2366*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2367*724ba675SRob Herring 0x00000002 0x000000d5 0x00000004 0x00000004 2368*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2369*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2370*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2371*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2372*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2373*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2374*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2375*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2376*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2377*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2378*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2379*724ba675SRob Herring 0x00000013 0x00090009 0xa0f10000 0x00000000 2380*724ba675SRob Herring 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; 2381*724ba675SRob Herring }; 2382*724ba675SRob Herring 2383*724ba675SRob Herring timing-102000000 { 2384*724ba675SRob Herring clock-frequency = <102000000>; 2385*724ba675SRob Herring 2386*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2387*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010022>; 2388*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2389*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2390*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x0000000a>; 2391*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2392*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2393*724ba675SRob Herring 2394*724ba675SRob Herring nvidia,emc-configuration = < 0x00000006 2395*724ba675SRob Herring 0x0000000d 0x00000004 0x00000002 0x00000004 2396*724ba675SRob Herring 0x00000004 0x00000001 0x00000005 0x00000002 2397*724ba675SRob Herring 0x00000002 0x00000001 0x00000001 0x00000000 2398*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000b 2399*724ba675SRob Herring 0x0000000a 0x00000181 0x00000000 0x00000060 2400*724ba675SRob Herring 0x00000001 0x00000001 0x00000002 0x00000000 2401*724ba675SRob Herring 0x00000001 0x00000007 0x0000000f 0x0000000f 2402*724ba675SRob Herring 0x00000003 0x00000008 0x00000004 0x00000004 2403*724ba675SRob Herring 0x00000002 0x000001a9 0x00000004 0x00000004 2404*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x007800a4 2405*724ba675SRob Herring 0x00008000 0x000fc000 0x000fc000 0x000fc000 2406*724ba675SRob Herring 0x000fc000 0x000fc000 0x000fc000 0x000fc000 2407*724ba675SRob Herring 0x000fc000 0x00000000 0x00000000 0x00000000 2408*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2409*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2410*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2411*724ba675SRob Herring 0x00000000 0x000fc000 0x000fc000 0x000fc000 2412*724ba675SRob Herring 0x000fc000 0x00100220 0x0800201c 0x00000000 2413*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2414*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2415*724ba675SRob Herring 0x00000025 0x00090009 0xa0f10000 0x00000000 2416*724ba675SRob Herring 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; 2417*724ba675SRob Herring }; 2418*724ba675SRob Herring 2419*724ba675SRob Herring timing-204000000 { 2420*724ba675SRob Herring clock-frequency = <204000000>; 2421*724ba675SRob Herring 2422*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2423*724ba675SRob Herring nvidia,emc-mode-1 = <0x00010042>; 2424*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020001>; 2425*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2426*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000013>; 2427*724ba675SRob Herring nvidia,emc-cfg-dyn-self-ref; 2428*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2429*724ba675SRob Herring 2430*724ba675SRob Herring nvidia,emc-configuration = < 0x0000000c 2431*724ba675SRob Herring 0x0000001a 0x00000008 0x00000003 0x00000005 2432*724ba675SRob Herring 0x00000004 0x00000001 0x00000006 0x00000003 2433*724ba675SRob Herring 0x00000003 0x00000002 0x00000002 0x00000000 2434*724ba675SRob Herring 0x00000001 0x00000003 0x00000001 0x0000000c 2435*724ba675SRob Herring 0x0000000b 0x00000303 0x00000000 0x000000c0 2436*724ba675SRob Herring 0x00000001 0x00000001 0x00000003 0x00000000 2437*724ba675SRob Herring 0x00000001 0x00000007 0x0000001d 0x0000001d 2438*724ba675SRob Herring 0x00000004 0x0000000b 0x00000005 0x00000004 2439*724ba675SRob Herring 0x00000002 0x00000351 0x00000004 0x00000006 2440*724ba675SRob Herring 0x00000000 0x00000000 0x00004282 0x004400a4 2441*724ba675SRob Herring 0x00008000 0x00072000 0x00072000 0x00072000 2442*724ba675SRob Herring 0x00072000 0x00072000 0x00072000 0x00072000 2443*724ba675SRob Herring 0x00072000 0x00000000 0x00000000 0x00000000 2444*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2445*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2446*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2447*724ba675SRob Herring 0x00000000 0x00080000 0x00080000 0x00080000 2448*724ba675SRob Herring 0x00080000 0x000e0220 0x0800201c 0x00000000 2449*724ba675SRob Herring 0x77ffc004 0x01f1f008 0x00000000 0x00000007 2450*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2451*724ba675SRob Herring 0x0000004a 0x00090009 0xa0f10000 0x00000000 2452*724ba675SRob Herring 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; 2453*724ba675SRob Herring }; 2454*724ba675SRob Herring 2455*724ba675SRob Herring timing-533000000 { 2456*724ba675SRob Herring clock-frequency = <533000000>; 2457*724ba675SRob Herring 2458*724ba675SRob Herring nvidia,emc-auto-cal-interval = <0x001fffff>; 2459*724ba675SRob Herring nvidia,emc-mode-1 = <0x000100c2>; 2460*724ba675SRob Herring nvidia,emc-mode-2 = <0x00020006>; 2461*724ba675SRob Herring nvidia,emc-mode-reset = <0x00000000>; 2462*724ba675SRob Herring nvidia,emc-zcal-cnt-long = <0x00000030>; 2463*724ba675SRob Herring nvidia,emc-cfg-periodic-qrst; 2464*724ba675SRob Herring 2465*724ba675SRob Herring nvidia,emc-configuration = < 0x0000001f 2466*724ba675SRob Herring 0x00000045 0x00000016 0x00000009 0x00000008 2467*724ba675SRob Herring 0x00000009 0x00000003 0x0000000d 0x00000009 2468*724ba675SRob Herring 0x00000009 0x00000005 0x00000003 0x00000000 2469*724ba675SRob Herring 0x00000004 0x00000009 0x00000006 0x0000000d 2470*724ba675SRob Herring 0x00000010 0x000007df 0x00000000 0x000001f7 2471*724ba675SRob Herring 0x00000003 0x00000003 0x00000009 0x00000000 2472*724ba675SRob Herring 0x00000001 0x0000000f 0x0000004b 0x0000004b 2473*724ba675SRob Herring 0x00000008 0x0000001b 0x0000000c 0x00000004 2474*724ba675SRob Herring 0x00000002 0x000008aa 0x00000000 0x00000006 2475*724ba675SRob Herring 0x00000000 0x00000000 0x00006282 0xf0120091 2476*724ba675SRob Herring 0x00008000 0x0000000a 0x0000000a 0x0000000a 2477*724ba675SRob Herring 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2478*724ba675SRob Herring 0x0000000a 0x00000000 0x00000000 0x00000000 2479*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2480*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2481*724ba675SRob Herring 0x00000000 0x00000000 0x00000000 0x00000000 2482*724ba675SRob Herring 0x00000000 0x0000000c 0x0000000c 0x0000000c 2483*724ba675SRob Herring 0x0000000c 0x000a0220 0x0800003d 0x00000000 2484*724ba675SRob Herring 0x77ffc004 0x01f1f408 0x00000000 0x00000007 2485*724ba675SRob Herring 0x08000068 0x08000000 0x00000802 0x00064000 2486*724ba675SRob Herring 0x000000c0 0x000e000e 0xa0f10000 0x00000000 2487*724ba675SRob Herring 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; 2488*724ba675SRob Herring }; 2489*724ba675SRob Herring }; 2490*724ba675SRob Herring }; 2491*724ba675SRob Herring 2492*724ba675SRob Herring hda@70030000 { 2493*724ba675SRob Herring status = "okay"; 2494*724ba675SRob Herring }; 2495*724ba675SRob Herring 2496*724ba675SRob Herring ahub@70080000 { 2497*724ba675SRob Herring i2s@70080400 { /* i2s1 */ 2498*724ba675SRob Herring status = "okay"; 2499*724ba675SRob Herring }; 2500*724ba675SRob Herring 2501*724ba675SRob Herring /* BT SCO */ 2502*724ba675SRob Herring i2s@70080600 { /* i2s3 */ 2503*724ba675SRob Herring status = "okay"; 2504*724ba675SRob Herring }; 2505*724ba675SRob Herring }; 2506*724ba675SRob Herring 2507*724ba675SRob Herring sdmmc1: mmc@78000000 { 2508*724ba675SRob Herring status = "okay"; 2509*724ba675SRob Herring 2510*724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 2511*724ba675SRob Herring bus-width = <4>; 2512*724ba675SRob Herring 2513*724ba675SRob Herring vmmc-supply = <&vdd_usd>; /* ldo2 */ 2514*724ba675SRob Herring vqmmc-supply = <&vddio_usd>; /* ldo3 */ 2515*724ba675SRob Herring }; 2516*724ba675SRob Herring 2517*724ba675SRob Herring sdmmc3: mmc@78000400 { 2518*724ba675SRob Herring status = "okay"; 2519*724ba675SRob Herring 2520*724ba675SRob Herring #address-cells = <1>; 2521*724ba675SRob Herring #size-cells = <0>; 2522*724ba675SRob Herring 2523*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 2524*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 2525*724ba675SRob Herring assigned-clock-rates = <50000000>; 2526*724ba675SRob Herring 2527*724ba675SRob Herring max-frequency = <50000000>; 2528*724ba675SRob Herring keep-power-in-suspend; 2529*724ba675SRob Herring bus-width = <4>; 2530*724ba675SRob Herring non-removable; 2531*724ba675SRob Herring 2532*724ba675SRob Herring mmc-pwrseq = <&brcm_wifi_pwrseq>; 2533*724ba675SRob Herring vmmc-supply = <&vdd_3v3_sys>; 2534*724ba675SRob Herring vqmmc-supply = <&vdd_1v8_vio>; 2535*724ba675SRob Herring 2536*724ba675SRob Herring /* Azurewave AW-AH663 BCM4330B1 */ 2537*724ba675SRob Herring wifi@1 { 2538*724ba675SRob Herring compatible = "brcm,bcm4329-fmac"; 2539*724ba675SRob Herring reg = <1>; 2540*724ba675SRob Herring 2541*724ba675SRob Herring interrupt-parent = <&gpio>; 2542*724ba675SRob Herring interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 2543*724ba675SRob Herring interrupt-names = "host-wake"; 2544*724ba675SRob Herring }; 2545*724ba675SRob Herring }; 2546*724ba675SRob Herring 2547*724ba675SRob Herring sdmmc4: mmc@78000600 { 2548*724ba675SRob Herring status = "okay"; 2549*724ba675SRob Herring bus-width = <8>; 2550*724ba675SRob Herring vmmc-supply = <&vcore_emmc>; 2551*724ba675SRob Herring vqmmc-supply = <&vdd_1v8_vio>; 2552*724ba675SRob Herring non-removable; 2553*724ba675SRob Herring }; 2554*724ba675SRob Herring 2555*724ba675SRob Herring usb@7d000000 { 2556*724ba675SRob Herring compatible = "nvidia,tegra30-udc"; 2557*724ba675SRob Herring status = "okay"; 2558*724ba675SRob Herring dr_mode = "otg"; 2559*724ba675SRob Herring vbus-supply = <&vdd_vbus_usb1>; 2560*724ba675SRob Herring }; 2561*724ba675SRob Herring 2562*724ba675SRob Herring usb-phy@7d000000 { 2563*724ba675SRob Herring status = "okay"; 2564*724ba675SRob Herring dr_mode = "otg"; 2565*724ba675SRob Herring nvidia,hssync-start-delay = <0>; 2566*724ba675SRob Herring nvidia,xcvr-lsfslew = <2>; 2567*724ba675SRob Herring nvidia,xcvr-lsrslew = <2>; 2568*724ba675SRob Herring }; 2569*724ba675SRob Herring 2570*724ba675SRob Herring usb@7d008000 { 2571*724ba675SRob Herring status = "okay"; 2572*724ba675SRob Herring }; 2573*724ba675SRob Herring 2574*724ba675SRob Herring usb-phy@7d008000 { 2575*724ba675SRob Herring status = "okay"; 2576*724ba675SRob Herring vbus-supply = <&vdd_vbus_usb3>; 2577*724ba675SRob Herring }; 2578*724ba675SRob Herring 2579*724ba675SRob Herring mains: ac-adapter-detect { 2580*724ba675SRob Herring compatible = "gpio-charger"; 2581*724ba675SRob Herring charger-type = "mains"; 2582*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 2583*724ba675SRob Herring }; 2584*724ba675SRob Herring 2585*724ba675SRob Herring backlight: backlight { 2586*724ba675SRob Herring compatible = "pwm-backlight"; 2587*724ba675SRob Herring 2588*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 2589*724ba675SRob Herring power-supply = <&vdd_5v0_bl>; 2590*724ba675SRob Herring pwms = <&pwm 0 5000000>; 2591*724ba675SRob Herring 2592*724ba675SRob Herring brightness-levels = <1 255>; 2593*724ba675SRob Herring num-interpolated-steps = <254>; 2594*724ba675SRob Herring default-brightness-level = <15>; 2595*724ba675SRob Herring }; 2596*724ba675SRob Herring 2597*724ba675SRob Herring /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 2598*724ba675SRob Herring clk32k_in: clock-32k { 2599*724ba675SRob Herring compatible = "fixed-clock"; 2600*724ba675SRob Herring #clock-cells = <0>; 2601*724ba675SRob Herring clock-frequency = <32768>; 2602*724ba675SRob Herring clock-output-names = "pmic-oscillator"; 2603*724ba675SRob Herring }; 2604*724ba675SRob Herring 2605*724ba675SRob Herring cpus { 2606*724ba675SRob Herring cpu0: cpu@0 { 2607*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 2608*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 2609*724ba675SRob Herring #cooling-cells = <2>; 2610*724ba675SRob Herring }; 2611*724ba675SRob Herring cpu1: cpu@1 { 2612*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 2613*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 2614*724ba675SRob Herring #cooling-cells = <2>; 2615*724ba675SRob Herring }; 2616*724ba675SRob Herring cpu2: cpu@2 { 2617*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 2618*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 2619*724ba675SRob Herring #cooling-cells = <2>; 2620*724ba675SRob Herring }; 2621*724ba675SRob Herring cpu3: cpu@3 { 2622*724ba675SRob Herring cpu-supply = <&vdd_cpu>; 2623*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 2624*724ba675SRob Herring #cooling-cells = <2>; 2625*724ba675SRob Herring }; 2626*724ba675SRob Herring }; 2627*724ba675SRob Herring 2628*724ba675SRob Herring display-panel { 2629*724ba675SRob Herring compatible = "panel-lvds"; 2630*724ba675SRob Herring 2631*724ba675SRob Herring width-mm = <217>; 2632*724ba675SRob Herring height-mm = <136>; 2633*724ba675SRob Herring 2634*724ba675SRob Herring data-mapping = "jeida-24"; 2635*724ba675SRob Herring 2636*724ba675SRob Herring panel-timing { 2637*724ba675SRob Herring /* 1280x800@60Hz */ 2638*724ba675SRob Herring clock-frequency = <68000000>; 2639*724ba675SRob Herring hactive = <1280>; 2640*724ba675SRob Herring vactive = <800>; 2641*724ba675SRob Herring hfront-porch = <48>; 2642*724ba675SRob Herring hback-porch = <18>; 2643*724ba675SRob Herring hsync-len = <30>; 2644*724ba675SRob Herring vsync-len = <5>; 2645*724ba675SRob Herring vfront-porch = <3>; 2646*724ba675SRob Herring vback-porch = <12>; 2647*724ba675SRob Herring }; 2648*724ba675SRob Herring }; 2649*724ba675SRob Herring 2650*724ba675SRob Herring extcon-keys { 2651*724ba675SRob Herring compatible = "gpio-keys"; 2652*724ba675SRob Herring 2653*724ba675SRob Herring switch-dock-insert { 2654*724ba675SRob Herring label = "Chagall Dock"; 2655*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; 2656*724ba675SRob Herring linux,input-type = <EV_SW>; 2657*724ba675SRob Herring linux,code = <SW_DOCK>; 2658*724ba675SRob Herring debounce-interval = <10>; 2659*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 2660*724ba675SRob Herring wakeup-source; 2661*724ba675SRob Herring }; 2662*724ba675SRob Herring 2663*724ba675SRob Herring switch-lineout-detect { 2664*724ba675SRob Herring label = "Audio dock line-out detect"; 2665*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; 2666*724ba675SRob Herring linux,input-type = <EV_SW>; 2667*724ba675SRob Herring linux,code = <SW_LINEOUT_INSERT>; 2668*724ba675SRob Herring debounce-interval = <10>; 2669*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 2670*724ba675SRob Herring wakeup-source; 2671*724ba675SRob Herring }; 2672*724ba675SRob Herring }; 2673*724ba675SRob Herring 2674*724ba675SRob Herring gpio-keys { 2675*724ba675SRob Herring compatible = "gpio-keys"; 2676*724ba675SRob Herring 2677*724ba675SRob Herring key-power { 2678*724ba675SRob Herring label = "Power"; 2679*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 2680*724ba675SRob Herring linux,code = <KEY_POWER>; 2681*724ba675SRob Herring debounce-interval = <10>; 2682*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 2683*724ba675SRob Herring wakeup-source; 2684*724ba675SRob Herring }; 2685*724ba675SRob Herring 2686*724ba675SRob Herring key-volume-down { 2687*724ba675SRob Herring label = "Volume Down"; 2688*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; 2689*724ba675SRob Herring linux,code = <KEY_VOLUMEDOWN>; 2690*724ba675SRob Herring debounce-interval = <10>; 2691*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 2692*724ba675SRob Herring wakeup-source; 2693*724ba675SRob Herring }; 2694*724ba675SRob Herring 2695*724ba675SRob Herring key-volume-up { 2696*724ba675SRob Herring label = "Volume Up"; 2697*724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 2698*724ba675SRob Herring linux,code = <KEY_VOLUMEUP>; 2699*724ba675SRob Herring debounce-interval = <10>; 2700*724ba675SRob Herring wakeup-event-action = <EV_ACT_ASSERTED>; 2701*724ba675SRob Herring wakeup-source; 2702*724ba675SRob Herring }; 2703*724ba675SRob Herring }; 2704*724ba675SRob Herring 2705*724ba675SRob Herring haptic-feedback { 2706*724ba675SRob Herring compatible = "gpio-vibrator"; 2707*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 2708*724ba675SRob Herring vcc-supply = <&vdd_3v3_sys>; 2709*724ba675SRob Herring }; 2710*724ba675SRob Herring 2711*724ba675SRob Herring opp-table-actmon { 2712*724ba675SRob Herring /delete-node/ opp-625000000; 2713*724ba675SRob Herring /delete-node/ opp-667000000; 2714*724ba675SRob Herring /delete-node/ opp-750000000; 2715*724ba675SRob Herring /delete-node/ opp-800000000; 2716*724ba675SRob Herring /delete-node/ opp-900000000; 2717*724ba675SRob Herring }; 2718*724ba675SRob Herring 2719*724ba675SRob Herring opp-table-emc { 2720*724ba675SRob Herring /delete-node/ opp-625000000-1200; 2721*724ba675SRob Herring /delete-node/ opp-625000000-1250; 2722*724ba675SRob Herring /delete-node/ opp-667000000-1200; 2723*724ba675SRob Herring /delete-node/ opp-750000000-1300; 2724*724ba675SRob Herring /delete-node/ opp-800000000-1300; 2725*724ba675SRob Herring /delete-node/ opp-900000000-1350; 2726*724ba675SRob Herring }; 2727*724ba675SRob Herring 2728*724ba675SRob Herring brcm_wifi_pwrseq: pwrseq-wifi { 2729*724ba675SRob Herring compatible = "mmc-pwrseq-simple"; 2730*724ba675SRob Herring 2731*724ba675SRob Herring clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 2732*724ba675SRob Herring clock-names = "ext_clock"; 2733*724ba675SRob Herring 2734*724ba675SRob Herring reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; 2735*724ba675SRob Herring post-power-on-delay-ms = <300>; 2736*724ba675SRob Herring power-off-delay-us = <300>; 2737*724ba675SRob Herring }; 2738*724ba675SRob Herring 2739*724ba675SRob Herring sound { 2740*724ba675SRob Herring compatible = "pegatron,tegra-audio-wm8903-chagall", 2741*724ba675SRob Herring "nvidia,tegra-audio-wm8903"; 2742*724ba675SRob Herring nvidia,model = "Pegatron Chagall WM8903"; 2743*724ba675SRob Herring 2744*724ba675SRob Herring nvidia,audio-routing = 2745*724ba675SRob Herring "Headphone Jack", "HPOUTR", 2746*724ba675SRob Herring "Headphone Jack", "HPOUTL", 2747*724ba675SRob Herring "Int Spk", "ROP", 2748*724ba675SRob Herring "Int Spk", "RON", 2749*724ba675SRob Herring "Int Spk", "LOP", 2750*724ba675SRob Herring "Int Spk", "LON", 2751*724ba675SRob Herring "IN1R", "Mic Jack", 2752*724ba675SRob Herring "DMICDAT", "Int Mic"; 2753*724ba675SRob Herring 2754*724ba675SRob Herring nvidia,i2s-controller = <&tegra_i2s1>; 2755*724ba675SRob Herring nvidia,audio-codec = <&wm8903>; 2756*724ba675SRob Herring 2757*724ba675SRob Herring nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 2758*724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 2759*724ba675SRob Herring nvidia,headset; 2760*724ba675SRob Herring 2761*724ba675SRob Herring clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 2762*724ba675SRob Herring <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 2763*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2764*724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 2765*724ba675SRob Herring 2766*724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 2767*724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2768*724ba675SRob Herring 2769*724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 2770*724ba675SRob Herring <&tegra_car TEGRA30_CLK_EXTERN1>; 2771*724ba675SRob Herring }; 2772*724ba675SRob Herring 2773*724ba675SRob Herring thermal-zones { 2774*724ba675SRob Herring /* 2775*724ba675SRob Herring * NCT72 has two sensors: 2776*724ba675SRob Herring * 2777*724ba675SRob Herring * 0: internal that monitors ambient/skin temperature 2778*724ba675SRob Herring * 1: external that is connected to the CPU's diode 2779*724ba675SRob Herring * 2780*724ba675SRob Herring * Ideally we should use userspace thermal governor, 2781*724ba675SRob Herring * but it's a much more complex solution. The "skin" 2782*724ba675SRob Herring * zone exists as a simpler solution which prevents 2783*724ba675SRob Herring * Chagall from getting too hot from a user's tactile 2784*724ba675SRob Herring * perspective. The CPU zone is intended to protect 2785*724ba675SRob Herring * silicon from damage. 2786*724ba675SRob Herring */ 2787*724ba675SRob Herring 2788*724ba675SRob Herring skin-thermal { 2789*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 2790*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 2791*724ba675SRob Herring 2792*724ba675SRob Herring thermal-sensors = <&nct72 0>; 2793*724ba675SRob Herring 2794*724ba675SRob Herring trips { 2795*724ba675SRob Herring trip0: skin-alert { 2796*724ba675SRob Herring /* throttle at 57C until temperature drops to 56.8C */ 2797*724ba675SRob Herring temperature = <57000>; 2798*724ba675SRob Herring hysteresis = <200>; 2799*724ba675SRob Herring type = "passive"; 2800*724ba675SRob Herring }; 2801*724ba675SRob Herring 2802*724ba675SRob Herring trip1: skin-crit { 2803*724ba675SRob Herring /* shut down at 65C */ 2804*724ba675SRob Herring temperature = <65000>; 2805*724ba675SRob Herring hysteresis = <2000>; 2806*724ba675SRob Herring type = "critical"; 2807*724ba675SRob Herring }; 2808*724ba675SRob Herring }; 2809*724ba675SRob Herring 2810*724ba675SRob Herring cooling-maps { 2811*724ba675SRob Herring map0 { 2812*724ba675SRob Herring trip = <&trip0>; 2813*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2814*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2815*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2816*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2817*724ba675SRob Herring <&actmon THERMAL_NO_LIMIT 2818*724ba675SRob Herring THERMAL_NO_LIMIT>; 2819*724ba675SRob Herring }; 2820*724ba675SRob Herring }; 2821*724ba675SRob Herring }; 2822*724ba675SRob Herring 2823*724ba675SRob Herring cpu-thermal { 2824*724ba675SRob Herring polling-delay-passive = <1000>; /* milliseconds */ 2825*724ba675SRob Herring polling-delay = <5000>; /* milliseconds */ 2826*724ba675SRob Herring 2827*724ba675SRob Herring thermal-sensors = <&nct72 1>; 2828*724ba675SRob Herring 2829*724ba675SRob Herring trips { 2830*724ba675SRob Herring trip2: cpu-alert { 2831*724ba675SRob Herring /* throttle at 85C until temperature drops to 84.8C */ 2832*724ba675SRob Herring temperature = <85000>; 2833*724ba675SRob Herring hysteresis = <200>; 2834*724ba675SRob Herring type = "passive"; 2835*724ba675SRob Herring }; 2836*724ba675SRob Herring 2837*724ba675SRob Herring trip3: cpu-crit { 2838*724ba675SRob Herring /* shut down at 90C */ 2839*724ba675SRob Herring temperature = <90000>; 2840*724ba675SRob Herring hysteresis = <2000>; 2841*724ba675SRob Herring type = "critical"; 2842*724ba675SRob Herring }; 2843*724ba675SRob Herring }; 2844*724ba675SRob Herring 2845*724ba675SRob Herring cooling-maps { 2846*724ba675SRob Herring map1 { 2847*724ba675SRob Herring trip = <&trip2>; 2848*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2849*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2850*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2851*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2852*724ba675SRob Herring <&actmon THERMAL_NO_LIMIT 2853*724ba675SRob Herring THERMAL_NO_LIMIT>; 2854*724ba675SRob Herring }; 2855*724ba675SRob Herring }; 2856*724ba675SRob Herring }; 2857*724ba675SRob Herring }; 2858*724ba675SRob Herring}; 2859