xref: /linux/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring#include <dt-bindings/input/input.h>
3*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h>
4*724ba675SRob Herring#include "tegra30.dtsi"
5*724ba675SRob Herring#include "tegra30-cpu-opp.dtsi"
6*724ba675SRob Herring#include "tegra30-cpu-opp-microvolt.dtsi"
7*724ba675SRob Herring
8*724ba675SRob Herring/**
9*724ba675SRob Herring * This file contains common DT entry for all fab version of Cardhu.
10*724ba675SRob Herring * There is multiple fab version of Cardhu starting from A01 to A07.
11*724ba675SRob Herring * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
12*724ba675SRob Herring * A02 will have different sets of GPIOs for fixed regulator compare to
13*724ba675SRob Herring * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
14*724ba675SRob Herring * compatible with fab version A04. Based on Cardhu fab version, the
15*724ba675SRob Herring * related dts file need to be chosen like for Cardhu fab version A02,
16*724ba675SRob Herring * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17*724ba675SRob Herring * tegra30-cardhu-a04.dts.
18*724ba675SRob Herring * The identification of board is done in two ways, by looking the sticker
19*724ba675SRob Herring * on PCB and by reading board id eeprom.
20*724ba675SRob Herring * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
21*724ba675SRob Herring * number is the fab version like here it is 002 and hence fab version A02.
22*724ba675SRob Herring * The (downstream internal) U-Boot of Cardhu display the board-id as
23*724ba675SRob Herring * follows:
24*724ba675SRob Herring * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
25*724ba675SRob Herring * In this Fab version is 02 i.e. A02.
26*724ba675SRob Herring * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
27*724ba675SRob Herring * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
28*724ba675SRob Herring * wide.
29*724ba675SRob Herring */
30*724ba675SRob Herring
31*724ba675SRob Herring/ {
32*724ba675SRob Herring	model = "NVIDIA Tegra30 Cardhu evaluation board";
33*724ba675SRob Herring	compatible = "nvidia,cardhu", "nvidia,tegra30";
34*724ba675SRob Herring
35*724ba675SRob Herring	aliases {
36*724ba675SRob Herring		rtc0 = "/i2c@7000d000/tps65911@2d";
37*724ba675SRob Herring		rtc1 = "/rtc@7000e000";
38*724ba675SRob Herring		serial0 = &uarta;
39*724ba675SRob Herring		serial1 = &uartc;
40*724ba675SRob Herring	};
41*724ba675SRob Herring
42*724ba675SRob Herring	chosen {
43*724ba675SRob Herring		stdout-path = "serial0:115200n8";
44*724ba675SRob Herring	};
45*724ba675SRob Herring
46*724ba675SRob Herring	memory@80000000 {
47*724ba675SRob Herring		reg = <0x80000000 0x40000000>;
48*724ba675SRob Herring	};
49*724ba675SRob Herring
50*724ba675SRob Herring	pcie@3000 {
51*724ba675SRob Herring		status = "okay";
52*724ba675SRob Herring
53*724ba675SRob Herring		/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
54*724ba675SRob Herring		avdd-pexb-supply = <&ldo1_reg>;
55*724ba675SRob Herring		vdd-pexb-supply = <&ldo1_reg>;
56*724ba675SRob Herring		avdd-pex-pll-supply = <&ldo1_reg>;
57*724ba675SRob Herring		hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
58*724ba675SRob Herring		vddio-pex-ctl-supply = <&sys_3v3_reg>;
59*724ba675SRob Herring		avdd-plle-supply = <&ldo2_reg>;
60*724ba675SRob Herring
61*724ba675SRob Herring		pci@1,0 {
62*724ba675SRob Herring			nvidia,num-lanes = <4>;
63*724ba675SRob Herring		};
64*724ba675SRob Herring
65*724ba675SRob Herring		pci@2,0 {
66*724ba675SRob Herring			nvidia,num-lanes = <1>;
67*724ba675SRob Herring		};
68*724ba675SRob Herring
69*724ba675SRob Herring		pci@3,0 {
70*724ba675SRob Herring			status = "okay";
71*724ba675SRob Herring			nvidia,num-lanes = <1>;
72*724ba675SRob Herring		};
73*724ba675SRob Herring	};
74*724ba675SRob Herring
75*724ba675SRob Herring	host1x@50000000 {
76*724ba675SRob Herring		dc@54200000 {
77*724ba675SRob Herring			rgb {
78*724ba675SRob Herring				status = "okay";
79*724ba675SRob Herring
80*724ba675SRob Herring				nvidia,panel = <&panel>;
81*724ba675SRob Herring			};
82*724ba675SRob Herring		};
83*724ba675SRob Herring	};
84*724ba675SRob Herring
85*724ba675SRob Herring	pinmux@70000868 {
86*724ba675SRob Herring		pinctrl-names = "default";
87*724ba675SRob Herring		pinctrl-0 = <&state_default>;
88*724ba675SRob Herring
89*724ba675SRob Herring		state_default: pinmux {
90*724ba675SRob Herring			sdmmc1_clk_pz0 {
91*724ba675SRob Herring				nvidia,pins = "sdmmc1_clk_pz0";
92*724ba675SRob Herring				nvidia,function = "sdmmc1";
93*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
95*724ba675SRob Herring			};
96*724ba675SRob Herring			sdmmc1_cmd_pz1 {
97*724ba675SRob Herring				nvidia,pins =	"sdmmc1_cmd_pz1",
98*724ba675SRob Herring						"sdmmc1_dat0_py7",
99*724ba675SRob Herring						"sdmmc1_dat1_py6",
100*724ba675SRob Herring						"sdmmc1_dat2_py5",
101*724ba675SRob Herring						"sdmmc1_dat3_py4";
102*724ba675SRob Herring				nvidia,function = "sdmmc1";
103*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
104*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
105*724ba675SRob Herring			};
106*724ba675SRob Herring			sdmmc3_clk_pa6 {
107*724ba675SRob Herring				nvidia,pins = "sdmmc3_clk_pa6";
108*724ba675SRob Herring				nvidia,function = "sdmmc3";
109*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
111*724ba675SRob Herring			};
112*724ba675SRob Herring			sdmmc3_cmd_pa7 {
113*724ba675SRob Herring				nvidia,pins =	"sdmmc3_cmd_pa7",
114*724ba675SRob Herring						"sdmmc3_dat0_pb7",
115*724ba675SRob Herring						"sdmmc3_dat1_pb6",
116*724ba675SRob Herring						"sdmmc3_dat2_pb5",
117*724ba675SRob Herring						"sdmmc3_dat3_pb4";
118*724ba675SRob Herring				nvidia,function = "sdmmc3";
119*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
120*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
121*724ba675SRob Herring			};
122*724ba675SRob Herring			sdmmc4_clk_pcc4 {
123*724ba675SRob Herring				nvidia,pins =	"sdmmc4_clk_pcc4",
124*724ba675SRob Herring						"sdmmc4_rst_n_pcc3";
125*724ba675SRob Herring				nvidia,function = "sdmmc4";
126*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
128*724ba675SRob Herring			};
129*724ba675SRob Herring			sdmmc4_dat0_paa0 {
130*724ba675SRob Herring				nvidia,pins =	"sdmmc4_dat0_paa0",
131*724ba675SRob Herring						"sdmmc4_dat1_paa1",
132*724ba675SRob Herring						"sdmmc4_dat2_paa2",
133*724ba675SRob Herring						"sdmmc4_dat3_paa3",
134*724ba675SRob Herring						"sdmmc4_dat4_paa4",
135*724ba675SRob Herring						"sdmmc4_dat5_paa5",
136*724ba675SRob Herring						"sdmmc4_dat6_paa6",
137*724ba675SRob Herring						"sdmmc4_dat7_paa7";
138*724ba675SRob Herring				nvidia,function = "sdmmc4";
139*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
140*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
141*724ba675SRob Herring			};
142*724ba675SRob Herring			dap2_fs_pa2 {
143*724ba675SRob Herring				nvidia,pins =	"dap2_fs_pa2",
144*724ba675SRob Herring						"dap2_sclk_pa3",
145*724ba675SRob Herring						"dap2_din_pa4",
146*724ba675SRob Herring						"dap2_dout_pa5";
147*724ba675SRob Herring				nvidia,function = "i2s1";
148*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
150*724ba675SRob Herring			};
151*724ba675SRob Herring			sdio3 {
152*724ba675SRob Herring				nvidia,pins = "drive_sdio3";
153*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
154*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
155*724ba675SRob Herring				nvidia,pull-down-strength = <46>;
156*724ba675SRob Herring				nvidia,pull-up-strength = <42>;
157*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
158*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
159*724ba675SRob Herring			};
160*724ba675SRob Herring			uart3_txd_pw6 {
161*724ba675SRob Herring				nvidia,pins =	"uart3_txd_pw6",
162*724ba675SRob Herring						"uart3_cts_n_pa1",
163*724ba675SRob Herring						"uart3_rts_n_pc0",
164*724ba675SRob Herring						"uart3_rxd_pw7";
165*724ba675SRob Herring				nvidia,function = "uartc";
166*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168*724ba675SRob Herring			};
169*724ba675SRob Herring		};
170*724ba675SRob Herring	};
171*724ba675SRob Herring
172*724ba675SRob Herring	serial@70006000 {
173*724ba675SRob Herring		status = "okay";
174*724ba675SRob Herring	};
175*724ba675SRob Herring
176*724ba675SRob Herring	serial@70006200 {
177*724ba675SRob Herring		compatible = "nvidia,tegra30-hsuart";
178*724ba675SRob Herring		/delete-property/ reg-shift;
179*724ba675SRob Herring		status = "okay";
180*724ba675SRob Herring	};
181*724ba675SRob Herring
182*724ba675SRob Herring	pwm@7000a000 {
183*724ba675SRob Herring		status = "okay";
184*724ba675SRob Herring	};
185*724ba675SRob Herring
186*724ba675SRob Herring	panelddc: i2c@7000c000 {
187*724ba675SRob Herring		status = "okay";
188*724ba675SRob Herring		clock-frequency = <100000>;
189*724ba675SRob Herring	};
190*724ba675SRob Herring
191*724ba675SRob Herring	i2c@7000c400 {
192*724ba675SRob Herring		status = "okay";
193*724ba675SRob Herring		clock-frequency = <100000>;
194*724ba675SRob Herring	};
195*724ba675SRob Herring
196*724ba675SRob Herring	i2c@7000c500 {
197*724ba675SRob Herring		status = "okay";
198*724ba675SRob Herring		clock-frequency = <100000>;
199*724ba675SRob Herring
200*724ba675SRob Herring		/* ALS and Proximity sensor */
201*724ba675SRob Herring		isl29028@44 {
202*724ba675SRob Herring			compatible = "isil,isl29028";
203*724ba675SRob Herring			reg = <0x44>;
204*724ba675SRob Herring			interrupt-parent = <&gpio>;
205*724ba675SRob Herring			interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
206*724ba675SRob Herring		};
207*724ba675SRob Herring
208*724ba675SRob Herring		i2cmux@70 {
209*724ba675SRob Herring			compatible = "nxp,pca9546";
210*724ba675SRob Herring			#address-cells = <1>;
211*724ba675SRob Herring			#size-cells = <0>;
212*724ba675SRob Herring			reg = <0x70>;
213*724ba675SRob Herring			reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
214*724ba675SRob Herring		};
215*724ba675SRob Herring	};
216*724ba675SRob Herring
217*724ba675SRob Herring	i2c@7000c700 {
218*724ba675SRob Herring		status = "okay";
219*724ba675SRob Herring		clock-frequency = <100000>;
220*724ba675SRob Herring	};
221*724ba675SRob Herring
222*724ba675SRob Herring	i2c@7000d000 {
223*724ba675SRob Herring		status = "okay";
224*724ba675SRob Herring		clock-frequency = <100000>;
225*724ba675SRob Herring
226*724ba675SRob Herring		wm8903: wm8903@1a {
227*724ba675SRob Herring			compatible = "wlf,wm8903";
228*724ba675SRob Herring			reg = <0x1a>;
229*724ba675SRob Herring			interrupt-parent = <&gpio>;
230*724ba675SRob Herring			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
231*724ba675SRob Herring
232*724ba675SRob Herring			gpio-controller;
233*724ba675SRob Herring			#gpio-cells = <2>;
234*724ba675SRob Herring
235*724ba675SRob Herring			micdet-cfg = <0>;
236*724ba675SRob Herring			micdet-delay = <100>;
237*724ba675SRob Herring			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
238*724ba675SRob Herring		};
239*724ba675SRob Herring
240*724ba675SRob Herring		pmic: tps65911@2d {
241*724ba675SRob Herring			compatible = "ti,tps65911";
242*724ba675SRob Herring			reg = <0x2d>;
243*724ba675SRob Herring
244*724ba675SRob Herring			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
245*724ba675SRob Herring			#interrupt-cells = <2>;
246*724ba675SRob Herring			interrupt-controller;
247*724ba675SRob Herring			wakeup-source;
248*724ba675SRob Herring
249*724ba675SRob Herring			ti,system-power-controller;
250*724ba675SRob Herring
251*724ba675SRob Herring			#gpio-cells = <2>;
252*724ba675SRob Herring			gpio-controller;
253*724ba675SRob Herring
254*724ba675SRob Herring			vcc1-supply = <&vdd_ac_bat_reg>;
255*724ba675SRob Herring			vcc2-supply = <&vdd_ac_bat_reg>;
256*724ba675SRob Herring			vcc3-supply = <&vio_reg>;
257*724ba675SRob Herring			vcc4-supply = <&vdd_5v0_reg>;
258*724ba675SRob Herring			vcc5-supply = <&vdd_ac_bat_reg>;
259*724ba675SRob Herring			vcc6-supply = <&vdd2_reg>;
260*724ba675SRob Herring			vcc7-supply = <&vdd_ac_bat_reg>;
261*724ba675SRob Herring			vccio-supply = <&vdd_ac_bat_reg>;
262*724ba675SRob Herring
263*724ba675SRob Herring			regulators {
264*724ba675SRob Herring				vdd1_reg: vdd1 {
265*724ba675SRob Herring					regulator-name = "vddio_ddr_1v2";
266*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
267*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
268*724ba675SRob Herring					regulator-always-on;
269*724ba675SRob Herring				};
270*724ba675SRob Herring
271*724ba675SRob Herring				vdd2_reg: vdd2 {
272*724ba675SRob Herring					regulator-name = "vdd_1v5_gen";
273*724ba675SRob Herring					regulator-min-microvolt = <1500000>;
274*724ba675SRob Herring					regulator-max-microvolt = <1500000>;
275*724ba675SRob Herring					regulator-always-on;
276*724ba675SRob Herring				};
277*724ba675SRob Herring
278*724ba675SRob Herring				vddctrl_reg: vddctrl {
279*724ba675SRob Herring					regulator-name = "vdd_cpu,vdd_sys";
280*724ba675SRob Herring					regulator-min-microvolt = <800000>;
281*724ba675SRob Herring					regulator-max-microvolt = <1250000>;
282*724ba675SRob Herring					regulator-coupled-with = <&vdd_core>;
283*724ba675SRob Herring					regulator-coupled-max-spread = <300000>;
284*724ba675SRob Herring					regulator-max-step-microvolt = <100000>;
285*724ba675SRob Herring					regulator-always-on;
286*724ba675SRob Herring
287*724ba675SRob Herring					nvidia,tegra-cpu-regulator;
288*724ba675SRob Herring				};
289*724ba675SRob Herring
290*724ba675SRob Herring				vio_reg: vio {
291*724ba675SRob Herring					regulator-name = "vdd_1v8_gen";
292*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
293*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
294*724ba675SRob Herring					regulator-always-on;
295*724ba675SRob Herring				};
296*724ba675SRob Herring
297*724ba675SRob Herring				ldo1_reg: ldo1 {
298*724ba675SRob Herring					regulator-name = "vdd_pexa,vdd_pexb";
299*724ba675SRob Herring					regulator-min-microvolt = <1050000>;
300*724ba675SRob Herring					regulator-max-microvolt = <1050000>;
301*724ba675SRob Herring				};
302*724ba675SRob Herring
303*724ba675SRob Herring				ldo2_reg: ldo2 {
304*724ba675SRob Herring					regulator-name = "vdd_sata,avdd_plle";
305*724ba675SRob Herring					regulator-min-microvolt = <1050000>;
306*724ba675SRob Herring					regulator-max-microvolt = <1050000>;
307*724ba675SRob Herring				};
308*724ba675SRob Herring
309*724ba675SRob Herring				/* LDO3 is not connected to anything */
310*724ba675SRob Herring
311*724ba675SRob Herring				ldo4_reg: ldo4 {
312*724ba675SRob Herring					regulator-name = "vdd_rtc";
313*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
314*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
315*724ba675SRob Herring					regulator-always-on;
316*724ba675SRob Herring				};
317*724ba675SRob Herring
318*724ba675SRob Herring				ldo5_reg: ldo5 {
319*724ba675SRob Herring					regulator-name = "vddio_sdmmc,avdd_vdac";
320*724ba675SRob Herring					regulator-min-microvolt = <3300000>;
321*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
322*724ba675SRob Herring					regulator-always-on;
323*724ba675SRob Herring				};
324*724ba675SRob Herring
325*724ba675SRob Herring				ldo6_reg: ldo6 {
326*724ba675SRob Herring					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
327*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
328*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
329*724ba675SRob Herring				};
330*724ba675SRob Herring
331*724ba675SRob Herring				ldo7_reg: ldo7 {
332*724ba675SRob Herring					regulator-name = "vdd_pllm,x,u,a_p_c_s";
333*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
334*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
335*724ba675SRob Herring					regulator-always-on;
336*724ba675SRob Herring				};
337*724ba675SRob Herring
338*724ba675SRob Herring				ldo8_reg: ldo8 {
339*724ba675SRob Herring					regulator-name = "vdd_ddr_hs";
340*724ba675SRob Herring					regulator-min-microvolt = <1000000>;
341*724ba675SRob Herring					regulator-max-microvolt = <1000000>;
342*724ba675SRob Herring					regulator-always-on;
343*724ba675SRob Herring				};
344*724ba675SRob Herring			};
345*724ba675SRob Herring		};
346*724ba675SRob Herring
347*724ba675SRob Herring		nct1008: temperature-sensor@4c {
348*724ba675SRob Herring			compatible = "onnn,nct1008";
349*724ba675SRob Herring			reg = <0x4c>;
350*724ba675SRob Herring			vcc-supply = <&sys_3v3_reg>;
351*724ba675SRob Herring			interrupt-parent = <&gpio>;
352*724ba675SRob Herring			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
353*724ba675SRob Herring			#thermal-sensor-cells = <1>;
354*724ba675SRob Herring		};
355*724ba675SRob Herring
356*724ba675SRob Herring		vdd_core: tps62361@60 {
357*724ba675SRob Herring			compatible = "ti,tps62361";
358*724ba675SRob Herring			reg = <0x60>;
359*724ba675SRob Herring
360*724ba675SRob Herring			regulator-name = "tps62361-vout";
361*724ba675SRob Herring			regulator-min-microvolt = <500000>;
362*724ba675SRob Herring			regulator-max-microvolt = <1500000>;
363*724ba675SRob Herring			regulator-coupled-with = <&vddctrl_reg>;
364*724ba675SRob Herring			regulator-coupled-max-spread = <300000>;
365*724ba675SRob Herring			regulator-max-step-microvolt = <100000>;
366*724ba675SRob Herring			regulator-boot-on;
367*724ba675SRob Herring			regulator-always-on;
368*724ba675SRob Herring			ti,vsel0-state-high;
369*724ba675SRob Herring			ti,vsel1-state-high;
370*724ba675SRob Herring
371*724ba675SRob Herring			nvidia,tegra-core-regulator;
372*724ba675SRob Herring		};
373*724ba675SRob Herring	};
374*724ba675SRob Herring
375*724ba675SRob Herring	spi@7000da00 {
376*724ba675SRob Herring		status = "okay";
377*724ba675SRob Herring		spi-max-frequency = <25000000>;
378*724ba675SRob Herring
379*724ba675SRob Herring		flash@1 {
380*724ba675SRob Herring			compatible = "winbond,w25q32", "jedec,spi-nor";
381*724ba675SRob Herring			reg = <1>;
382*724ba675SRob Herring			spi-max-frequency = <20000000>;
383*724ba675SRob Herring		};
384*724ba675SRob Herring	};
385*724ba675SRob Herring
386*724ba675SRob Herring	pmc@7000e400 {
387*724ba675SRob Herring		status = "okay";
388*724ba675SRob Herring		nvidia,invert-interrupt;
389*724ba675SRob Herring		nvidia,suspend-mode = <1>;
390*724ba675SRob Herring		nvidia,cpu-pwr-good-time = <2000>;
391*724ba675SRob Herring		nvidia,cpu-pwr-off-time = <200>;
392*724ba675SRob Herring		nvidia,core-pwr-good-time = <3845 3845>;
393*724ba675SRob Herring		nvidia,core-pwr-off-time = <0>;
394*724ba675SRob Herring		nvidia,core-power-req-active-high;
395*724ba675SRob Herring		nvidia,sys-clock-req-active-high;
396*724ba675SRob Herring		core-supply = <&vdd_core>;
397*724ba675SRob Herring	};
398*724ba675SRob Herring
399*724ba675SRob Herring	ahub@70080000 {
400*724ba675SRob Herring		i2s@70080400 {
401*724ba675SRob Herring			status = "okay";
402*724ba675SRob Herring		};
403*724ba675SRob Herring	};
404*724ba675SRob Herring
405*724ba675SRob Herring	mmc@78000000 {
406*724ba675SRob Herring		status = "okay";
407*724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
408*724ba675SRob Herring		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
409*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
410*724ba675SRob Herring		bus-width = <4>;
411*724ba675SRob Herring	};
412*724ba675SRob Herring
413*724ba675SRob Herring	mmc@78000600 {
414*724ba675SRob Herring		status = "okay";
415*724ba675SRob Herring		bus-width = <8>;
416*724ba675SRob Herring		non-removable;
417*724ba675SRob Herring	};
418*724ba675SRob Herring
419*724ba675SRob Herring	usb@7d008000 {
420*724ba675SRob Herring		status = "okay";
421*724ba675SRob Herring	};
422*724ba675SRob Herring
423*724ba675SRob Herring	usb-phy@7d008000 {
424*724ba675SRob Herring		vbus-supply = <&usb3_vbus_reg>;
425*724ba675SRob Herring		status = "okay";
426*724ba675SRob Herring	};
427*724ba675SRob Herring
428*724ba675SRob Herring	backlight: backlight {
429*724ba675SRob Herring		compatible = "pwm-backlight";
430*724ba675SRob Herring
431*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
432*724ba675SRob Herring		power-supply = <&vdd_bl_reg>;
433*724ba675SRob Herring		pwms = <&pwm 0 5000000>;
434*724ba675SRob Herring
435*724ba675SRob Herring		brightness-levels = <0 4 8 16 32 64 128 255>;
436*724ba675SRob Herring		default-brightness-level = <6>;
437*724ba675SRob Herring	};
438*724ba675SRob Herring
439*724ba675SRob Herring	clk32k_in: clock-32k {
440*724ba675SRob Herring		compatible = "fixed-clock";
441*724ba675SRob Herring		clock-frequency = <32768>;
442*724ba675SRob Herring		#clock-cells = <0>;
443*724ba675SRob Herring	};
444*724ba675SRob Herring
445*724ba675SRob Herring	cpus {
446*724ba675SRob Herring		cpu0: cpu@0 {
447*724ba675SRob Herring			cpu-supply = <&vddctrl_reg>;
448*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
449*724ba675SRob Herring			#cooling-cells = <2>;
450*724ba675SRob Herring		};
451*724ba675SRob Herring
452*724ba675SRob Herring		cpu1: cpu@1 {
453*724ba675SRob Herring			cpu-supply = <&vddctrl_reg>;
454*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
455*724ba675SRob Herring			#cooling-cells = <2>;
456*724ba675SRob Herring		};
457*724ba675SRob Herring
458*724ba675SRob Herring		cpu2: cpu@2 {
459*724ba675SRob Herring			cpu-supply = <&vddctrl_reg>;
460*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
461*724ba675SRob Herring			#cooling-cells = <2>;
462*724ba675SRob Herring		};
463*724ba675SRob Herring
464*724ba675SRob Herring		cpu3: cpu@3 {
465*724ba675SRob Herring			cpu-supply = <&vddctrl_reg>;
466*724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
467*724ba675SRob Herring			#cooling-cells = <2>;
468*724ba675SRob Herring		};
469*724ba675SRob Herring	};
470*724ba675SRob Herring
471*724ba675SRob Herring	gpio-keys {
472*724ba675SRob Herring		compatible = "gpio-keys";
473*724ba675SRob Herring
474*724ba675SRob Herring		key-power {
475*724ba675SRob Herring			label = "Power";
476*724ba675SRob Herring			interrupt-parent = <&pmic>;
477*724ba675SRob Herring			interrupts = <2 0>;
478*724ba675SRob Herring			linux,code = <KEY_POWER>;
479*724ba675SRob Herring			debounce-interval = <100>;
480*724ba675SRob Herring			wakeup-source;
481*724ba675SRob Herring		};
482*724ba675SRob Herring
483*724ba675SRob Herring		key-volume-down {
484*724ba675SRob Herring			label = "Volume Down";
485*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
486*724ba675SRob Herring			linux,code = <KEY_VOLUMEDOWN>;
487*724ba675SRob Herring			debounce-interval = <10>;
488*724ba675SRob Herring		};
489*724ba675SRob Herring
490*724ba675SRob Herring		key-volume-up {
491*724ba675SRob Herring			label = "Volume Up";
492*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
493*724ba675SRob Herring			linux,code = <KEY_VOLUMEUP>;
494*724ba675SRob Herring			debounce-interval = <10>;
495*724ba675SRob Herring		};
496*724ba675SRob Herring	};
497*724ba675SRob Herring
498*724ba675SRob Herring	panel: panel {
499*724ba675SRob Herring		compatible = "chunghwa,claa101wb01";
500*724ba675SRob Herring		ddc-i2c-bus = <&panelddc>;
501*724ba675SRob Herring
502*724ba675SRob Herring		power-supply = <&vdd_pnl1_reg>;
503*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
504*724ba675SRob Herring
505*724ba675SRob Herring		backlight = <&backlight>;
506*724ba675SRob Herring	};
507*724ba675SRob Herring
508*724ba675SRob Herring	vdd_ac_bat_reg: regulator-acbat {
509*724ba675SRob Herring		compatible = "regulator-fixed";
510*724ba675SRob Herring		regulator-name = "vdd_ac_bat";
511*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
512*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
513*724ba675SRob Herring		regulator-always-on;
514*724ba675SRob Herring	};
515*724ba675SRob Herring
516*724ba675SRob Herring	cam_1v8_reg: regulator-cam {
517*724ba675SRob Herring		compatible = "regulator-fixed";
518*724ba675SRob Herring		regulator-name = "cam_1v8";
519*724ba675SRob Herring		regulator-min-microvolt = <1800000>;
520*724ba675SRob Herring		regulator-max-microvolt = <1800000>;
521*724ba675SRob Herring		enable-active-high;
522*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
523*724ba675SRob Herring		vin-supply = <&vio_reg>;
524*724ba675SRob Herring	};
525*724ba675SRob Herring
526*724ba675SRob Herring	cp_5v_reg: regulator-5v0cp {
527*724ba675SRob Herring		compatible = "regulator-fixed";
528*724ba675SRob Herring		regulator-name = "cp_5v";
529*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
530*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
531*724ba675SRob Herring		regulator-boot-on;
532*724ba675SRob Herring		regulator-always-on;
533*724ba675SRob Herring		enable-active-high;
534*724ba675SRob Herring		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
535*724ba675SRob Herring	};
536*724ba675SRob Herring
537*724ba675SRob Herring	emmc_3v3_reg: regulator-emmc {
538*724ba675SRob Herring		compatible = "regulator-fixed";
539*724ba675SRob Herring		regulator-name = "emmc_3v3";
540*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
541*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
542*724ba675SRob Herring		regulator-always-on;
543*724ba675SRob Herring		regulator-boot-on;
544*724ba675SRob Herring		enable-active-high;
545*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
546*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
547*724ba675SRob Herring	};
548*724ba675SRob Herring
549*724ba675SRob Herring	modem_3v3_reg: regulator-modem {
550*724ba675SRob Herring		compatible = "regulator-fixed";
551*724ba675SRob Herring		regulator-name = "modem_3v3";
552*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
553*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
554*724ba675SRob Herring		enable-active-high;
555*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
556*724ba675SRob Herring	};
557*724ba675SRob Herring
558*724ba675SRob Herring	pex_hvdd_3v3_reg: regulator-pex {
559*724ba675SRob Herring		compatible = "regulator-fixed";
560*724ba675SRob Herring		regulator-name = "pex_hvdd_3v3";
561*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
562*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
563*724ba675SRob Herring		enable-active-high;
564*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
565*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
566*724ba675SRob Herring	};
567*724ba675SRob Herring
568*724ba675SRob Herring	vdd_cam1_ldo_reg: regulator-cam1 {
569*724ba675SRob Herring		compatible = "regulator-fixed";
570*724ba675SRob Herring		regulator-name = "vdd_cam1_ldo";
571*724ba675SRob Herring		regulator-min-microvolt = <2800000>;
572*724ba675SRob Herring		regulator-max-microvolt = <2800000>;
573*724ba675SRob Herring		enable-active-high;
574*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
575*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
576*724ba675SRob Herring	};
577*724ba675SRob Herring
578*724ba675SRob Herring	vdd_cam2_ldo_reg: regulator-cam2 {
579*724ba675SRob Herring		compatible = "regulator-fixed";
580*724ba675SRob Herring		regulator-name = "vdd_cam2_ldo";
581*724ba675SRob Herring		regulator-min-microvolt = <2800000>;
582*724ba675SRob Herring		regulator-max-microvolt = <2800000>;
583*724ba675SRob Herring		enable-active-high;
584*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
585*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
586*724ba675SRob Herring	};
587*724ba675SRob Herring
588*724ba675SRob Herring	vdd_cam3_ldo_reg: regulator-cam3 {
589*724ba675SRob Herring		compatible = "regulator-fixed";
590*724ba675SRob Herring		regulator-name = "vdd_cam3_ldo";
591*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
592*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
593*724ba675SRob Herring		enable-active-high;
594*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
595*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
596*724ba675SRob Herring	};
597*724ba675SRob Herring
598*724ba675SRob Herring	vdd_com_reg: regulator-com {
599*724ba675SRob Herring		compatible = "regulator-fixed";
600*724ba675SRob Herring		regulator-name = "vdd_com";
601*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
602*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
603*724ba675SRob Herring		regulator-always-on;
604*724ba675SRob Herring		regulator-boot-on;
605*724ba675SRob Herring		enable-active-high;
606*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
607*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
608*724ba675SRob Herring	};
609*724ba675SRob Herring
610*724ba675SRob Herring	vdd_fuse_3v3_reg: regulator-fuse {
611*724ba675SRob Herring		compatible = "regulator-fixed";
612*724ba675SRob Herring		regulator-name = "vdd_fuse_3v3";
613*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
614*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
615*724ba675SRob Herring		enable-active-high;
616*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
617*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
618*724ba675SRob Herring	};
619*724ba675SRob Herring
620*724ba675SRob Herring	vdd_pnl1_reg: regulator-pnl1 {
621*724ba675SRob Herring		compatible = "regulator-fixed";
622*724ba675SRob Herring		regulator-name = "vdd_pnl1";
623*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
624*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
625*724ba675SRob Herring		regulator-always-on;
626*724ba675SRob Herring		regulator-boot-on;
627*724ba675SRob Herring		enable-active-high;
628*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
629*724ba675SRob Herring		vin-supply = <&sys_3v3_reg>;
630*724ba675SRob Herring	};
631*724ba675SRob Herring
632*724ba675SRob Herring	vdd_vid_reg: regulator-vid {
633*724ba675SRob Herring		compatible = "regulator-fixed";
634*724ba675SRob Herring		regulator-name = "vddio_vid";
635*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
636*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
637*724ba675SRob Herring		enable-active-high;
638*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
639*724ba675SRob Herring		gpio-open-drain;
640*724ba675SRob Herring		vin-supply = <&vdd_5v0_reg>;
641*724ba675SRob Herring	};
642*724ba675SRob Herring
643*724ba675SRob Herring	sound {
644*724ba675SRob Herring		compatible = "nvidia,tegra-audio-wm8903-cardhu",
645*724ba675SRob Herring			     "nvidia,tegra-audio-wm8903";
646*724ba675SRob Herring		nvidia,model = "NVIDIA Tegra Cardhu";
647*724ba675SRob Herring
648*724ba675SRob Herring		nvidia,audio-routing =
649*724ba675SRob Herring			"Headphone Jack", "HPOUTR",
650*724ba675SRob Herring			"Headphone Jack", "HPOUTL",
651*724ba675SRob Herring			"Int Spk", "ROP",
652*724ba675SRob Herring			"Int Spk", "RON",
653*724ba675SRob Herring			"Int Spk", "LOP",
654*724ba675SRob Herring			"Int Spk", "LON",
655*724ba675SRob Herring			"Mic Jack", "MICBIAS",
656*724ba675SRob Herring			"IN1L", "Mic Jack";
657*724ba675SRob Herring
658*724ba675SRob Herring		nvidia,i2s-controller = <&tegra_i2s1>;
659*724ba675SRob Herring		nvidia,audio-codec = <&wm8903>;
660*724ba675SRob Herring
661*724ba675SRob Herring		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
662*724ba675SRob Herring		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
663*724ba675SRob Herring			GPIO_ACTIVE_LOW>;
664*724ba675SRob Herring
665*724ba675SRob Herring		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
666*724ba675SRob Herring			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
667*724ba675SRob Herring			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
668*724ba675SRob Herring		clock-names = "pll_a", "pll_a_out0", "mclk";
669*724ba675SRob Herring
670*724ba675SRob Herring		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
671*724ba675SRob Herring				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
672*724ba675SRob Herring
673*724ba675SRob Herring		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
674*724ba675SRob Herring					 <&tegra_car TEGRA30_CLK_EXTERN1>;
675*724ba675SRob Herring	};
676*724ba675SRob Herring
677*724ba675SRob Herring	thermal-zones {
678*724ba675SRob Herring		cpu-thermal {
679*724ba675SRob Herring			polling-delay-passive = <1000>; /* milliseconds */
680*724ba675SRob Herring			polling-delay = <5000>; /* milliseconds */
681*724ba675SRob Herring
682*724ba675SRob Herring			thermal-sensors = <&nct1008 1>;
683*724ba675SRob Herring
684*724ba675SRob Herring			trips {
685*724ba675SRob Herring				trip0: cpu-alert0 {
686*724ba675SRob Herring					/* throttle at 57C until temperature drops to 56.8C */
687*724ba675SRob Herring					temperature = <57000>;
688*724ba675SRob Herring					hysteresis = <200>;
689*724ba675SRob Herring					type = "passive";
690*724ba675SRob Herring				};
691*724ba675SRob Herring
692*724ba675SRob Herring				trip1: cpu-crit {
693*724ba675SRob Herring					/* shut down at 60C */
694*724ba675SRob Herring					temperature = <60000>;
695*724ba675SRob Herring					hysteresis = <2000>;
696*724ba675SRob Herring					type = "critical";
697*724ba675SRob Herring				};
698*724ba675SRob Herring			};
699*724ba675SRob Herring
700*724ba675SRob Herring			cooling-maps {
701*724ba675SRob Herring				map0 {
702*724ba675SRob Herring					trip = <&trip0>;
703*724ba675SRob Herring					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
704*724ba675SRob Herring							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
705*724ba675SRob Herring							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
706*724ba675SRob Herring							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
707*724ba675SRob Herring				};
708*724ba675SRob Herring			};
709*724ba675SRob Herring		};
710*724ba675SRob Herring	};
711*724ba675SRob Herring};
712