1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring 3*724ba675SRob Herring#include "tegra30-asus-nexus7-grouper-common.dtsi" 4*724ba675SRob Herring#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi" 5*724ba675SRob Herring 6*724ba675SRob Herring/ { 7*724ba675SRob Herring compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; 8*724ba675SRob Herring 9*724ba675SRob Herring gpio@6000d000 { 10*724ba675SRob Herring init-mode-3g-hog { 11*724ba675SRob Herring gpio-hog; 12*724ba675SRob Herring gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, 13*724ba675SRob Herring <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>, 14*724ba675SRob Herring <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>, 15*724ba675SRob Herring <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>, 16*724ba675SRob Herring <TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>, 17*724ba675SRob Herring <TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>, 18*724ba675SRob Herring <TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>, 19*724ba675SRob Herring <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>, 20*724ba675SRob Herring <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>, 21*724ba675SRob Herring <TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>, 22*724ba675SRob Herring <TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>, 23*724ba675SRob Herring <TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>, 24*724ba675SRob Herring <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>, 25*724ba675SRob Herring <TEGRA_GPIO(U, 3) GPIO_ACTIVE_HIGH>, 26*724ba675SRob Herring <TEGRA_GPIO(N, 1) GPIO_ACTIVE_HIGH>, 27*724ba675SRob Herring <TEGRA_GPIO(N, 2) GPIO_ACTIVE_HIGH>, 28*724ba675SRob Herring <TEGRA_GPIO(N, 0) GPIO_ACTIVE_HIGH>, 29*724ba675SRob Herring <TEGRA_GPIO(N, 3) GPIO_ACTIVE_HIGH>; 30*724ba675SRob Herring output-low; 31*724ba675SRob Herring }; 32*724ba675SRob Herring }; 33*724ba675SRob Herring 34*724ba675SRob Herring pinmux@70000868 { 35*724ba675SRob Herring state_default: pinmux { 36*724ba675SRob Herring lcd_dc1_pd2 { 37*724ba675SRob Herring nvidia,pins = "lcd_dc1_pd2"; 38*724ba675SRob Herring nvidia,function = "displaya"; 39*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 40*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 41*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring lcd_pwr2_pc6 { 44*724ba675SRob Herring nvidia,pins = "lcd_pwr2_pc6"; 45*724ba675SRob Herring nvidia,function = "displaya"; 46*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 47*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 48*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 49*724ba675SRob Herring }; 50*724ba675SRob Herring spi2_cs2_n_pw3 { 51*724ba675SRob Herring nvidia,pins = "spi2_cs2_n_pw3"; 52*724ba675SRob Herring nvidia,function = "spi2"; 53*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 54*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 55*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring dap3_din_pp1 { 58*724ba675SRob Herring nvidia,pins = "dap3_din_pp1"; 59*724ba675SRob Herring nvidia,function = "i2s2"; 60*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 61*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 62*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring spi1_sck_px5 { 65*724ba675SRob Herring nvidia,pins = "spi1_sck_px5"; 66*724ba675SRob Herring nvidia,function = "spi1"; 67*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 68*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 69*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 70*724ba675SRob Herring }; 71*724ba675SRob Herring pu5 { 72*724ba675SRob Herring nvidia,pins = "pu5"; 73*724ba675SRob Herring nvidia,function = "pwm2"; 74*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 75*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 76*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring spi1_miso_px7 { 79*724ba675SRob Herring nvidia,pins = "spi1_miso_px7"; 80*724ba675SRob Herring nvidia,function = "spi1"; 81*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 82*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 83*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 84*724ba675SRob Herring }; 85*724ba675SRob Herring spi2_mosi_px0 { 86*724ba675SRob Herring nvidia,pins = "spi2_mosi_px0"; 87*724ba675SRob Herring nvidia,function = "spi2"; 88*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 89*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 90*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring clk3_req_pee1 { 93*724ba675SRob Herring nvidia,pins = "clk3_req_pee1"; 94*724ba675SRob Herring nvidia,function = "dev3"; 95*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 96*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 97*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 98*724ba675SRob Herring }; 99*724ba675SRob Herring ulpi_nxt_py2 { 100*724ba675SRob Herring nvidia,pins = "ulpi_nxt_py2"; 101*724ba675SRob Herring nvidia,function = "uartd"; 102*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 103*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 104*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring ulpi_stp_py3 { 107*724ba675SRob Herring nvidia,pins = "ulpi_stp_py3"; 108*724ba675SRob Herring nvidia,function = "uartd"; 109*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 110*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 111*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 112*724ba675SRob Herring }; 113*724ba675SRob Herring kb_row7_pr7 { 114*724ba675SRob Herring nvidia,pins = "kb_row7_pr7"; 115*724ba675SRob Herring nvidia,function = "kbc"; 116*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 117*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 118*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring pu4 { 121*724ba675SRob Herring nvidia,pins = "pu4"; 122*724ba675SRob Herring nvidia,function = "pwm1"; 123*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 124*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 125*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 126*724ba675SRob Herring }; 127*724ba675SRob Herring pu3 { 128*724ba675SRob Herring nvidia,pins = "pu3"; 129*724ba675SRob Herring nvidia,function = "rsvd4"; 130*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 131*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 132*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 133*724ba675SRob Herring }; 134*724ba675SRob Herring kb_row15_ps7 { 135*724ba675SRob Herring nvidia,pins = "kb_row15_ps7"; 136*724ba675SRob Herring nvidia,function = "kbc"; 137*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 139*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 140*724ba675SRob Herring }; 141*724ba675SRob Herring dap3_sclk_pp3 { 142*724ba675SRob Herring nvidia,pins = "dap3_sclk_pp3"; 143*724ba675SRob Herring nvidia,function = "i2s2"; 144*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 145*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 146*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 147*724ba675SRob Herring }; 148*724ba675SRob Herring kb_row3_pr3 { 149*724ba675SRob Herring nvidia,pins = "kb_row3_pr3", 150*724ba675SRob Herring "kb_row13_ps5"; 151*724ba675SRob Herring nvidia,function = "kbc"; 152*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 153*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 154*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring kb_row13_ps5 { 157*724ba675SRob Herring nvidia,pins = "kb_row13_ps5"; 158*724ba675SRob Herring nvidia,function = "kbc"; 159*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 160*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 161*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 162*724ba675SRob Herring }; 163*724ba675SRob Herring gmi_wp_n_pc7 { 164*724ba675SRob Herring nvidia,pins = "gmi_wp_n_pc7", 165*724ba675SRob Herring "gmi_wait_pi7", 166*724ba675SRob Herring "gmi_cs4_n_pk2", 167*724ba675SRob Herring "gmi_cs3_n_pk4"; 168*724ba675SRob Herring nvidia,function = "rsvd1"; 169*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 170*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 171*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 172*724ba675SRob Herring }; 173*724ba675SRob Herring gmi_cs6_n_pi3 { 174*724ba675SRob Herring nvidia,pins = "gmi_cs6_n_pi3"; 175*724ba675SRob Herring nvidia,function = "gmi"; 176*724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 177*724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 178*724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 179*724ba675SRob Herring }; 180*724ba675SRob Herring }; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring i2c@7000c500 { 184*724ba675SRob Herring proximity-sensor@28 { 185*724ba675SRob Herring compatible = "microchip,cap1106"; 186*724ba675SRob Herring reg = <0x28>; 187*724ba675SRob Herring 188*724ba675SRob Herring /* 189*724ba675SRob Herring * Binding doesn't support specifying linux,input-type 190*724ba675SRob Herring * and this results in unwanted key-presses handled by 191*724ba675SRob Herring * applications, hence keep it disabled for now. 192*724ba675SRob Herring */ 193*724ba675SRob Herring status = "disabled"; 194*724ba675SRob Herring 195*724ba675SRob Herring interrupt-parent = <&gpio>; 196*724ba675SRob Herring interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>; 197*724ba675SRob Herring 198*724ba675SRob Herring linux,keycodes = <KEY_RESERVED>, 199*724ba675SRob Herring <KEY_RESERVED>, 200*724ba675SRob Herring <KEY_RESERVED>, 201*724ba675SRob Herring <KEY_RESERVED>, 202*724ba675SRob Herring <KEY_RESERVED>, 203*724ba675SRob Herring <SW_FRONT_PROXIMITY>; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring nfc@2a { 207*724ba675SRob Herring compatible = "nxp,pn544-i2c"; 208*724ba675SRob Herring reg = <0x2a>; 209*724ba675SRob Herring 210*724ba675SRob Herring interrupt-parent = <&gpio>; 211*724ba675SRob Herring interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>; 212*724ba675SRob Herring 213*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 214*724ba675SRob Herring firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; 215*724ba675SRob Herring }; 216*724ba675SRob Herring }; 217*724ba675SRob Herring 218*724ba675SRob Herring display-panel { 219*724ba675SRob Herring enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; 220*724ba675SRob Herring 221*724ba675SRob Herring panel-timing { 222*724ba675SRob Herring clock-frequency = <81750000>; 223*724ba675SRob Herring hactive = <800>; 224*724ba675SRob Herring vactive = <1280>; 225*724ba675SRob Herring hfront-porch = <64>; 226*724ba675SRob Herring hback-porch = <128>; 227*724ba675SRob Herring hsync-len = <64>; 228*724ba675SRob Herring vsync-len = <1>; 229*724ba675SRob Herring vfront-porch = <5>; 230*724ba675SRob Herring vback-porch = <2>; 231*724ba675SRob Herring }; 232*724ba675SRob Herring }; 233*724ba675SRob Herring}; 234